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CN101499470A - Power source layout of integrated circuit and its design method - Google Patents

Power source layout of integrated circuit and its design method Download PDF

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CN101499470A
CN101499470A CNA2008100053338A CN200810005333A CN101499470A CN 101499470 A CN101499470 A CN 101499470A CN A2008100053338 A CNA2008100053338 A CN A2008100053338A CN 200810005333 A CN200810005333 A CN 200810005333A CN 101499470 A CN101499470 A CN 101499470A
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metal
power supply
power
integrated circuit
layer
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CN101499470B (en
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庄佳霖
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Realtek Semiconductor Corp
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Abstract

The invention discloses a power layout of an integrated circuit, a method for designing the power layout of the integrated circuit and a method for constructing the power layout of the integrated circuit. The power supply layout mode utilizes a plurality of metal stems with consistent line width to form a power supply network and a power supply ring. In particular, the power supply ring includes a plurality of metal rings formed by a relatively densely packed metal stem in the metal stem, the power supply ring is configured to receive power and distribute the power to electronic components of the integrated circuit.

Description

集成电路电源布局及其设计方法 Integrated circuit power supply layout and its design method

技术领域 technical field

本发明涉及集成电路(Integrated circuit,IC)的电源布局的设计,并且特别地,本发明涉及用于集成电路内的电源供应网络(Power mesh)与电源供应环(Power ring)的布局设计。The present invention relates to the design of the power supply layout of an integrated circuit (Integrated circuit, IC), and in particular, the present invention relates to the layout design of a power supply network (Power mesh) and a power supply ring (Power ring) used in the integrated circuit.

背景技术 Background technique

请参阅图1A,图1A提供传统的集成电路裸晶(IC die)(或芯片)1的简化的截面视图。如图1A所示,该晶体电路裸晶1包含一层半导体层(Semiconductor layer)10、六层由底至顶起算的连续的金属层(Metal layer)(121~126)、分别形成于两相邻金属层之间的数层绝缘层(Insulating layer)14以及一层钝化层(Passivation layer)16。该半导体层10用来形成例如晶体管等电子元件(Electronic device)(未示出),并且也可能用来对这些电子元件之间电气连接做布线(Routing)。为了达成最小芯片面积以及最快电路速度,通常仅有较短的电气连接形成于该半导体层10上。该金属层(121~126)即是针对其余的电气连接而提供。金属层所采用的层数需视实际接线布线的复杂程度而定。例如,八层金属层甚至更多层金属层即被广泛采用在接线布线复杂程度高的集成电路设计上。Please refer to FIG. 1A , which provides a simplified cross-sectional view of a conventional integrated circuit die (IC die) (or chip) 1 . As shown in FIG. 1A, the crystal circuit bare die 1 includes a semiconductor layer (Semiconductor layer) 10, six consecutive metal layers (Metal layer) (Metal layer) (121-126) from bottom to top, respectively formed in two phases There are several layers of insulating layers (Insulating layer) 14 and a layer of passivation layer (Passivation layer) 16 between adjacent metal layers. The semiconductor layer 10 is used to form electronic devices (not shown) such as transistors, and may also be used for routing electrical connections between these electronic devices. In order to achieve the smallest chip area and the fastest circuit speed, usually only short electrical connections are formed on the semiconductor layer 10 . The metal layers (121-126) are provided for the remaining electrical connections. The number of layers used in the metal layer depends on the complexity of the actual wiring. For example, eight metal layers or even more metal layers are widely used in the design of integrated circuits with high wiring complexity.

关于在该金属层(121~126)上的接线布线,电源分布网络(Powerdistribution network)(未示出)可形成在第一层金属层121处,并且耦接至该电子元件,其中电源分布网络可由多个具有较细线宽的金属轨(Metal rail)所组成。Regarding the wiring wiring on the metal layers (121-126), a power distribution network (Powerdistribution network) (not shown) may be formed at the first metal layer 121 and coupled to the electronic components, wherein the power distribution network It can be composed of multiple metal rails (Metal rail) with thinner line width.

请参阅图1B,图1B绘示形成在该集成电路裸晶1的较顶层金属层处的接线布线以及其所在的金属层。Please refer to FIG. 1B . FIG. 1B shows the wires formed on the top metal layer of the integrated circuit die 1 and the metal layer where they are located.

如图1B所示,电源供应网络18形成在第六层金属层126以及第五层金属层125处。该电源供应网络18由多个其线宽比金属轨还宽的金属干(MetalAs shown in FIG. 1B , the power supply network 18 is formed at the sixth metal layer 126 and the fifth metal layer 125 . The power supply network 18 consists of a plurality of metal stems (Metal

trunk)(182、184)所组成。除此之外,形成在不同金属层(126、125)处的金属干(182、184)通过形成在绝缘层14处的介层窗(Via)142做相互连接。同样通过介层窗142,该电源供应网络18与该电源分布网络连接。该金属干(182、184)区分为作为连接电源(Power)的电源金属干182以及连接接地(Ground)的接地金属干184。在同一层金属层,电源金属干182与接地金属干184交错排列。形成在第六层126金属层处的金属干(182、184)与形成在第五层金属层125处的金属干(182、184)相互垂直。形成在第六层126处的电源金属干182仅连接至形成在第五层125处的电源金属干182,并且形成在第六层126处的接地金属干184仅连接至形成在第五层125处的接地金属干184。trunk) (182, 184). In addition, metal stems ( 182 , 184 ) formed at different metal layers ( 126 , 125 ) are interconnected through vias (Via) 142 formed at insulating layer 14 . Also via vias 142, the power supply network 18 is connected to the power distribution network. The metal stems ( 182 , 184 ) are divided into a power metal stem 182 connected to a power supply (Power) and a ground metal stem 184 connected to a ground (Ground). On the same metal layer, the power metal stems 182 and the ground metal stems 184 are alternately arranged. The metal stems ( 182 , 184 ) formed at the sixth metal layer 126 are perpendicular to the metal stems ( 182 , 184 ) formed at the fifth metal layer 125 . The power metal stem 182 formed at the sixth layer 126 is only connected to the power metal stem 182 formed at the fifth layer 125, and the ground metal stem 184 formed at the sixth layer 126 is connected only to the power metal stem 182 formed at the fifth layer 125. The ground metal stem 184 at the place.

请再参阅图1B,电源供应环17(所绘示乃电源供应环17的一小段)可形成在第六层金属层126处。在实务上,该电源供应环17由两个其线宽比金属干(182、184)还宽的金属环(172、174)所组成。该两个金属环(172、174)区分为连接电源的电源金属环172以及连接接地的接地金属环174。形成在第六层金属层126处的金属环(172、174)将围绕同样形成在第六层金属层126处的金属干(182、184)以形成环状结构(未示出)。该电源供应环17用以接收电源,并且将该电源经由该电源供应网络18传导至该电源分布网络,该电源分布网络用以分配该电源给该电子元件。Referring to FIG. 1B again, the power supply ring 17 (shown is a small section of the power supply ring 17 ) can be formed at the sixth metal layer 126 . In practice, the power supply ring 17 is composed of two metal rings ( 172 , 174 ) whose wire width is wider than the metal stems ( 182 , 184 ). The two metal rings ( 172 , 174 ) are divided into a power metal ring 172 connected to a power source and a ground metal ring 174 connected to a ground. The metal rings (172, 174) formed at the sixth metal layer 126 will surround the metal stems (182, 184) also formed at the sixth metal layer 126 to form a ring structure (not shown). The power supply ring 17 is used to receive power, and transmit the power to the power distribution network via the power supply network 18, and the power distribution network is used to distribute the power to the electronic components.

在设计集成电路时,如上述的电源规划需收集各式规格以配合工艺、成品率及资源占用,等的要求。然而,由于所需配合的细节甚多,因此必须由经验丰富的布局工程师(Layout engineer)来实现的,如此将造成庞大的人力负担。When designing an integrated circuit, various specifications need to be collected for the power planning mentioned above to meet the requirements of process, yield and resource occupation, etc. However, due to the many details that need to be coordinated, it must be realized by an experienced layout engineer, which will cause a huge manpower burden.

发明内容 Contents of the invention

因此,本发明的一范畴在于提供一种集成电路裸晶(或芯片)的电源布局及其设计方法,该集成电路裸晶并且整合一电源供应网络与电源供应环,并且特别地,该电源供应网络与该电源供应环之间的阻抗差异可以缩小,且该电源供应网络与该电源供应环的布线的壅塞可以有效舒缓。Therefore, one scope of the present invention is to provide a power supply layout of an integrated circuit die (or chip) and a design method thereof, which integrates a power supply network and a power supply ring, and in particular, the power supply The impedance difference between the network and the power supply ring can be reduced, and the congestion of the wiring between the power supply network and the power supply ring can be effectively alleviated.

根据本发明的一较佳具体实施例的集成电路裸晶,其包含一半导体层、多个形成于该半导体层上的电子元件、N层由底至顶起算的连续的金属层、电源分布网络、电源供应网络以及电源供应环。该金属层彼此绝缘,且形成于该半导体层上或之上,N为正整数。该电源分布网络包含多个金属轨,并且耦接至该电子元件。该电源供应网络包含多个金属干,该金属干形成在第N层金属层至第i层金属层处,该金属干通过多个第一介层窗相互连接并且通过多个第二介层窗与该金属轨连接,i为小于N的正整数。该电源供应环包含多个金属环,该金属环由该金属干中部分密集聚集的金属干所形成并与该电源供应网络相互连接。该电源供应环用以接收电源并且将该电源经由该电源供应网络传导至该电源分布网络,该电源分布网络再将该电源分配给该电子元件。According to a preferred embodiment of the present invention, an integrated circuit die comprises a semiconductor layer, a plurality of electronic components formed on the semiconductor layer, N layers of continuous metal layers counted from bottom to top, and a power distribution network , power supply network and power supply ring. The metal layers are insulated from each other and formed on or above the semiconductor layer, and N is a positive integer. The power distribution network includes a plurality of metal rails and is coupled to the electronic component. The power supply network includes a plurality of metal stems, the metal stems are formed at the N-th metal layer to the i-th metal layer, and the metal stems are connected to each other through a plurality of first vias and through a plurality of second vias It is connected with the metal rail, and i is a positive integer smaller than N. The power supply ring includes a plurality of metal rings, the metal rings are formed by some metal stems densely gathered in the metal stems and are connected to the power supply network. The power supply ring is used for receiving power and conducting the power to the power distribution network through the power supply network, and the power distribution network then distributes the power to the electronic components.

于本发明的另一较佳具体实施例中,该金属环并且形成在第(N-1)层金属层至第i层金属层处。该金属环并且通过多个第三介层窗相互连接。In another preferred embodiment of the present invention, the metal ring is also formed at the (N-1)-th metal layer to the i-th metal layer. The metal rings are also connected to each other through a plurality of third vias.

关于本发明的优点与精神可以通过以下的发明详述及附图得到进一步的了解。The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

附图说明 Description of drawings

图1A为传统的集成电路裸晶1的简化的截面视图。FIG. 1A is a simplified cross-sectional view of a conventional integrated circuit die 1 .

图1B为示意地绘示出形成在该集成电路裸晶1的金属层(126、125)处的接线布线。FIG. 1B schematically illustrates the wiring lines formed at the metal layers ( 126 , 125 ) of the IC die 1 .

图2A为根据本发明的一较佳具体实施例的集成电路裸晶2的简化的截面视图。FIG. 2A is a simplified cross-sectional view of an integrated circuit die 2 according to a preferred embodiment of the present invention.

图2B为示意地绘示出形成在该集成电路裸晶2的金属层(228、227)处的接线布线。FIG. 2B schematically illustrates the wires formed at the metal layers ( 228 , 227 ) of the IC die 2 .

图3为根据本发明的用以设计集成电路裸晶的方法的流程图。FIG. 3 is a flowchart of a method for designing an integrated circuit die according to the present invention.

图4为根据本发明于调整金属布线的疏密程度后,所产生的电源供应环一角的实际设计图案例。FIG. 4 is an example of an actual design diagram of a corner of a power supply ring generated after adjusting the density of the metal wiring according to the present invention.

图5为应用本发明并以计算机自动化所形成电源供应环(边缘自动布线)的实际设计图案例。Fig. 5 is an example of an actual design diagram of a power supply ring (edge automatic wiring) formed by applying the present invention and using computer automation.

附图标记说明Explanation of reference signs

1、2:集成电路裸晶             10、20:半导体层1, 2: Integrated circuit bare crystal 10, 20: Semiconductor layer

121~126以及221~228:金属层121~126 and 221~228: metal layer

14、24:绝缘层                 142:介层窗14, 24: insulating layer 142: via window

16、26:钝化层                 17、27:电源供应环16, 26: Passivation layer 17, 27: Power supply ring

172、272:电源金属环           174、274:接地金属环172, 272: Metal ring for power supply 174, 274: Metal ring for grounding

18、28:电源供应网络           182、282:电源金属干18, 28: Power supply network 182, 282: Power metal dry

184、284:接地金属干  242:第一介层窗184, 284: Ground metal stem 242: First via

244:第三介层窗       S30~S36:流程步骤244: Third via window S30~S36: Process steps

具体实施方式 Detailed ways

以下将详述本发明的较佳具体实施例,藉以充分解说本发明的特征、精神、优点以及实施上的简便性。Preferred specific embodiments of the present invention will be described in detail below, so as to fully illustrate the features, spirit, advantages and simplicity of implementation of the present invention.

请参阅图2A,图2A提供根据本发明的一较佳具体实施例的集成电路裸晶(或芯片)2的简化的截面视图。如图2A所示,该晶体电路裸晶2包含一层半导体层20、八层由底至顶起算的连续的金属层(221~228)、分别形成于两相邻金属层之间的数层绝缘层24以及一层钝化层26。该半导体层20用来形成例如晶体管等电子元件(未示出)。金属层所采用的层数需视实际接线布线的复杂程度而定。因此,图2A所披露的八层金属层仅是为了说明简便,而非对本发明作为限制。Please refer to FIG. 2A, which provides a simplified cross-sectional view of an integrated circuit die (or chip) 2 according to a preferred embodiment of the present invention. As shown in FIG. 2A, the crystal circuit die 2 includes a semiconductor layer 20, eight consecutive metal layers (221-228) counted from bottom to top, and several layers respectively formed between two adjacent metal layers. An insulating layer 24 and a passivation layer 26 . The semiconductor layer 20 is used to form electronic components such as transistors (not shown). The number of layers used in the metal layer depends on the complexity of the actual wiring. Therefore, the eight metal layers disclosed in FIG. 2A are only for the convenience of illustration, rather than limiting the present invention.

关于在该金属层(221~228)上的接线布线,电源分布网络(未示出)形成在第一层金属层221处,并且耦接至该电子元件。同样地,该电源分布网络由多个具有第一线宽的金属轨所组成,该金属轨即形成在第一层金属层221处,并且耦接至该电子元件。Regarding the wiring wiring on the metal layers (221-228), a power distribution network (not shown) is formed at the first metal layer 221 and coupled to the electronic components. Likewise, the power distribution network is composed of a plurality of metal tracks with a first line width, and the metal tracks are formed at the first metal layer 221 and coupled to the electronic component.

请参阅图2B,图2B示意地绘示出形成在较顶层金属层处的接线布线以及其所在的金属层。Please refer to FIG. 2B . FIG. 2B schematically illustrates the wiring lines formed at the top metal layer and the metal layer where they are located.

如图2B所示,电源供应网络28形成在第N层金属层(图2B所绘示的第八层金属层228)至第i层金属层(图2B仅绘示出第七层金属层227)处。于一具体实施例中,N为大于或等于6的整数,i为范围从(N-3)至(N-1)中的整数。As shown in FIG. 2B , the power supply network 28 is formed from the Nth metal layer (the eighth metal layer 228 shown in FIG. 2B ) to the i-th metal layer (only the seventh metal layer 227 is shown in FIG. 2B ). ) place. In a specific embodiment, N is an integer greater than or equal to 6, and i is an integer ranging from (N-3) to (N-1).

该电源供应网络28由多个具有第二线宽的金属干(282、284)所组成,并且形成在不同金属层(例如图2B中所示第八层金属层228与第七层金属层227)处的金属干(282、284)通过形成在绝缘层24处的第一介层窗242做相互连接。同样通过形成在绝缘层24处的第二介层窗(未示出),该电源供应网络28与该电源分布网络连接(未示出)。在实务上,若采用八层金属层,金属干的布线会运用到第八层及第七层金属层,针对复杂的接线布线,甚至会运用到第六层及第五层金属层。采用六层金属层,金属干的布线一般会运用到第六层及第五层金属层。The power supply network 28 is composed of a plurality of metal stems (282, 284) having a second line width, and formed on different metal layers (such as the eighth metal layer 228 and the seventh metal layer 227 shown in FIG. 2B ). The metal stems ( 282 , 284 ) at are connected to each other through the first via 242 formed at the insulating layer 24 . Also via a second via (not shown) formed at the insulating layer 24, the power supply network 28 is connected to the power distribution network (not shown). In practice, if eight metal layers are used, the wiring of the metal trunk will be applied to the eighth and seventh metal layers. For complex wiring and wiring, it will even be applied to the sixth and fifth metal layers. Six metal layers are used, and the wiring of the metal stem is generally applied to the sixth and fifth metal layers.

于一具体实施例中,该第二线宽比该第一线宽还宽。也就是说,在此实施例中,该金属干(282、284)的线宽得以较该金属轨的线宽还宽。In a specific embodiment, the second line width is wider than the first line width. That is to say, in this embodiment, the line width of the metal stem ( 282 , 284 ) can be wider than the line width of the metal track.

同样示于图2B,该金属干(282、284)区分为作为连接电源的电源金属干282以及连接接地的接地金属干284。在同一层金属层,电源金属干182与接地金属干184交错排列。形成在相邻层金属层(例如,第八层金属层228与第七层金属层227)处的金属干(282、284)相互垂直。形成在相邻层金属层(例如,第八层金属层228与第七层金属层227)处的电源金属干282相互连接,并且形成在相邻层金属层(例如,第八层金属层228与第七层金属层227)处的接地金属干282相互连接。Also shown in FIG. 2B , the metal stems ( 282 , 284 ) are divided into a power metal stem 282 for connecting to a power source and a grounding metal stem 284 for connecting to a ground. On the same metal layer, the power metal stems 182 and the ground metal stems 184 are alternately arranged. The metal stems ( 282 , 284 ) formed at adjacent metal layers (eg, the eighth metal layer 228 and the seventh metal layer 227 ) are perpendicular to each other. The power supply metal stems 282 formed on adjacent metal layers (for example, the eighth metal layer 228 and the seventh metal layer 227) are connected to each other, and formed on the adjacent metal layers (for example, the eighth metal layer 228 It is connected with the ground metal stem 282 at the seventh metal layer 227).

请再参阅图2B,电源供应环27(所绘示乃电源供应环27之一小段)可形成在最顶层金属层228处。该电源供应环27可由多个具有该第二线宽的金属环(272、274)所组成。也就是说,于本发明一具体实施例中,该金属环(272、274)的线宽得以与该金属干(282、284)的线宽相同。本发明便是利用调整该金属干(282、284)之间的疏密度以形成金属环(272、274)所需的结构。经由定义金属干(282、284)而形成的电源供应环27便可接收电源,并且将该电源经由该电源供应网络28传导至该电源分布网络。该电源分布网络用以分配该电源给该电子元件。Referring to FIG. 2B again, the power supply ring 27 (shown as a small section of the power supply ring 27 ) can be formed at the topmost metal layer 228 . The power supply ring 27 may be composed of a plurality of metal rings ( 272 , 274 ) having the second line width. That is to say, in an embodiment of the present invention, the line width of the metal rings (272, 274) can be the same as the line width of the metal stems (282, 284). The present invention uses adjusting the density between the metal stems (282, 284) to form the required structure of the metal rings (272, 274). A power supply ring 27 formed by defining metal stems (282, 284) receives power and conducts it via the power supply network 28 to the power distribution network. The power distribution network is used to distribute the power to the electronic components.

根据本发明的接线布线技术,该电源供应网络28与该电源供应环27之间的阻抗差异将因此缩小,进而避免金属布线的烧毁。此外,为了舒缓该电源供应网络28与该电源供应环27的布线的壅塞(Congestion),于本发明的另一较佳具体实施例中,同样示于图2B,该金属环(272、274)亦可形成于第(N-1)层金属层至第i层金属层处。According to the wiring and wiring technology of the present invention, the impedance difference between the power supply network 28 and the power supply ring 27 will be reduced, thereby avoiding the burning of the metal wiring. In addition, in order to alleviate the congestion (Congestion) of the wiring of the power supply network 28 and the power supply ring 27, in another preferred embodiment of the present invention, also shown in FIG. 2B, the metal ring (272, 274) It can also be formed on the (N-1)th metal layer to the i-th metal layer.

同样依循本发明的特征、精神及优点,本发明亦披露一种用以设计集成电路裸晶(或芯片)的方法3。基本上,该集成电路裸晶包含半导体层以及N层由底至顶起算的连续的金属层,其中N可为大于或等于6的正整数。该金属层彼此绝缘,并且形成于该半导体层上或之上。以下将详述根据本发明的集成电路裸晶设计方法3的流程步骤。Also following the features, spirit and advantages of the present invention, the present invention also discloses a method 3 for designing an integrated circuit die (or chip). Basically, the integrated circuit die includes a semiconductor layer and N layers of continuous metal layers counted from bottom to top, wherein N can be a positive integer greater than or equal to 6. The metal layers are insulated from each other and formed on or over the semiconductor layer. The process steps of the integrated circuit die design method 3 according to the present invention will be described in detail below.

请参阅图3,首先,该设计方法3执行步骤S30,配置多个电子元件于该半导体层上。Please refer to FIG. 3 , first, the design method 3 executes step S30 , disposing a plurality of electronic components on the semiconductor layer.

接着,该设计方法3执行步骤S32,在第一层金属层处,配置电源分布网络。该电源分布网络由多个具有第一线宽的金属轨所组成,并且耦接至该电子元件。Next, the design method 3 executes step S32, configuring a power distribution network at the first metal layer. The power distribution network is composed of a plurality of metal tracks with a first line width, and is coupled to the electronic component.

接着,该设计方法3执行步骤S34,在第N层金属层至第i层金属层处,配置该电源供应网络,其中假设i为范围从(N-3)至(N-1)中的整数。该电源供应网络可由多个具有第二线宽的金属干所组成,而且可将该第二线宽设定比该第一线宽宽。该金属干通过多个第一介层窗相互连接,并且通过多个第二介层窗与该金属轨连接。Next, the design method 3 executes step S34, configuring the power supply network at the N-th metal layer to the i-th metal layer, wherein it is assumed that i is an integer ranging from (N-3) to (N-1) . The power supply network can be composed of a plurality of metal stems with a second line width, and the second line width can be set wider than the first line width. The metal stems are connected to each other through a plurality of first vias, and connected to the metal rails through a plurality of second vias.

最后,该设计方法3执行步骤S36,在第N层金属层处,调整该金属干之间的疏密度以形成电源供应环所需的结构。Finally, the design method 3 executes step S36 , at the Nth metal layer, the density between the metal stems is adjusted to form the required structure of the power supply ring.

为了舒缓该电源供应网络与该电源供应环的布线的壅塞,该设计方法3进一步在第(N-1)层金属层至第i层金属层处,配置该金属环。In order to alleviate the congestion of the power supply network and the wiring of the power supply ring, the design method 3 further configures the metal ring at the (N-1)th metal layer to the i-th metal layer.

在本发明的具体实施例中,由于可以使用相同线宽的金属布线以产生所需要的电源供应环,因此便得以在用户定义后,由计算机自动化的方式调整金属布线的疏密程度来形成所需要的电源供应环。如此一来,将不再需要为了不同的电路布局,花费额外的人力为电源供应环另外做布线。In a specific embodiment of the present invention, since the metal wiring with the same line width can be used to generate the required power supply ring, the density of the metal wiring can be automatically adjusted by the computer to form the required power supply ring. required power supply ring. In this way, it is no longer necessary to spend extra manpower to make additional wiring for the power supply ring for different circuit layouts.

请参阅图4及图5。图4为本发明于调整金属布线的疏密程度后,所产生的电源供应环一角的实际设计图。而图5为因应不同的电路布局,计算机自动化所形成电源供应环(边缘自动布线)的实际设计图。Please refer to Figure 4 and Figure 5. FIG. 4 is an actual design diagram of a corner of the power supply ring produced by adjusting the density of the metal wiring according to the present invention. FIG. 5 is an actual design diagram of a power supply ring (edge automatic wiring) formed by computer automation in response to different circuit layouts.

通过以上较佳具体实施例的详述,希望能更加清楚描述本发明的特征与精神,而并非以上述所披露的较佳具体实施例来对本发明的范畴加以限制。相反地,其目的是希望能涵盖各种改变及具相等性的安排于本发明所欲申请的专利范围的范畴内。因此,本发明所申请的专利范围的范畴应该根据上述的说明作最宽广的解释,以致使其涵盖所有可能的改变以及具相等性的安排。Through the detailed description of the preferred specific embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention. Therefore, the scope of the claimed scope of the present invention should be interpreted in the broadest way based on the above description, so as to cover all possible changes and equivalent arrangements.

Claims (15)

1.一种集成电路的电源布局,包含:1. A power supply layout of an integrated circuit, comprising: 半导体层;semiconductor layer; 多个电子元件,该电子元件形成于该半导体层上;a plurality of electronic components formed on the semiconductor layer; N层由底至顶起算的连续的金属层,该金属层彼此绝缘且形成于该半导体层上或之上,N为正整数;N layers are continuous metal layers counted from bottom to top, the metal layers are insulated from each other and formed on or over the semiconductor layer, N is a positive integer; 电源分布网络,该电源分布网络包含多个金属轨,并且耦接至该电子元件;a power distribution network comprising a plurality of metal rails and coupled to the electronic component; 电源供应网络,该电源供应网络包含多个金属干,该金属干形成在第N层金属层至第i层金属层处,该金属干通过多个第一介层窗相互连接并且通过多个第二介层窗与该金属轨连接,i为小于N的正整数;以及A power supply network, the power supply network includes a plurality of metal stems, the metal stems are formed at the Nth metal layer to the i-th metal layer, the metal stems are connected to each other through a plurality of first vias and are connected to each other through a plurality of first vias The second via is connected to the metal track, i is a positive integer less than N; and 电源供应环,该电源供应环包含多个金属环,该金属环由该金属干中部分密集聚集的金属干所形成,该电源供应环用以接收电源并且将该电源经由该电源供应网络传导至该电源分布网络,该电源分布网络再将该电源分配给该电子元件。The power supply ring, the power supply ring includes a plurality of metal rings, the metal rings are formed by the densely gathered metal stems in the metal stem, and the power supply ring is used to receive power and conduct the power through the power supply network to The power distribution network distributes the power to the electronic components. 2.如权利要求1所述的集成电路的电源布局,其中该金属轨具有第一线宽而该金属干具有第二线宽,且该第二线宽大于该第一线宽。2. The power supply layout of an integrated circuit as claimed in claim 1, wherein the metal track has a first line width and the metal stem has a second line width, and the second line width is larger than the first line width. 3.如权利要求1所述的集成电路的电源布局,其中该金属轨形成在第一层金属层处。3. The power supply layout of an integrated circuit as claimed in claim 1, wherein the metal track is formed at the first metal layer. 4.如权利要求1所述的集成电路的电源布局,其中该电源供应环围绕该电源供应网络。4. The power supply layout of an integrated circuit as claimed in claim 1, wherein the power supply ring surrounds the power supply network. 5.一种用以设计集成电路的电源布局的方法,该集成电路裸晶包含半导体层以及N层由底至顶起算的连续的金属层,该金属层彼此绝缘且形成于该半导体层上或之上,N为正整数,该方法包含下列步骤:5. A method for designing a power supply layout of an integrated circuit, the integrated circuit die comprising a semiconductor layer and N layers of continuous metal layers from bottom to top, the metal layers are insulated from each other and formed on the semiconductor layer or Above, N is a positive integer, and the method includes the following steps: 配置多个电子元件于该半导体层上;disposing a plurality of electronic components on the semiconductor layer; 在第一层金属层处,配置电源分布网络,该电源分布网络包含多个金属轨,该金属轨耦接至该电子元件;At the first metal layer, a power distribution network is configured, the power distribution network includes a plurality of metal rails, and the metal rails are coupled to the electronic component; 在第N层金属层至第i层金属层处,配置电源供应网络,该电源供应网络包含多个第一金属干,该第一金属干通过多个第一介层窗相互连接并且通过多个第二介层窗与该金属轨连接,i为小于N的正整数;以及A power supply network is configured at the N-th metal layer to the i-th metal layer, and the power supply network includes a plurality of first metal stems, and the first metal stems are connected to each other through a plurality of first vias and through a plurality of The second via is connected to the metal track, i is a positive integer less than N; and 调整该电源供应网络周围的该金属干间的疏密程度,以形成电源供应环,该电源供应环包含多个金属环,该电源供应环用以接收电源并且将该电源经由该电源供应网络传导至该电源分布网络,该电源分布网络再将该电源分配给该电子元件。Adjusting the density of the metal stem around the power supply network to form a power supply ring, the power supply ring includes a plurality of metal rings, the power supply ring is used to receive power and conduct the power through the power supply network to the power distribution network, and the power distribution network then distributes the power to the electronic components. 6.如权利要求5所述的方法,其中N大于或等于6。6. The method of claim 5, wherein N is greater than or equal to six. 7.如权利要求5所述的方法,其中该金属轨具有第一线宽而该金属干具有第二线宽,且该第二线宽大于该第一线宽。7. The method of claim 5, wherein the metal track has a first line width and the metal stem has a second line width, and the second line width is greater than the first line width. 8.如权利要求5所述的方法,其中i的范围为自(N-3)至(N-1)。8. The method of claim 5, wherein i ranges from (N-3) to (N-1). 9.如权利要求8所述的方法,其中该金属环形成于第N层金属层至第i层金属层处。9. The method as claimed in claim 8, wherein the metal ring is formed at the N-th metal layer to the i-th metal layer. 10.如权利要求5所述的方法,其中在第j层金属层处的该金属干垂直于在第(j-1)层金属层处的该金属干,j大于等于(i+1)小于等于N的正整数。10. The method according to claim 5, wherein the metal stem at the jth metal layer is perpendicular to the metal stem at the (j-1)th metal layer, and j is greater than or equal to (i+1) less than A positive integer equal to N. 11.如权利要求8所述的方法,其中形成该电源供应环的该金属干的布线密度大于该电源供应网络的该金属干的布线密度。11. The method of claim 8, wherein the wiring density of the metal stems forming the power supply ring is greater than the wiring density of the metal stems of the power supply network. 12.一种建构集成电路的电源布局的方法,该方法包括下例步骤:12. A method for constructing a power supply layout of an integrated circuit, the method comprising the following steps: 配置电源供应网络,该电源供应网络包括多个金属布线;以及configuring a power supply network comprising a plurality of metal traces; and 调整该电源供应网络周围的该金属布线间的疏密程度,以形成电源供应环,用以接收电源;adjusting the density of the metal wiring around the power supply network to form a power supply ring for receiving power; 其中,该金属布线间的该疏密程度由用户定义后,以计算机自动化的方式执行。Wherein, the degree of density between the metal wirings is defined by the user and then executed in a computer-automatic manner. 13.如权利要求12所述的方法,其中该电源供应网络及该电源供应环形成于该集成电路的多个金属层。13. The method of claim 12, wherein the power supply network and the power supply ring are formed on metal layers of the integrated circuit. 14.如权利要求12所述的方法,其中形成该电源供应环的该金属布线较该电源供应网络的该金属布线为稠密。14. The method of claim 12, wherein the metal wiring forming the power supply ring is denser than the metal wiring of the power supply network. 15.如权利要求12所述的方法,其中该计算机自动化的方式为用于该电源供应网络边缘的自动布线,以形成该电源供应环。15. The method as claimed in claim 12, wherein the computer-automated means is automatic wiring for the edge of the power supply network to form the power supply ring.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237356A (en) * 2010-05-06 2011-11-09 台湾积体电路制造股份有限公司 Integrated circuit and its power supply layout and power supply layout method
CN104794253A (en) * 2014-01-17 2015-07-22 京微雅格(北京)科技有限公司 Layout method and device capable of achieving clean supply for chip interior analog modules

Family Cites Families (5)

* Cited by examiner, † Cited by third party
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US5981987A (en) * 1997-12-02 1999-11-09 Nurlogic Design, Inc. Power ground metallization routing in a semiconductor device
US6838713B1 (en) * 1999-07-12 2005-01-04 Virage Logic Corporation Dual-height cell with variable width power rail architecture
US6467074B1 (en) * 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks
CN1950941A (en) * 2004-04-27 2007-04-18 皇家飞利浦电子股份有限公司 Integrated circuit layout for virtual power supply
CN100514603C (en) * 2005-03-03 2009-07-15 联华电子股份有限公司 Method for realizing circuit layout

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102237356A (en) * 2010-05-06 2011-11-09 台湾积体电路制造股份有限公司 Integrated circuit and its power supply layout and power supply layout method
CN104794253A (en) * 2014-01-17 2015-07-22 京微雅格(北京)科技有限公司 Layout method and device capable of achieving clean supply for chip interior analog modules
CN104794253B (en) * 2014-01-17 2018-01-05 京微雅格(北京)科技有限公司 Realize the layout method and its device of chip internal analog module clean supply

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