CN101494180B - Forming method for a semiconductor device and semiconductor device - Google Patents

Abstract

The invention provides a forming method for a semiconductor device, comprising the following steps: forming a conductive bump on a surface of a substrate; forming a dielectric layer on a peripheral surface of the conductive bump; arranging the substrate on one surface of a substrate to enable the conductive bump with the dielectric layer to be accommodated in a through hole of the substrate; and removing the substrate. The semiconductor device formed includes a substrate, a semiconductor integrated circuit, and a conductive structure. The through hole is arranged in the substrate, the semiconductor integrated circuit is arranged in the substrate, and the conductive structure is arranged in the through hole and electrically connected with the semiconductor integrated circuit. The conductive structure comprises a conductive bump and a dielectric layer. The longitudinal dimension of the conductive bump is larger than that of the through hole. The dielectric layer covers only the peripheral surface of the conductive bump or covers a part of the surface of the substrate.

Description

Forming method for a semiconductor device and semiconductor device

technical field

The invention relates to a forming method for a semiconductor device and the semiconductor device; in particular, a forming method for a semiconductor device and the semiconductor device.

Background technique

With the evolution of functions and applications of electronic products and consumers' requirements for appearance, the packaging of integrated circuits is becoming increasingly dense and small, and even develops from two-dimensional to three-dimensional. Therefore, the industry has developed wafer-level packaging (WaferLevel Package, WLP), three-dimensional packaging, multi-chip packaging (Multi-Chip Package) and system-in-package (System In Package) and other packaging technologies.

According to different application requirements, it can be divided into planar multi-chip module (Multi-Chip Module), multi-chip package (Multi-Chip Package) and three-dimensional stacked package (3D stacked package). Among them, the three-dimensional stacked packaging allows several chips to be combined in a stacked manner, which can more efficiently reduce the packaging area, and can reduce the overall size and weight at the same time, meeting the needs of light, thin and short, so it is gradually adopted by the industry.

Taking the known wafer-level three-dimensional integrated circuit or stacked package as an example, in order to achieve electrical conduction between the top and bottom of the wafer-level chip scale package (Wafer Level Chip Scale Package, WLCSP), the process is quite complicated. The flow chart is as follows As shown in FIG. 1 , the relevant cross-sectional drawings are shown in FIGS. 2A to 2H . During the manufacturing process, two laser drillings are mainly required, plus one electroplating.

In more detail, in step 101, laser drilling is performed on the substrate 201 (a cross-sectional view shown in FIG. 2A ) prior to the crystal grain to form a via hole 203 (via hole). This is the first laser drilling, Its cross-sectional view is shown in Figure 1B. Then, in step 103, a dielectric layer 205 is formed on the surrounding surface of the substrate 201, and the dielectric layer 205 can just fill the through hole 203, and its cross-sectional view is shown in FIG. 2C. Next, as shown in FIG. 2D , step 105 is performed to perform another laser drilling in the through hole 203 filled with the dielectric layer 205, which is the second laser drilling, to remove part of the dielectric filled in the through hole 203. layer 205, making the via hole 203 pass through again. It should be noted that part of the dielectric layer 205 remains on the inner wall after the second drilling for insulation. Finally, as shown in FIG. 2E , step 107 is performed to electroplate in the through hole 203 of the dielectric layer to form a columnar conductive structure 207 in the through hole 203 . In step 109 , solder 209 is electroplated or printed on both ends of the columnar conductive structure 207 to form a structure as shown in FIG. 2F . So far, a single wafer with the conductive structure 207 can be formed.

When the three-dimensional stacking in step 111 is performed, several wafers are stacked, and at this time, the solder 209 at both ends of the conductive structure 207 in each wafer is exactly corresponding, as shown in FIG. 2G . Therefore, step 113 is executed at last to perform fusion welding to electrically connect each product circle, as shown in FIG. 2H .

However, in the process of forming the known semiconductor device, laser drilling needs to be performed twice, and the price and start-up cost of the laser drilling machine are extremely high. On the other hand, it is not easy to fill the dielectric layer into the via hole. In addition, during the second laser drilling, accurate alignment is required to avoid mis-drilling; and when the conductive layer is plated in the through hole, the conductive layer is prone to unevenness and low flatness. Each of the above problems has become a huge cost and process load for the industry.

In view of this, it is an urgent problem to be solved in the industry to provide a method for forming a semiconductor device with a relatively low manufacturing cost and the formed semiconductor device.

Contents of the invention

An object of the present invention is to provide a method for forming a semiconductor device, comprising the following steps: (a) forming a conductive bump (bump) on a surface of a substrate; (b) forming a dielectric layer on a peripheral surface of the conductive bump; (c) disposing the substrate on a surface of a substrate so that the conductive bump having a dielectric layer is accommodated in a through hole of the substrate; and (d) removing the substrate material.

Another object of the present invention is to provide a semiconductor device, which includes a substrate, a semiconductor integrated circuit, and a conductive structure. A through hole is formed through the substrate, and the through hole has a first longitudinal dimension. The semiconductor integrated circuit is arranged in the substrate. The conductive structure is disposed in the through hole to be electrically connected with the semiconductor integrated circuit. The conductive structure includes a conductive bump and a dielectric layer. The conductive bump has a second longitudinal dimension, and the second longitudinal dimension is substantially greater than the first longitudinal dimension. The dielectric layer only covers a peripheral surface of the conductive bump and is in close contact with a side wall of the through hole.

Another object of the present invention is to provide a semiconductor device, which includes a substrate, a semiconductor integrated circuit and a conductive structure. A through hole is formed through the substrate, and the through hole has a first longitudinal dimension. The semiconductor integrated circuit is arranged in the substrate. The conductive structure is disposed in the through hole to be electrically connected with the semiconductor integrated circuit. The conductive structure includes a conductive bump and a dielectric layer. The conductive bump has a second longitudinal dimension, and the second longitudinal dimension is substantially greater than the first longitudinal dimension. The dielectric layer is coated on a peripheral surface of the conductive bump and a surface of the substrate, wherein the dielectric layer coated on the peripheral surface of the conductive bump is in close contact with the sidewall of the through hole.

Since the present invention only needs to perform laser drilling once on the base material, the cost can be greatly reduced, and there will be no alignment problem of the second drilling.

In order to make the above-mentioned purpose, technical features and advantages of the present invention more comprehensible, preferred embodiments are described in detail below with accompanying drawings.

Description of drawings

Fig. 1 is the forming flowchart of known semiconductor device;

2A to 2H are schematic diagrams of forming a known semiconductor device;

3 is a flowchart of forming a semiconductor device according to the first embodiment of the present invention;

4A to 4J are schematic diagrams of forming a semiconductor device according to the first embodiment of the present invention;

5 is a flow chart of forming a semiconductor device according to a second embodiment of the present invention; and

6A to 6J are schematic diagrams of forming a semiconductor device according to a second embodiment of the present invention.

Detailed ways

The first embodiment of the present invention is a method for forming a semiconductor device, the flow chart of which is shown in FIG. 3 , and the relevant cross-sectional views are shown in FIGS. 4A to 4J . This forming method includes the following steps: first, execute step 301 to laser drill holes on a base material 401, thereby forming two through holes 403, as shown in Figure 4A and Figure 4B in cross-sectional view, the upper part of the base material 401 is interposed There is a semiconductor integrated circuit 415 between the through holes 403 . In this embodiment, the substrate 401 is a wafer, but in other embodiments, it can also be a die.

In step 303, two conductive bumps (bump) 405 are formed on a surface of a substrate 407, the cross-sectional view of which is shown in FIG. 4C, wherein the conductive bumps 405 may be called conductive plugs (conductive plugs) herein. , the formation method can be electroplating, gold wire (Gold Wire) or metal pin (Metal Pin); and the material of the substrate 407 can be polyimide (polyimide, PI). In this embodiment, the cross-section of these conductive bumps 405 is circular, while the vertical cross-section is a T-shape. The horizontal part above the T-shape can facilitate the electrical conduction with the semiconductor integrated circuit 415. (shown in the accompanying drawings). And the conductive bump 405 has a second longitudinal dimension.

Then perform step 305, that is, form a dielectric layer 409 on a peripheral surface of each conductive bump 405; in more detail, step 305 further includes sequentially performing 305(a), 305(b) and 305(c) Three steps. Step 305( a ) coating and forming a photoresist layer 411 (the material may be polyimide) on the surface of the substrate 407 and the surrounding surface of the conductive bump 405 , as shown in FIG. 4D . Step 305(b) exposes and develops to cure a part of the photoresist layer 411 on the surrounding surface of the conductive bump 405 to form a dielectric layer 409 as a protective insulation, as shown in FIG. , CVD) or thermal oxidation (Thermal Oxidation). In step 305(c), the photoresist layer 411 around the dielectric layer 409 is etched, thereby removing the photoresist around the conductive bump 405, as shown in FIG. 4F. By performing steps 305(a)-305(c), part of the photoresist layer 411 can be cured into the dielectric layer 409 on the surrounding surface of the conductive bump 405 .

Next, step 307 is performed, setting the base material 407 on the surface of the base material 401 for alignment bonding, so that each conductive bump 405 with a dielectric layer 409 is accommodated in each through hole 403 of the base material 401, wherein each The through hole 403 has a first longitudinal dimension, and the second longitudinal dimension of the conductive bump 405 is larger than the first longitudinal dimension of the through hole 403, that is, after the conductive bump 405 is accommodated in the through hole 403, it will partially protrude, As shown in Figure 4G. After the alignment bonding is completed, step 309 is performed to remove the substrate 407 , and the conductive bumps 405 are transferred to the substrate 401 , as shown in FIG. 4H . Wherein, step 309 achieves the removal of the substrate 407 by etching, tearing or grinding. So far, a single wafer with the conductive bumps 405 formed therein can be obtained.

Subsequently, step 311 is executed, and a conductor 413 is respectively disposed on both ends of the conductive bump 405 , as shown in FIG. 4I . In step 311, the conductor 413 is provided by printing or electroplating, and the conductor 413 can be solder or solder ball. Then step 313 is executed to stack several substrates 401 that have been provided with conductors 413 in step 311 in alignment. Finally, step 315 is executed to melt the conductor 413 to be electrically connected to the semiconductor integrated circuit 415 on another substrate 401 , as shown in FIG. 4J , where the melting is achieved by reflow.

The semiconductor device formed in the first embodiment is shown in FIG. 4I. This semiconductor device includes a base material 401, a semiconductor integrated circuit 415, a conductive structure 417 and two conductors 413, and the semiconductor device is a wafer (wafer), so as to become a wafer-level chip size package, in other implementations Among them, it can also be a die. Referring to FIG. 4B at the same time, a through hole 403 is formed through the substrate 401, and the through hole 403 has a first longitudinal dimension. The semiconductor integrated circuit 415 is disposed in the substrate 401 . The conductive structure 417 is disposed in the through hole 403 to be electrically connected to the semiconductor integrated circuit 415 . The conductive structure 417 includes a conductive bump 405 and a dielectric layer 409 . The conductive bump 405 is a metal bump, and as described in the first embodiment, the conductive bump 405 of the semiconductor device is T-shaped, so as to facilitate the electrical conduction with the semiconductor integrated circuit 415. In other embodiments, The conductive bump 405 can be in other shapes to contact the semiconductor integrated circuit 415 . The conductive bump 405 has a second longitudinal dimension, and the second longitudinal dimension is substantially larger than the first longitudinal dimension. The dielectric layer 409 is an oxide layer. For example, the material of the oxide layer can be silicon dioxide (SiO ₂ ), copper oxide (CuO), copper dioxide (CuO ₂ ), aluminum oxide (Al ₂ O ₃ ), or tin oxide (SnO ₂ ). The dielectric layer 409 covers only a peripheral surface of the conductive bump 405 and is in close contact with a sidewall of the through hole 403 . The two conductors 413 are respectively disposed at two ends of the conductive structure 417 to be electrically connected with the conductive structure 417 . The conductor 413 includes a bonding wire, a solder ball or a metal bump.

In actual application, the semiconductor device is electrically connected to another semiconductor device through the conductive structure 417 and the conductor 413, as shown in FIG. They can be respectively a wafer and a die.

The second embodiment of the present invention is also a forming method for a semiconductor device, the flow chart of which is shown in FIG. 5 , and the relevant cross-sectional views are shown in FIGS. 6A to 6J . This forming method includes the following steps: First, execute step 501 to laser drill holes on a base material 601, thereby forming two through holes 603, as shown in Figure 6A and Figure 6B in cross-sectional view, the upper part of the base material 601 is interposed There is a semiconductor integrated circuit 615 between the through holes 603 . In this embodiment, the substrate 601 is a wafer, but in other embodiments, it can also be a die.

In step 503, two conductive bumps 605 are formed on one surface of a substrate 607, the cross-sectional view of which is shown in FIG. , punching gold wires or planting metal pins; and the material of the substrate 407 can be polyimide. In this embodiment, the cross-section of these conductive bumps 605 is circular, while the vertical cross-section is a T-shape. The horizontal part above the T-shape can facilitate the electrical conduction with the semiconductor integrated circuit 615. (shown in the accompanying drawings). And the conductive bump 605 has a second longitudinal dimension.

Then step 505 is performed, that is, a dielectric layer 609 is formed on a peripheral surface of each conductive bump 605 , as shown in FIG. 6D . However, different from the first embodiment, the dielectric layer 609 of this embodiment is formed on the surface of the substrate 607 and one surface of the conductive bump 605 , and the method used in this step is spin coating.

Next, step 507 is performed, and the base material 607 is disposed on the surface of the substrate 601 for alignment bonding, so that each conductive bump 605 having a dielectric layer 609 is accommodated in each through hole 603 of the substrate 601, wherein each The through hole 603 has a first longitudinal dimension, and the second longitudinal dimension of the conductive bump 605 is larger than the first longitudinal dimension of the through hole 603, that is, after the conductive bump 605 is accommodated in the through hole 603, it will partially protrude, As shown in Figure 6E.

Step 509 removes the dielectric layer 609 on the bottom surface of the conductive bump 605, that is, removes the dielectric layer 609 on the lower surface of the conductive bump 605 (that is, the bottom surface of the longitudinal part below the T shape), as shown in FIG. 6F As shown, the removal method in this embodiment is grinding, and other removal methods can also be used in other implementations.

Step 511 is performed to remove the substrate 607, and the conductive bumps 605 are then transferred to the substrate 601, as shown in FIG. 6G. Wherein, step 511 achieves the removal of the substrate 607 by etching, tearing or grinding. So far, a single wafer with the conductive bumps 605 formed therein can be obtained.

Subsequently, step 513 is executed, and a conductor 613 is respectively disposed on both ends of the conductive bump 605 , as shown in FIG. 6H . In step 515, the conductor 613 is provided by printing or electroplating, and the conductor 613 can be solder or solder ball. Then step 517 is executed, and several substrates 601 with conductors 613 disposed in step 515 are aligned and stacked, as shown in FIG. 6I . Finally, step 519 is performed to melt the conductor 613 to be electrically connected to the semiconductor integrated circuit 615 on another substrate 601. The melting here is achieved by reflow, and the dielectric layer 609 is also cured at the same time. As shown in Figure 6J.

The semiconductor device formed in the second embodiment is shown in FIG. 6H. This semiconductor device includes a substrate 601, a semiconductor integrated circuit 615, a conductive structure 617 and two conductors 613, and the semiconductor device is a wafer to form a wafer-level chip size package. In other implementations, also Can be a grain. Referring to FIG. 6B at the same time, a through hole 603 is formed through the substrate 601, and the through hole 603 has a first longitudinal dimension. The semiconductor integrated circuit 615 is disposed in the substrate 601 . The conductive structure 617 is disposed in the through hole 603 to be electrically connected to the semiconductor integrated circuit 615 . The conductive structure 617 includes a conductive bump 605 and a dielectric layer 609 . The conductive bump 605 is a metal bump, and as described in the first embodiment, the conductive bump 605 of the semiconductor device is T-shaped, so as to facilitate the electrical conduction with the semiconductor integrated circuit 615. In other embodiments, The conductive bump 605 can have other shapes to contact the semiconductor integrated circuit 615 . The conductive bump 605 has a second longitudinal dimension, and the second longitudinal dimension is substantially larger than the first longitudinal dimension. The dielectric layer 609 is an oxide layer. For example, the material of the oxide layer can be silicon dioxide (SiO ₂ ), copper oxide (CuO), copper dioxide (CuO ₂ ), aluminum oxide (Al ₂ O ₃ ), or tin oxide (SnO ₂ ). The dielectric layer 609 is coated on a peripheral surface of the conductive bump 605 and a surface of the substrate 601 , wherein the dielectric layer 609 coated on the peripheral surface of the conductive bump 605 is in close contact with a sidewall of the through hole 603 . The two conductors 613 are respectively disposed at two ends of the conductive structure 617 to be electrically connected to the conductive structure 617 . The conductor 613 includes a bonding wire, a solder ball or a metal bump.

In actual application, the semiconductor device is electrically connected to another semiconductor device through the conductive structure 617 and the conductor 613, as shown in FIG. They can be respectively a wafer and a die.

In the above two embodiments, although only 2 through holes are drilled in each substrate, and only 2 corresponding conductive bumps are formed, those skilled in the art should be able to easily deduce other implementation quantities.

With the structure of the present invention, only one laser drilling is required in the production process, the production cost is low, there is no problem of filling holes in the dielectric layer, and there is no problem of alignment of the second laser drilling, and there is no need for electroplating in the through holes The conductive layer simplifies the manufacturing process. There is also no problem with the flatness of the conductive layer in the via hole

The above-mentioned embodiments are only used to illustrate the implementation of the present invention and explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalence arrangements that can be easily accomplished by those skilled in the art belong to the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.

Claims (10)

1. manufacturing process that is used for the semiconductor device is characterized in that comprising the following step:

(a) form a conductive projection on a surface of a ground;

(b) form a dielectric layer in a circumferential surface of this conductive projection;

(c) this ground is set on a surface of a base material, this conductive projection with this dielectric layer is fitted be placed in the through hole of this base material; And

(d) by etching, remove or worn to remove this ground.

2. the method for claim 1 is characterized in that, step (b) more comprises:

(e) form a photoresist layer reaches this conductive projection on this surface of this ground this circumferential surface;

(f) solidify a part of photoresist layer of this circumferential surface of this conductive projection, to form this dielectric layer; And

(g) this photoresist layer around this dielectric layer of etching.

3. the method for claim 1 is characterized in that, step (b) more comprises:

(h) form a dielectric layer on this surface of this ground and on the surface of this conductive projection; And

(i) remove this dielectric layer of the bottom surface in this surface of this conductive projection.

4. the method for claim 1 is characterized in that, more comprises the following step behind completing steps (d):

(j) by printing or plating the two ends of one electric conductor in this conductive projection are set respectively;

(k) melt this electric conductor to electrically connect with another semiconductor integrated circuit.

5. semiconductor device comprises:

One base material provides a through hole, and this through hole has one first longitudinal size;

The semiconductor integrated circuit is arranged in this base material; And

One conductive structure is arranged in this through hole, and to electrically connect with this semiconductor integrated circuit, this conductive structure comprises:

One conductive projection, a T font that is formed as one, have a lateral part, a top and a below longitudinal component, this conductive projection has one second longitudinal size, and this second longitudinal size is basically greater than this first longitudinal size, and wherein this conductive projection sees through this lateral part, top and the electric connection of this semiconductor integrated circuit; And

One dielectric layer only is coated on a circumferential surface of this conductive projection, and connects airtight with a sidewall of this through hole.

6. semiconductor device as claimed in claim 5 is characterized in that, dielectric layer more is coated on the surface of this base material, only is coated on this dielectric layer of this circumferential surface of this conductive projection and this sidewall of this through hole and connects airtight.

7. semiconductor device as claimed in claim 5 is characterized in that, this conductive projection is a metal coupling.

8. semiconductor device as claimed in claim 5 is characterized in that, more comprises two electric conductors, is arranged at two ends of this conductive structure respectively, and to electrically connect with this conductive structure, this electric conductor comprises a bonding wire, a tin ball or a metal coupling.

9. semiconductor device as claimed in claim 8, it is characterized in that, by this conductive structure and this electric conductor to electrically connect with second half conductor means, wherein this second half conductor means and this semiconductor device have a same configuration basically, and this second half conductor means and this semiconductor device are changed to a wafer or a crystal grain.

10. semiconductor device as claimed in claim 5 is characterized in that, this dielectric layer is an oxide layer.

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