CN101494019B - Driving device for a gate driver of a flat panel display - Google Patents
Driving device for a gate driver of a flat panel display Download PDFInfo
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- CN101494019B CN101494019B CN200810004569XA CN200810004569A CN101494019B CN 101494019 B CN101494019 B CN 101494019B CN 200810004569X A CN200810004569X A CN 200810004569XA CN 200810004569 A CN200810004569 A CN 200810004569A CN 101494019 B CN101494019 B CN 101494019B
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- 239000000872 buffer Substances 0.000 claims description 5
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- 101150018164 dio1 gene Proteins 0.000 description 8
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- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 5
- 101150080656 DIO2 gene Proteins 0.000 description 3
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Abstract
A driving device for a gate driver of a flat panel display for reducing the production cost of the gate driver includes a plurality of addressing units and an output control circuit. Each addressing unit of the plurality of addressing units is used for generating a plurality of addressing signals. The output control circuit is used for carrying out logical operation on a plurality of addressing signals generated by each addressing unit of the plurality of addressing units and a plurality of addressing signals generated by other addressing units in sequence to generate a plurality of channel output signals so as to drive the flat panel display to display image data.
Description
Technical field
The present invention relates to a kind of drive unit that is used for a gate drivers of a flat-panel screens, particularly a kind of drive unit that reduces the production cost of this gate drivers.
Background technology
LCD has that external form is frivolous, power consumption is few and characteristic such as radiationless pollution, has been widely used on the information products such as computer system, mobile phone, PDA(Personal Digital Assistant).The principle of work of LCD is to utilize liquid crystal molecule under different ordered states, light had different polarizations or refraction effect, therefore can control the amount of penetrating of light via the liquid crystal molecule of different ordered states, further produce the output light of varying strength, and the red, green, blue of different GTG intensity.
Please refer to Fig. 1, Fig. 1 is existing a thin film transistor (TFT) (Thin Film Transistor, TFT) synoptic diagram of LCD 10.Thin Film Transistor-LCD 10 comprises a panel (LCD Panel) 100, one sequential generator 102, a data line signal output circuit 104 and one scan line signal output apparatus 106.Data line signal output circuit 104 includes a plurality of source electrode drivers (Source Driver) 140 that are serially connected with a sequence, and scanning-line signal output circuit 106 also includes a plurality of gate drivers (Gate Driver) 160 that are serially connected with a sequence.For the sake of clarity, only draw three gate drivers 160 among Fig. 1.The control signal that data line signal output circuit 104 is produced according to clock generator 102, one data-signal is converted to a voltage signal, and a clock signal clk and an initial signal Dio1 that scanning-line signal output circuit 106 is produced according to clock generator 102, the output of control voltage signal, and then control the potential difference (PD) of the equivalent capacity of each pixel, make panel 100 present different gray scale variation.Data-signal is to follow single direction input data line signal output apparatus 104 in regular turn, as p among Fig. 1
n(x, y), p
n(x+1, y), p
n(x+2, y) ... p
n(x, y+1), p
n(x+1, y+1), p
n(x+2, y+1) ... p
N+1(x, y), p
N+1(x+1, y), p
N+1(x+2, y) ... p
N+1(x, y+1), p
N+1(x+1, y+1), p
N+1(x+2, y+1) ... order shown in.In addition, the quantity of Thin Film Transistor-LCD 10 employed source electrode drivers 140 or gate driver 160 is that the resolution according to single source electrode driver 140 or single gate drivers 160 controllable numbers of channels and Thin Film Transistor-LCD 10 determines.
Please refer to Fig. 2 and Fig. 3, Fig. 2 is the functional block diagram of gate drivers 160, and Fig. 3 is the working timing figure of gate drivers 160 shown in Figure 2.At this hypothesis gate drivers 160 is one to include the gate drivers of K delivery channel, therefore, gate drivers 160 includes K shift register (Shift Register) 200, a K electric potential transducer (Level Shifter) 202 and K impact damper (Output Buffer) 204.K electric potential transducer 202 is respectively coupled to K shift register 200, and K impact damper 204 also is respectively coupled to K electric potential transducer 202.Start signal Dio1 (or initial signal Dio2 of different directions) and clock signal clk input to a shift register 200 of K shift register 200.When the positive edge of a clock triggered (Clock Rising Trigger), shift register 200 can transmit an address signal to next shift register 200, and exported address signal to corresponding electric potential transducer 202.Next, address signal becomes channel output (Channel Output) signal by impact damper 204 after changing via electric potential transducer 202 again.Therefore, K address signal, Q
1To Q
K, can be passed to K electric potential transducer 202 respectively, and become K channel output signal, X by K impact damper 204
1To X
K
Above-mentioned gate drivers 160 is to use existing One-hot addressing mode, that is to say, each needs a shift register 200 and an electric potential transducer 202 each output channel.Circuit that it should be noted that electric potential transducer has accounted for gate drivers area cost over half.Along with the progress of semiconductor technology, the controllable output channel quantity of each gate drivers will get more and more, and assembly volume also is tending towards miniaturization, design gate drivers with existing One-hot addressing mode, can't reduce production costs effectively.
Summary of the invention
Therefore, fundamental purpose of the present invention promptly is to provide a kind of drive unit that is used for a gate drivers of a flat-panel screens, is used for reducing the production cost of this gate drivers.
The present invention discloses a kind of drive unit that is used for a gate drivers of a flat-panel screens, is used for reducing the production cost of this gate drivers, includes a plurality of selected cells, and each selected cell is used for producing a plurality of address signals; And an output control circuit, be used in regular turn will these a plurality of selected cells a plurality of address signals that a plurality of address signal and other selected cell produced that each selected cell produced carry out logical operation, to produce a plurality of channel output signal.
The present invention discloses a kind of drive unit that is used for a flat-panel screens in addition, is used for reducing the production cost of this flat-panel screens, includes a panel; One sequential generator; The multiple source driver is coupled between this clock generator and this panel, is used for output image data to this panel; And a plurality of gate drivers, be coupled between this clock generator and this panel, be used for driving this panel display image data, each gate drivers of these a plurality of gate drives includes: a plurality of selected cells, and each selected cell is used for producing a plurality of address signals; And an output control circuit, be used in regular turn will these a plurality of selected cells a plurality of address signals that a plurality of address signal and other selected cell produced that each selected cell produced carry out logical operation, to produce a plurality of channel output signal.
Description of drawings
Fig. 1 is the synoptic diagram of an existing Thin Film Transistor-LCD.
Fig. 2 is the functional block diagram of an existing gate drivers.
Fig. 3 is the working timing figure of gate drivers shown in Figure 2.
Fig. 4 is the functional block diagram of the embodiment of the invention one gate drivers.
Fig. 5 is the functional block diagram of one first selected cell of gate drivers shown in Figure 4.
Fig. 6 is the functional block diagram of one second selected cell of gate drivers shown in Figure 4.
Fig. 7 is the functional block diagram of an output control unit of gate drivers shown in Figure 4.
Fig. 8 is the working timing figure of gate drivers shown in Figure 4.
Fig. 9 is the functional block diagram of the embodiment of the invention one gate drivers.
Figure 10 is the functional block diagram of one first selected cell of gate drivers shown in Figure 9.
Figure 11 is the working timing figure that gate drivers shown in Figure 9 is used dipulse.
Figure 12 is the working timing figure that gate drivers shown in Figure 9 is used long pulse.
Figure 13 is the functional block diagram of the embodiment of the invention one flat-panel screens.
The reference numeral explanation
10 Thin Film Transistor-LCDs
130 flat-panel screens
100,1300 panels
102,1302 clock generators
104 data line signal output circuits
106 scanning-line signal output circuits
140,1304 source electrode drivers
160,40,90,1306 gate drivers
200,410 shift registers
202,412 electric potential transducers
204,416 impact dampers
400,900 first selected cells
402,902 second selected cells
404,904 output control circuits
406,906 output control units
414 logical blocks
Dio1, Dio2 start signal
CLK, CLK1 clock signal.
Embodiment
Because use in the gate drivers of existing One-hot addressing mode, each needs a shift register and an electric potential transducer each output channel, could produce a channel output signal, therefore can't reduce production costs effectively.The present invention will thus, can significantly save the assembly area of gate drivers with the delivery channel of two-stage addressing (Two-stage Addressing) design gate drivers, and then save production cost.
Please refer to Fig. 4, Fig. 4 is the functional block diagram of the embodiment of the invention one gate drivers 40.In Fig. 4, suppose that gate drivers 40 is one to include the gate drivers of K delivery channel.Gate drivers 40 includes one first selected cell 400, one second selected cell 402 and an output control circuit 404.First selected cell 400 and second selected cell 402 all are coupled to output control circuit 404, are respectively applied for the addressing of phase one and the addressing of subordinate phase, are used for producing K address signal corresponding to K delivery channel.First selected cell 400 produces M address signal, and each address signal is with M
1, M
2..., M
m..., M
MExpression, 1≤m≤M.Second selected cell 402 produces N address signal, and each address signal is with N
0, N
1..., N
n..., N
N-1Expression, 0≤n≤N-1.In addition, output control circuit 404 can be divided into N output control unit 406 again.N output control unit 406 is used for address signal M that first selected cell 400 is produced
1, M
2..., M
m..., M
MThe address signal N that is produced with second selected cell 402 respectively
0, N
1..., N
n..., N
N-1Carry out logical operation, thereby produce K channel output (Channel Output) signal X
1, X
2..., X
M, X
M+1..., X
K
In brief, gate drivers 40 is to be one group with M output channel, altogether K output channel is divided into the N group, K≤M * N.The addressing of phase one is to produce address signal M by first selected cell 400
1To M
N, the addressing of subordinate phase then is to produce address signal N by second selected cell 402
0To N
N-1In Fig. 4, an initial signal Dio1 and clock signal clk, CLK1 are that the time schedule controller by gate drivers 40 is produced.Dio1 is the start signal of first selected cell 400 and second selected cell 402.
CLK is the clock signal of first selected cell 400, and CLK1 is the clock signal of second selected cell 402 and is the fractional frequency signal of counting (Counting) number of first selected cell 400.When the positive edge of clock triggers (Clock Rising Trigger), the address signal M that output control unit 406 is produced first selected cell 400
1, M
2..., M
m..., M
MThe address signal N that is produced with second selected cell 402 in regular turn
0Carry out logical operation, and produce channel output signal X
1, X
2..., X
MWhen the positive edge of next clock triggered, first selected cell 400 was replied by address signal M
1Begin output, the address signal of second selected cell 402 output then carry to N
1, at this moment, the address signal M that next output control unit 406 will be produced first selected cell 400
1, M
2..., M
m..., M
MThe address signal N that is produced with second selected cell 402
1Carry out logical operation, and produce channel output signal X
M+1, X
M+2..., X
2MThus, by first selected cell 400 and second selected cell 402, gate drivers 40 can produce channel output signal X
1, X
2..., X
M, X
M+1..., X
K
About the detailed functions of first selected cell 400, second selected cell 402 and output control unit 406, please respectively with reference to figure 5, Fig. 6 and Fig. 7.Fig. 5 is the functional block diagram of first selected cell 400, and Fig. 6 is the functional block diagram of second selected cell 402, and Fig. 7 is the functional block diagram of output control unit 406.As shown in Figure 5, first selected cell 400 includes M shift register 410 and M electric potential transducer 412.When the positive edge of clock triggered, shift register 410 can transmit an address signal to next shift register 410, and exported address signal to an electric potential transducer 412.M electric potential transducer 412 is used for changing the current potential of the address signal that M shift register 410 exported, to produce address signal M
1To M
MAs shown in Figure 6, be similar to first selected cell, 400, the second selected cells 402 and include N shift register 410 and N electric potential transducer 412, to produce address signal N
0To N
N-1
As shown in Figure 7, each output control unit 406 of output control circuit 404 includes M logical block 414 and M impact damper 416.M the address signal M that logical block 414 is produced first selected cell 400
1, M
2..., M
m..., M
MAn address signal N who is produced with second selected cell 402 respectively
nCarry out logical operation, and produce channel output signal X by M impact damper 416
n, h=(n * M)+m, 1≤m≤M, 0≤n≤N-1.In addition, please refer to Fig. 8, Fig. 8 is the working timing figure of gate drivers 40.Start signal Dio2 represents the start signal of different directions.As mentioned above, the embodiment of the invention is to be one group with M output channel, altogether K output channel is divided into the N group, K≤M * N.For instance, if gate drivers 40 includes 400 delivery channels, first selected cell 400 can comprise 20 shift registers 410 and 20 electric potential transducers 412, to produce address signal M
1, M
2..., M
20And second selected cell 402 can comprise 20 shift registers 410 and 20 electric potential transducers 412, to produce address signal N
0, N
1..., N
19The M that first selected cell 400 is produced
1, M
2..., M
20Can pass through output control unit 406, respectively the address signal N that is produced with unit, second location 402
0, N
1..., N
19Carry out logical operation, obtain channel output signal X
1, X
2..., X
400That is to say that 40 shift registers 410 of 40 needs of gate drivers and 40 electric potential transducers 412 can produce 400 channel output signal.If with existing One-hot addressing mode design gate drivers 40, need 400 shift registers 410 and 400 electric potential transducers 412, in comparison, the present invention can significantly save the area cost of gate drivers 40.
Furtherly, utilize the gate drivers 40 of two-stage addressing to be one embodiment of the invention, this area tool knows that usually the knowledgeable is when doing suitable variation and modification according to this.For instance, the two-stage addressing is also extensible to be the multistage addressing, stage number 〉=2.Accordingly, gate drivers 40 comprises a plurality of selected cells, and wherein, the clock signal of each stage selected cell is the fractional frequency signal of the count number of addressing previous stage.For instance, if the channel output signal of gate drivers 40 is to produce by the addressing of three stages, then gate drivers 40 includes one first selected cell, one second selected cell and one the 3rd selected cell.One address signal of first selected cell and an address signal of second selected cell carry out logical operation, obtain a subordinate phase address signal, the subordinate phase address signal carries out logical operation with an address signal of the 3rd selected cell again, obtain a phase III address signal, be a channel output signal, wherein, the clock signal of the 3rd selected cell is the fractional frequency signal of the count number of subordinate phase address signal.It should be noted that, in the gate drivers 40 of two-stage addressing, each logical block 414 of M logical block 414 is used for two different address signals are carried out logical operation simultaneously, and in the gate drivers 40 of multistage addressing, logical block 414 also can design so that a plurality of address signals are carried out logical operation simultaneously, but not can only carry out the logical operation of two different address signals simultaneously.For instance, if the channel output signal of gate drivers 40 is to produce by the addressing of eight stages, logical block 414 also can be carried out logical operation to eight address signals simultaneously.
In addition, the present invention also can be applicable to use the gate drivers of dipulse (Double-Pulse) or long pulse (Long-Pulse).Dipulse is meant and occurs twice start signal continuously in fixing clock spacing.Long pulse is meant the pulse length of start signal greater than a clock period, and gate drivers has continuous plural passage output at one time.If gate drivers 40 uses dipulse or long pulses, the address signal M that is produced when first selected cell 400
1, M
2..., M
m..., M
MThe samsara counting finishes and replys by address signal M
1When beginning to export, the address signal of second selected cell, 402 outputs will be exported N simultaneously
nAnd N
N+1And make the mistake, therefore, the present invention provides a gate drivers 90 in addition, as shown in Figure 9.Gate drivers 90 is gate drivers of the multistage addressing of a use dipulse or long pulse.
In Fig. 9, gate drivers 90 is to be example with the two-stage addressing, and also extensible is the multistage addressing, stage number 〉=2.Be similar to gate drivers 40, gate drivers 90 comprises one first selected cell 900, one second selected cell 902 and an output control circuit 904.Output control circuit 904 can be divided into a plurality of output control units 906 again.Second selected cell 902 is same as second selected cell 402 of gate drivers 40, and each output control unit 906 is same as the output control unit 406 of gate drivers 40, does not give unnecessary details at this.First selected cell 900 that it should be noted that gate drivers 90 is different with first selected cell 400 of gate drivers 40.
Please refer to Figure 10, Figure 10 is the functional block diagram of first selected cell 900.First selected cell 400 of gate drivers 40 includes M shift register 410 and M electric potential transducer 412, and first selected cell 900 of gate drivers 90 then includes 2M shift register 410 and 2M electric potential transducer 412.As shown in figure 10, the addressing of the phase one of gate drivers 90 is divided into two groups, respectively with (M-1) and (M-2) expression.Preceding M shift register 410 and preceding M electric potential transducer 412 are (M-1) group, produce address signal M
1To M
MM electric potential transducer 412 of a back M shift register 410 and back is (M-2) group, produces address signal M
M+1To M
2MThus, can avoid because the problem of dipulse or the subordinate phase addressing error that long pulse caused.As Fig. 9 and shown in Figure 10, an initial signal Dio1 and clock signal clk, CLK1 are that the time schedule controller by gate drivers 90 is produced.Dio1 is the start signal of first selected cell 900 and second selected cell 902.CLK is the clock signal of first selected cell 900, and CLK1 is the clock signal of second selected cell 902 and is the fractional frequency signal of the count number of first selected cell 900.In addition, please refer to Figure 11 and Figure 12.Figure 11 is the working timing figure that gate drivers 90 is used dipulse, and Figure 12 is the working timing figure that gate drivers 90 is used long pulse.In Figure 11, L represents that the clock spacing (L 〉=2) of fixing, dipulse are illustrated in and occurs twice start signal in the spacing L continuously.In Figure 12, T
CycleThe width of a clock period of expression, T represents the width of start signal Dio1, long pulse is represented T 〉=2T
Cycle
Please refer to Figure 13, Figure 13 is the functional block diagram of the embodiment of the invention one flat-panel screens 130.The principle of work of flat-panel screens 130 is similar to the existing Thin Film Transistor-LCD 10 of Fig. 1, does not give unnecessary details at this.Flat-panel screens 130 comprises a panel 1300, a sequential generator 1302, multiple source driver 1304 and a plurality of gate drivers 1306.Multiple source driver 1304 is coupled between clock generator 1302 and the panel 1300, is used for output image data to panel 1300.A plurality of gate drivers 1306 are coupled between clock generator 1302 and the panel 1300, are used for driving panel 1300 display image datas.For the sake of clarity, only draw three gate drivers 1306 among Figure 13.In Figure 13, each gate drivers 1306 is to use the gate drivers of two-stage addressing, and its framework and principle of work thereof are same as gate drivers 40, do not give unnecessary details at this.It should be noted that gate drivers 1306 also can be the gate drivers of multistage addressing.On the other hand, the framework of gate drivers 1306 and principle of work thereof also can be same as gate drivers 90, and thus, flat-panel screens 130 can be used dipulse or long pulse.In addition, flat-panel screens 130 is not limited to LCD, also can be electricity slurry flat-panel screens (PDP), organic light emitting diode display (OLED) or integrate gate driver circuit (Gatedriver-on-array, various flat-panel screens such as flat-panel screens GOA) on glass substrate.
In sum, the present invention is divided into a plurality of selected cells with a plurality of shift registers and a plurality of electric potential transducer of gate drivers, and to carry out the addressing in a plurality of stages, the product of the counting of each stage addressing is the quantity of the channel output signal of gate drivers.Thus, the present invention can significantly save the assembly area of gate drivers, and then saves production cost.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810004569XA CN101494019B (en) | 2008-01-25 | 2008-01-25 | Driving device for a gate driver of a flat panel display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810004569XA CN101494019B (en) | 2008-01-25 | 2008-01-25 | Driving device for a gate driver of a flat panel display |
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| Publication Number | Publication Date |
|---|---|
| CN101494019A CN101494019A (en) | 2009-07-29 |
| CN101494019B true CN101494019B (en) | 2011-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810004569XA Expired - Fee Related CN101494019B (en) | 2008-01-25 | 2008-01-25 | Driving device for a gate driver of a flat panel display |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102103294B (en) * | 2009-12-17 | 2012-11-28 | 联咏科技股份有限公司 | Gate drive circuit and relevant liquid crystal display |
| CN102237055A (en) * | 2010-05-05 | 2011-11-09 | 联咏科技股份有限公司 | Gate driver for liquid crystal display (LCD) and driving method |
| JP5780649B2 (en) * | 2011-11-11 | 2015-09-16 | 株式会社Ｊｏｌｅｄ | Buffer circuit, scanning circuit, display device, and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5850216A (en) * | 1996-06-07 | 1998-12-15 | Lg Semicon Co., Ltd. | Driver circuit for thin film transistor-liquid crystal display |
| CN1534583A (en) * | 2003-03-31 | 2004-10-06 | 京东方显示器科技公司 | LCD driver |
-
2008
- 2008-01-25 CN CN200810004569XA patent/CN101494019B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5850216A (en) * | 1996-06-07 | 1998-12-15 | Lg Semicon Co., Ltd. | Driver circuit for thin film transistor-liquid crystal display |
| CN1534583A (en) * | 2003-03-31 | 2004-10-06 | 京东方显示器科技公司 | LCD driver |
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| Publication number | Publication date |
|---|---|
| CN101494019A (en) | 2009-07-29 |
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