CN101488699B - Digital Latch Control Circuit and Its Power Converter for Overvoltage Protection - Google Patents

Abstract

The invention provides a power converter with overvoltage protection. The power converter comprises a voltage conversion circuit and a digital latch control circuit. The voltage conversion circuit has a transformer having a primary winding, a secondary winding, and an auxiliary winding, wherein the auxiliary winding is configured to provide a supply voltage, and the digital latch control circuit is coupled to the voltage conversion circuit and configured to latch a voltage level of the supply voltage at a first predetermined level according to an over-voltage protection trigger signal, wherein the voltage conversion circuit is in a disabled state when the voltage level is latched at the first predetermined level.

Description

Digital Latch Control Circuit and Its Power Converter for Overvoltage Protection

technical field

The invention relates to a latch control circuit, in particular to a digital latch control circuit applied to overvoltage protection.

Background technique

Generally, power converters use an over-voltage protection mechanism to prevent internal high-voltage signals from exceeding a specific voltage level. Referring to FIG. 1 , it is a schematic diagram of a conventional power converter 100 . The power converter 100 is a flyback converter (flyback converter), as shown in the figure, it includes a bridge rectifier (bridge rectifier) 105, has a primary-side winding (primary-side winding) L _P and a secondary-side winding (secondary- side winding) L _S and transformer TX1 of auxiliary winding (auxiliary winding) La _aux , diode D ₁ , capacitors C ₁ and C ₂ , resistors R ₁ , R ₂ , R _p and R _n , transistors Q ₁ and Q ₂ and anti- A de-glitch circuit 110 . Those skilled in the art should understand the circuit design of the flyback converter, and the detailed circuit design of the power converter 100 is not listed here for simplicity of description. When the above-mentioned overvoltage protection mechanism is applied to the power converter 100, it will detect whether the level of the supply voltage V _CC on the capacitor _C2 shown in the figure is too high, so as to prevent the internal circuits of the power converter 100 from being unable to operate; generally Under the condition, when it is detected that the supply voltage V _CC is too high (that is, an abnormal situation occurs), the primary side winding L _P of the transformer TX will not transfer the energy of the AC input voltage V _AC to the secondary side winding L _S , similarly , the auxiliary winding L _aux also no longer receives energy from the AC input voltage V _AC , so the supply voltage V _CC itself will drop until the supply voltage V _CC drops to a voltage level at which the internal circuits of the power converter 100 can work normally, once The side winding L _P will perform energy transfer again, however, if the abnormal situation is still not eliminated, the level value of the supply voltage V _CC will increase and appear too high again, in other words, if the abnormal situation of the power converter 100 If it still exists, the level value of the supply voltage V _CC will fluctuate from high to low.

The power converter 100 uses resistors R _p and R _n and transistors Q ₁ and Q ₂ to solve the above problems, wherein the resistors R _p and R _n , transistors Q ₁ and Q ₂ are externally coupled circuit components. When it is detected that the supply voltage V _CC is too high, the over-voltage protection trigger signal OVP _trigger will be triggered to the base of the transistor Q ₂ (that is, the node N ₁ ), and the voltage level of the node N ₁ will be increased to turn on the transistor Q ₂ . Transistor Q ₂ is turned on, and then the voltage level of node N ₂ is pulled down to make transistor Q ₁ also turned on. At this time, although there is no over-voltage protection trigger signal OVP _trigger , the voltage level of node N ₁ It will increase due to the fact that the transistor _Q1 is turned on, so that the transistors _Q1 and _Q2 will be fully turned on in the end, and the supply voltage V _CC will be pulled down and remain low The level value is the divided voltage obtained by the AC input voltage V _AC passing through the diode of the bridge rectifier 105, the resistance R ₁ and the parallel connection of the resistance R _p and R _n in series, so no supply voltage will occur The level value of V _CC appears high and low repeatedly.

However, the circuitry of power converter 100 suffers from certain disadvantages. Since the circuit composed of transistors Q ₁ and Q ₂ and resistors R _p and R _n is an analog circuit, and under normal circumstances transistors Q ₁ and Q ₂ are not turned on, and nodes N ₁ and N ₂ are high impedance points ( high impedance point), the impedance values seen by the nodes _N1 and _N2 are quite high at this time, if they are disturbed by spike pulses, it is easy to make the transistors _Q1 and _Q2 enter the conduction state and cause the power converter 100 In order to solve this problem, an additional anti-spike circuit 110 (as shown in the power converter 100 of FIG. ₁ ) must be added on the node N1. However, this also means that the circuit cost will increase, and due to The anti-glitch circuit 110 must function when the power converter 100 is turned on, so an extra current needs to be provided to the anti-glitch circuit 110 when the power converter 100 is turned on.

Contents of the invention

One of the objectives of the present invention is to provide a digital latch control circuit for overvoltage protection and a power converter including the control circuit, so as to solve the above-mentioned problems.

According to an embodiment of the present invention, a power converter with overvoltage protection is disclosed. The power converter includes a voltage conversion circuit and a digital latch control circuit, the voltage conversion circuit has a transformer, the transformer has a primary winding, a secondary winding and an auxiliary winding, wherein the auxiliary winding is used to provide a supply voltage, and the The digital latch control circuit is coupled to the voltage conversion circuit, and is used for latching the voltage level of the supply voltage at a first predetermined level when receiving an overvoltage protection trigger signal, wherein when the voltage level is latched at the first At a predetermined level, the voltage conversion circuit is in a disabled state.

Description of drawings

FIG. 1 is a schematic diagram of a known power converter;

2 is a schematic diagram of an AC-to-DC power converter according to an embodiment of the present invention;

3 is a schematic diagram of the digital latch control circuit shown in FIG. 2 under normal operation and under latch operation;

FIG. 4 is a related timing diagram of the digital latch control circuit shown in FIG. 2 under normal operation and latch operation;

FIG. 5 is a schematic diagram of the waveform of the supply voltage V _CC shown in FIG. 2;

FIG. 6 is a schematic diagram of a power converter according to another embodiment of the present invention.

Explanation of main component symbols

100, 200, 600 power converter

105 bridge rectifier

110 Anti-spike interference circuit

205 Voltage conversion circuit

206 bridge rectifier

210 Digital latch control circuit

2105 Voltage regulator

2115 NOR gate

2120 D-type flip-flop

2125 Inverter

Detailed ways

Referring to FIG. 2 , FIG. 2 is a schematic diagram of an AC-to-DC power converter 200 according to an embodiment of the present invention. As shown in FIG. 2 , the power converter 200 is a flyback voltage converter, which includes a voltage conversion circuit 205 and a digital latch control circuit 210, wherein the voltage conversion circuit 205 has a bridge rectifier 206, an input filter capacitor C ₁ , and a transformer TX2 , resistor R ₁ , resistor R ₂ , diode D ₁ and capacitor C ₂ . The bridge rectifier 206 is used to rectify the AC input voltage V _AC into a pulsating DC voltage. The pulsating DC voltage is filtered by the input filter capacitor _C1 to generate a DC input voltage. The transformer TX2 has a primary winding L _P , a secondary winding L _S and an auxiliary winding _Laux . To simplify the description, the operations of the primary winding _LP and the secondary winding _LS are not described in detail here; the auxiliary winding _Laux , the resistor R ₂ , the diode D ₁ and the capacitor C ₂ provide the supply voltage V _CC .

The purpose of the digital latch control circuit 210 is to latch the voltage level of the supply voltage V _CC at a first predetermined level V ₁ when receiving the overvoltage protection trigger signal OVP _trigger , when the supply voltage V When the voltage level of _CC is latched at the first predetermined level _V1 , the voltage conversion circuit 205 will be in a disabled state (disabled) and cannot operate. At this time, the abnormality of the power supply can be eliminated after replugging.

The power converter 200 also includes a voltage regulator 2105. The voltage regulator 2105 converts the supply voltage V _CC into a converted voltage V CC _' lower than the voltage level of the supply voltage V _CC itself, and then the digital latch control circuit 210 The voltage level of the converted voltage V _{CC ′} is locked at the second predetermined level V2 to achieve the purpose of locking the voltage level of the supply voltage V _CC at the first predetermined level _V1 . The digital latch control circuit 210 is implemented with digital circuits and the required circuit components can be low-voltage components, so the circuit cost can be reduced. In detail, the digital latch control circuit 210 includes a switch unit SW composed of transistors _Q1 and _Q2 , a resistance unit R3 and a control module, wherein the control module consists of a NOR gate 2115, a D-type flip-flop (D-type flip-flop, DFF) 2120 and inverter 2125, the switch unit SW selectively turns on one of the transistors _Q1 and _Q2 according to the control signal _Sc , and the control module will be triggered according to the overvoltage protection The signal OVP _trigger , the converted voltage V _CC ' corresponding to the supply voltage V _CC , and the voltage level V' on the emitters of the transistors Q ₁ and Q ₂ are used to generate the control signal _Sc to control the switch unit SW. When the control signal When S _c controls the state of the transistor Q ₁ to be on and the state of the transistor Q ₂ to be non-conductive, the voltage level of the supply voltage V _CC will be locked at the first predetermined level V ₁ due to the relationship of voltage division.

Of course, in order to prevent the digital latch control circuit 210 from malfunctioning due to spikes affecting the value of the voltage level V', the digital latch control circuit 210 may include an anti-spike interference circuit, and this embodiment minimizes the added circuit cost, the anti-spike circuit is implemented with transistor Q3. Transistor Q3 and resistor unit R3 are equivalent in design to form a variable _resistor , so that the spike pulse of node _N ' The observed impedance value is small, so the voltage variation caused by the spike pulse will be quickly discharged through the resistor R3, so there will be no misoperation when the power converter 200 is turned on; and when the digital latch control circuit 210 starts When the supply voltage V _CC is latched at the first predetermined level V ₁ , since the converted voltage V _CC ' still needs to be above at least one specific level to maintain the circuit operation of the digital latch control circuit 210, it cannot A small resistor with a fixed resistance value is directly used as the anti-spike interference circuit, so the transistor Q3 used in this embodiment is a preferred design choice for the circuit.

Referring to FIG. 3 and FIG. 4 in conjunction, FIG. 3 is a schematic diagram of the digital latch control circuit 210 shown in FIG. 2 under normal operation and under latch operation, and FIG. Relevant timing diagrams under normal operation and latch operation. As shown in the upper part of Figure 3, during normal operation, because the supply voltage V _CC does not have an overvoltage situation, the overvoltage protection trigger signal OVP _trigger will continue to be at a low logic level (the time point t shown in Figure 4 ₁ ), the NOR gate 2115 outputs a reset control signal S _reset with a high logic level to the reset input CL of the D-type flip-flop 2120, so the D-type flip-flop 2120 will reset according to the received control signal S _reset , output the output signal V _Q with a low logic level to the inverter 2125 through the data output terminal Q, and the inverter 2125 inverts the output signal V _Q to obtain the control signal S _c with a high logic level, at this time The control signal _Sc will turn on the transistor _Q2 and not turn on the transistor _Q1 , the supply voltage V _CC itself does not have any path to the ground level, so the voltage conversion circuit 205 will operate normally.

When an overvoltage occurs in the supply voltage V _CC (as shown in the lower part of FIG. 3 ), the digital latch control circuit 210 will start to perform a latch operation (after the time point _t1 ) at this time. voltage so that the overvoltage protection trigger signal OVP _trigger will have a short pulse with a high logic level, which will make the NOR gate 2115 output a reset control signal S _reset with a low logic level, and the D-type flip-flop 2120 receives After the reset control signal S _{reset with} a low logic level and the overvoltage protection trigger signal OVP _trigger with a short pulse with a high logic level are received through the frequency input terminal at the same time, the converted voltage V received by the data input terminal D will be converted to _CC ' is delivered to the output terminal as its output signal V _Q , although the converted voltage V _CC ' is a voltage with a lower level value obtained from the supply voltage V _CC via the voltage regulator 2105 , however, the converted voltage V _CC ' The level value is still a high logic level for the D-type flip-flop 2120 and the inverter 2125, therefore, the control signal _Sc output by the inverter 2125 will be switched from the original high logic level to the low logic level , _so that _the transistor _Q1 will be turned on and the transistor _{Q2 will} not be turned on _. R ₃ is connected to the ground level, depending on the result of voltage division, the converted voltage V _CC ' will be latched at the second predetermined level V ₂ , so that the supply voltage V _CC will be latched at the first predetermined level V ₁ , wherein the first predetermined level V ₁ is designed such that the voltage converting circuit 205 is in a disabled state and cannot operate, and the abnormal situation needs to be eliminated after replugging. In this way, the user of the power converter 200 may infer that the power converter 200 is abnormal by finding that the voltage conversion circuit 205 is in a disabled state during use, and thus needs to be replugged to eliminate the abnormal situation.

Referring to FIG. 5 , FIG. 5 is a schematic waveform diagram of the supply voltage V _CC shown in FIG. 2 . As shown in FIG. 5 , the overvoltage of the supply voltage V _CC occurs at _the time point t ₁ and is latched at the first predetermined level V ₁ at the time point t _{2 .} The power converter 200 is plugged and unplugged again, and after the time point _t4 , the power converter 200 can operate normally because it is plugged and unplugged again to eliminate the original abnormal situation. In addition, in terms of circuit practice, the digital latch control circuit 210 is a digital circuit, and there is no problem of high-impedance nodes in the known latch control circuit due to the use of an analog circuit, so the power converter 200 of this embodiment has a relatively high High anti-spike interference capability, so there is no need to use other circuits with anti-spike interference function when the circuit system is turned on, and it is also avoided to provide additional current to the circuit when it is turned on.

Furthermore, the voltage regulator 2105 is an optional circuit component, which can be removed in another embodiment. Referring to FIG. 6 , FIG. 6 is a schematic diagram of a power converter 600 according to another embodiment of the present invention. In this embodiment, even without a voltage regulator, the power converter 600 can also realize the above-mentioned operation of locking the supply voltage V _CC at a specific level, so it also belongs to the scope of the present invention; , the circuit components and connections of the power converter 600 are the same as the circuit components and connections of the power converter 200 shown in FIG. The detailed operation process is not described in detail here in order to avoid excessive length.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the protection scope of the present invention shall fall within the scope of the present invention.

Claims (10)

1. power supply changeover device with overvoltage protection comprises:

Voltage conversion circuit has transformer, and this transformer has first side winding, secondary side winding and auxiliary winding, wherein should be used to provide supply voltage by auxiliary winding; And

Digital latch control circuit is coupled to this voltage conversion circuit, and the voltage level that is used for will supplying according to the overvoltage protection triggering signal voltage is latched in first predetermined level;

Wherein when this voltage level was latched in this first predetermined level, this voltage conversion circuit was in disabled status.

2. power supply changeover device as claimed in claim 1, wherein this digital latch control circuit comprises:

Switch element, have the first transistor and transistor seconds, this switch element according to control signal come optionally conducting this first, second transistorized one of them, wherein first end of this first transistor is coupled to this supply voltage, first end of this transistor seconds is coupled to earth level, this first, second transistorized control end is coupled to this control signal, and this first, second transistorized second end is coupled to each other;

Resistance unit is coupled to this earth level and this first, second transistorized this second end; And

Control module is coupled to this resistance unit and this switch element, is used for producing this control signal to control this switch element according to the voltage level on this overvoltage protection triggering signal, this supply voltage and this first, second transistorized this second end;

Wherein the state of controlling this first transistor when this control module is conducting and the state of controlling this transistor seconds during for not conducting, and this voltage level of this supply voltage is latched at this first predetermined level.

3. power supply changeover device as claimed in claim 2, wherein this control module comprises:

NOR gate is coupled to this first, second transistorized this second end, is used for receiving this voltage level and this overvoltage protection triggering signal that are positioned on this first, second transistorized this second end, with the output reset control signal;

Trigger has and is coupled to this NOR gate with the replacement input that receives this reset control signal, in order to the data input pin that receives this supply voltage, in order to the frequency input that receives this overvoltage protection triggering signal and in order to produce the data output end of output signal; And

Inverter is coupled to this trigger, is used for anti-phase this output signal to obtain this control signal.

4. power supply changeover device as claimed in claim 2, it also comprises:

The deglitch interfered circuit is coupled to this first, second transistorized this second end.

5. power supply changeover device as claimed in claim 4, wherein this deglitch interfered circuit comprises:

The 3rd transistor has first end, second end and control end, and the 3rd transistorized this first end is coupled to this first, second transistorized this second end, and the 3rd transistorized this second end and this control end are coupled to this earth level.

6. power supply changeover device as claimed in claim 1, also comprise pressurizer, be coupled to this voltage conversion circuit, be used for to supply voltage after the conversion that voltage transitions becomes to be lower than this supply voltage, wherein this digital latch control circuit is coupled to this pressurizer, be used for to change back voltage and be latched in second predetermined level, be latched in this first predetermined level with this voltage level that will supply voltage.

7. digital latch control circuit that is applied to overvoltage protection; the auxiliary winding of power supply changeover device is used to provide supply voltage; this digital latch control circuit is used for according to the overvoltage protection triggering signal; the voltage level of this supply voltage is latched in first predetermined level, and this digital latch control circuit comprises:

Switch element, have the first transistor and transistor seconds, this switch element according to control signal come optionally conducting this first, second transistorized one of them, wherein first end of this first transistor is coupled to this supply voltage, first end of this transistor seconds is coupled to earth level, this first, second transistorized control end is coupled to this control signal, and this first, second transistorized second end is coupled to each other;

Resistance unit is coupled to this earth level and this first, second transistorized this second end; And

Control module is coupled to this resistance unit and this switch element, is used for producing this control signal to control this switch element according to the voltage level on this overvoltage protection triggering signal, this supply voltage and this first, second transistorized this second end;

Wherein the state of controlling this first transistor when this control module is conducting and the state of controlling this transistor seconds during for not conducting, and this voltage level of this supply voltage is latched at this first predetermined level.

8. digital latch control circuit as claimed in claim 7, wherein this control module comprises:

NOR gate is coupled to this first, second transistorized this second end, is used for receiving this voltage level and this overvoltage protection triggering signal that are positioned on this first, second transistorized this second end, with the output reset control signal;

Trigger has and is coupled to this NOR gate with the replacement input that receives this reset control signal, in order to the data input pin that receives this supply voltage, in order to the frequency input that receives this overvoltage protection triggering signal and in order to produce the data output end of output signal; And

Inverter is coupled to this trigger, is used for anti-phase this output signal to obtain this control signal.

9. digital latch control circuit as claimed in claim 7, it also comprises:

The deglitch interfered circuit is coupled to this first, second transistorized this second end.

10. digital latch control circuit as claimed in claim 9, wherein this deglitch interfered circuit comprises:

The 3rd transistor has first end, second end and control end, and the 3rd transistorized this first end is coupled to this first, second transistorized this second end, and the 3rd transistorized this second end and this control end are coupled to this earth level.

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