CN101477456B - Self-correlated arithmetic unit and processor - Google Patents

Abstract

The invention discloses an autocorrelation operation unit and a processor. The autocorrelation operation unit includes: a correlation number processing unit, a multiplier, an adder, a second shift register and a register. Configure the function of the relevant operation unit, read the source operand in sequence according to the order of the data elements in the source operand and perform the autocorrelation operation, and output several data elements of the destination operand in sequence, so as to perform the autocorrelation operation Instructions can be read, decoded and executed only once, which simplifies the complexity of autocorrelation operations.

Description

A kind of autocorrelation operation unit and processor

【Technical field】

The invention relates to the field of integrated circuit design, in particular to a processor and an autocorrelation computing unit.

【Background technique】

In the communication field, it is often necessary to perform various operations on a sequence of data elements, such as autocorrelation operations. Figure 1 is a schematic diagram of the principles of autocorrelation operations. The data stream 100 moves one bit along the data stream direction every sampling period, and the arrow indicates the data stream direction. The data stream 100 includes a number of data elements 101, 102 and 103 which are the latest data elements entering and the ones about to exit window A 106, respectively. 104 and 105 are the latest data elements entering and about to exit window B107 respectively. The result of the autocorrelation operation is the sum of the products of the conjugate values of the multiple data elements entering window A and the corresponding multiple data elements entering window B. When the data elements 102 and 104 are the same data, it becomes a special mode of autocorrelation operation, that is, the operation of calculating the average power of the data elements. Existing processors need to take two source operands each time when processing autocorrelation operations, then store the result of the multiplication into memory, and then add/subtract the previous autocorrelation result, so the operation is complicated and needs to be improved .

【Content of invention】

The main technical problem to be solved by the present invention is to provide a processor and an autocorrelation computing unit to simplify the complexity of the autocorrelation computation.

In order to solve the above-mentioned technical problems, the present invention provides an autocorrelation operation unit, comprising: a correlation number processing unit, a multiplier, an adder, a second shift register and a register, and the correlation number processing unit includes a first shift register, The input terminal of the first shift register is used to input the data elements of the source operand, and its output terminal is connected to a multiplier, and the input terminals of the multiplier are respectively used to input the data elements of the source operand and the output of the relevant number processing unit The result, the output end of the multiplier is connected to the adder and the second shift register respectively, the input end of the adder is also connected to the output end of the second shift register and the output end of the register respectively, and the output end of the adder The output terminal is respectively connected to the input terminal of the register and the data element for the output destination operand.

The correlation number processing unit also includes a conjugate unit, the input of the conjugate unit is connected to the output of the first shift register, and the output of the conjugate unit is connected to a multiplier; or the conjugate The input end of the unit is used to input the data elements of the source operand, the output end of the unit is connected to the input end of the first shift register, and the output end of the first shift register is connected to the multiplier.

According to another aspect of the present invention, a processor is also provided, including an algorithm data control unit, a configuration register, and at least one arithmetic and logic operation unit, and the arithmetic and logic operation unit includes at least the above-mentioned autocorrelation operation An autocorrelation operation unit, the algorithm data control unit is connected to a configuration register, and the configuration register is connected to an autocorrelation operation unit, and the algorithm data control unit executes an autocorrelation operation instruction, and sends first configuration information to the configuration register, and the configuration register is connected to the first configuration information. The autocorrelation computing unit configures its own functions according to the first configuration information.

The beneficial effect of the present invention is that: the processor configures the function of the autocorrelation operation unit by executing the autocorrelation operation instruction, reads the source operands sequentially according to the order of the data elements in the source operands, and performs the autocorrelation operation The unit sequentially complex-multiplies the most recently read data element in the source operand with the conjugate value of the previously read data element in the first source operand to obtain a complex or real product result; The product result is subtracted from the product result corresponding to the previously read data element in the source operand, and added to the autocorrelation result corresponding to the previous data element of the latest read data element in the source operand to obtain An autocorrelation result of the destination operand corresponding to the most recently read data element in the source operand. And sequentially output several data elements of the destination operand, so that the autocorrelation operation instruction can be read, decoded and executed only once, which simplifies the complexity of the autocorrelation operation, and at the same time can reduce the size of the instruction memory and reduce the instruction decoding and power consumption for configuration operations.

【Description of drawings】

Fig. 1 is the schematic diagram of autocorrelation operation;

Figure 2A is a structural diagram of an embodiment of the present invention;

Fig. 2B is a structural diagram of another embodiment of the present invention;

Fig. 3 A is the structural diagram of an embodiment of the autocorrelation operation unit in the present invention;

Fig. 3B is a structural diagram of another embodiment of the autocorrelation operation unit in the present invention;

FIG. 3C is a structural diagram of another embodiment of the autocorrelation operation unit in the present invention.

【Detailed ways】

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

The following description describes an embodiment of a technique for performing autocorrelation or averaging power operations in a processing device, computer, or software program. In the following description, numerous specific details are set forth, such as processor types, microarchitectures, boot mechanisms, etc., in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without such specific details as described. Although the following embodiments are described with reference to digital signal processors, other embodiments are applicable to other types of integrated circuits and logic devices.

If the data processing is carried out according to the algorithm characteristics of data signal processing, the overall performance of the processor can undoubtedly be improved. For example, in the field of broadband communication, the baseband processing part of the system generally has the structural characteristics of pipeline or stream processing. Each processing module receives several data streams with homogeneous data elements, and generates several new data streams with homogeneous data elements through several repeated operations. For the processing of this kind of data with higher regularity, it is beneficial to use the execution unit with larger granularity to process the data quickly. For example, the above-mentioned repeated operation may be processed by an execution unit in the processor. Since this execution unit performs the same processing each time, and the location and addressing method of storing the source operand are relatively fixed, each repeated operation does not need to repeatedly read and decode instructions. The configuration of the execution unit is completed by executing an instruction operation (which can be completed by one instruction or multiple instructions) before data stream processing or when processing starts. Execution units are preferably data-driven. In this way, the execution unit executes an operation every time it receives a piece of data. The number of received data required to complete a task can be indicated in the instruction, that is, the number of data units included in the source operand. If all the data units in the source operand are processed and the results are output, the execution unit immediately stops working and waits for the next configuration and task.

Embodiments of the invention include means for implementing autocorrelation operations. Figure 1 is a schematic diagram of the principle of autocorrelation operation. The result of the autocorrelation operation is the sum of the complex product of multiple data elements entering window A and the corresponding conjugate values of multiple data elements entering window B, and the autocorrelation result of the previous operation is always known, Therefore, the current autocorrelation operation is actually the autocorrelation result of the previous operation plus the complex product result of the conjugate value of the latest data element 102 entering window A and the conjugate value of the latest entering window B data element 104 and subtracting the result of the complex number that will be moved out of window A The complex product result of data element 103 and the conjugate value of data element 105 to be shifted out of window B. According to the flow direction of the data stream, the data stream enters window A first. Before window B receives the first data element of the data stream, the data elements in window B can be understood as zero-valued, so the autocorrelation value is zero. When window B receives the first data element of the data stream, the autocorrelation values start to have real meaning. And when the first data element of the data stream becomes 105, the autocorrelation result starts outputting. Therefore, when the data elements of the data stream enter window A but not window B, there is no need to perform autocorrelation operation; when the first data element enters window B, the autocorrelation operation starts, but the autocorrelation result is kept and not sent to Outer output; when the first data element is moved out of window B, perform an autocorrelation operation, retain and output the autocorrelation result. Afterwards, the data stream outputs an autocorrelation result every time a data element bit is shifted. Until the last data element of the data stream enters window A, the last autocorrelation result is output at this time.

The source operand of the continuous autocorrelation operation is the above-mentioned data stream, which includes several data elements. The embodiment of the present invention is used to perform autocorrelation operation on source operands with a certain number of data elements.

Please refer to FIG. 2A, in one embodiment, the processor 200 that completes the autocorrelation operation includes an algorithm data control unit (abbreviated as ADU) 203, a configuration register 205, and at least one arithmetic logic operation unit, and the arithmetic logic operation unit includes at least one For the autocorrelation operation unit 201 that performs the autocorrelation operation, the algorithm data control part 203 is connected with the configuration register 205, and the configuration register 205 is connected with the autocorrelation operation unit 201, and the autocorrelation operation unit 201 is also respectively connected with the source operand input source and the destination operation The data output source is connected, and the algorithm data control unit 203 executes the configuration instruction. In this embodiment, the autocorrelation operation instruction is executed, and the first configuration information is sent to the configuration register 205. The autocorrelation operation unit 201 performs its own function according to the first configuration information. to configure.

In this embodiment, the algorithm data control unit 203 includes a storage unit 204 for storing instructions or data and a decoding unit 214 for decoding instructions. In other embodiments, the algorithm data control unit may also include other unit. In this embodiment, the configuration instruction executed by the algorithm data control unit includes an operation code, configuration information, and configuration purpose. The operation code is a command code specifying the operation performed by the instruction. The configuration information is the object of the instruction operation. The configuration register that enters the configuration information, for the autocorrelation operation instruction, the configuration information includes the number of data elements of the source operand, the window length of the autocorrelation operation, and the distance between the two windows. In other embodiments, the configuration information can also be Include additional information. The algorithm data control part 203 reads the autocorrelation operation instruction in the storage unit 204, decodes the instruction through the decoding unit 214, writes the first configuration information obtained by decoding into the configuration register 205, and the autocorrelation operation unit 201 according to the first configuration information A configuration information is used to configure the function, and realize the setting of specific parameters of the autocorrelation operation, such as the number of data units contained in the source operand, the window length of the autocorrelation operation, and the distance between two windows in the autocorrelation operation. The data elements of the source operand can come directly from the port of the digital signal processor, or from the internal register or data memory of the digital signal processor, that is, the input source of the source operand can be the port, internal register or data memory of the processor . Similarly, the data elements of the destination operand can be stored in the port, internal register or data memory of the digital signal processor, that is, the output source of the destination operand can also be the port, internal register or data memory of the processor.

The processor executes the autocorrelation instruction of single instruction multiple data input multiple data output on the source operand, configures the function of the autocorrelation operation unit, and reads and executes the source operand in sequence according to the order of the data elements in the source operand , and sequentially output several data elements of the destination operand, so that the autocorrelation operation instruction can be read, decoded and executed only once, simplifying the complexity of the autocorrelation operation.

Please refer to FIG. 2B. In another embodiment, the main difference between the processor 200 that completes the autocorrelation operation and the above-mentioned embodiment is that it also includes an interconnection logic unit 206, and the configuration register 205 is also connected with the interconnection logic unit 206. The algorithm data control The component 203 also executes other configuration instructions, sends the second configuration information to the configuration register 205, and the interconnection logic unit 206 configures the input path of the source operation data and the output path of the destination operation data according to the second configuration information.

In this embodiment, the processor 200 includes a plurality of arithmetic logic operation units (ALU) 202 for performing digital signal processing, and an algorithm data control unit (ADU) for reading and decoding instructions to generate configuration information of functions and connection relations. ) 203, a configuration register (Config) 205 that stores configuration and control information obtained through instruction decoding, and is responsible for configuring the connection relationship between the ALU and ports (Ports), the connection relationship between multiple ALUs, and the connection relationship between multiple ports The interconnect logic unit 206, and the port 208 responsible for the connection with the bus 209 between the external processor units. The functions that the ALU can complete include but are not limited to: addition, subtraction, multiplication, multiplication accumulation, and, or, XOR, left arithmetic/logic shift, right arithmetic/logic shift, comparison, transfer, etc. Arithmetic and logical operations . For example, the ALU 201 that performs autocorrelation calculations can complete complex calculation tasks, and can be configured to implement autocorrelation calculation processing of a data stream including multiple data elements. The interconnection logic unit 206 includes a register (Reg) 207 for data exchange between multiple ALUs. 211 and 212 are control buses for configuring ALU functions and configuring connections between ALUs and ports, respectively. 210 is a data bus between the ALU and interconnect logic unit 206 . 213 is a data bus between port 208 and interconnection logic 206 .

In this embodiment, the flow process of the autocorrelation operation is: ADU203 reads and decodes the autocorrelation instruction in the memory unit MEM204, and writes the configuration information of the function and the connection relationship obtained by decoding into the configuration register 205; the autocorrelation ALU201 and The interconnection logic unit 206 completes the configuration of the function and connection relationship according to the information in the configuration register 205, and the function configuration realizes the setting of the specific parameters of the autocorrelation operation, such as the number of data units contained in the source operand and the window length of the autocorrelation operation and the distance between two windows in the autocorrelation operation, the connection relationship configuration realizes the setting of the position of the source operand and the destination operand of the autocorrelation operation. The source operand input source can be at least one of the port 208 of the processor, the internal register 207 and the data memory, and the destination operand output source can also be at least one of the port 208 of the processor, the internal register 207 and the data memory, or Can be a different port or register than the input source of the source operand. The interconnect logic unit 206 selects the input and output paths according to the second configuration information. For example, after the configuration is completed, the autocorrelation ALU201 can read the data in the port 208 or the register (Reg) 207 to start a continuous autocorrelation operation, and output the result of the autocorrelation operation to the port 208 or the register (Reg) 207 .

In the above-mentioned embodiment, the processor adopts the data-driven mode, and if there is data, it will be processed, and the output processing result will be stored in the corresponding port or register. After all the data elements are output, stop processing and wait for the next configuration.

The autocorrelation operation unit for performing the autocorrelation operation according to the above-mentioned embodiments includes a correlation number processing unit, a multiplier, an adder, a second shift register, and a register. The input terminal of the correlation number processing unit is used to input the data elements of the source operand, the input terminals of the multiplier are respectively used to input the data elements of the source operand and the output result of the correlation number processing unit, and the output terminals of the multiplier are respectively connected to the adder and the second shift register, the input end of the adder is also respectively connected to the output end of the second shift register and the output end of the register, and the output end of the adder is respectively connected to the input end of the register and the data element for outputting the destination operand .

The correlation number processing unit is used to determine the correlation number to be multiplied with the data element of the input source operand. The data element of the input source operand is the first data element entering window A. When the data element in the source operand is For real numbers, the relevant number multiplied with the data elements of the input source operand is the first data element entering window B. When the data elements in the source operand are complex numbers, the correlation number multiplied with the data elements of the input source operand is the conjugate value of the first data element entering window B.

The following takes the data elements in the source operand as complex numbers as an example for illustration.

FIG. 3A is a logic block diagram of an embodiment of the autocorrelation operation unit according to the above embodiment. The data elements in the source operand are complex numbers, and the relevant number processing unit includes a first shift register (i.e., a source operand data element shift register) 300 and a conjugate unit 306, and the input of the source operand data element shift register 300 End is used for the data element of input source operand, and its output end connects and asks the input end of conjugate unit 306, asks the output end of conjugate unit 306 to connect multiplier, in the present embodiment, multiplier is complex number multiplier 307, addition The second shift register is a complex multiplication result shift register 301, and the register is an autocorrelation result register 309. The input source operand data elements are sent to the complex multiplier 307 one way, and the source operand data elements are sent to the first register bit 303 on the left of the shift register 300 . The source operand data element shift register 300 stores the source operand or part of the data elements thereof, and each time a data element of the source operand is newly received, the data in the source operand data element shift register 300 moves one bit in a certain direction, A previously stored data element of the source operand is discarded, while a newly received data element is stored in the empty bit register location in the source operand data element shift register 300 resulting from the shift. The last register bit 302 of shift register 300 corresponds to the most recent data element 104 entering window B in FIG. 1 . Therefore, the effective length of the shift register 300 is the distance between the first data elements respectively entering the two windows in FIG. 1 , that is, the distance between window A and window B. The data element (i.e. the data element 302 in the register) of a source operand that is about to be discarded due to shifting in the source operand shift register is obtained through the conjugate unit 306, and the result is combined with the newly received source operand Complex multiplication by one data element. The output result of the complex multiplier 307 is sent to the complex adder 308 one way, and the first register bit 304 on the left side of the complex multiplication result shift register 301 is sent all the way. The complex multiplication result shift register 301 stores the complex multiplication results corresponding to some data elements of the source operands, and each time a complex multiplication result is newly generated, the data in the complex multiplication result shift register 301 moves one bit in a certain direction, and one bit is discarded. The complex multiplication result corresponding to the data element of the previously stored source operand, and simultaneously a new complex multiplication result is stored in the vacancy register unit generated by shifting in the complex multiplication result shift register 301; the complex multiplication result shift register The length of 301 is the window length of the autocorrelation operation, that is, the length of window A or window B, the length of window A and window B is equal, and 305 is the last register bit, and its storage value corresponds to the data flow data element 103 in Figure 1 The product result with the conjugate value of 105. The complex adder 308 receives three input data, which are the previous autocorrelation value, the current complex multiplier result and the value stored in the register 305 . The input value stored in the register 305 is subtracted by the subtractor in the complex adder 308 . The output result of the complex adder is stored in the correlation value register 309 one by one, and output as the data element of the destination operand. The correlation value register 309 stores the autocorrelation result corresponding to the previous data element of the latest read data element in the source operand.

Each time the two shift registers receive one piece of data, they automatically move one register bit to the specified direction. In this embodiment, each time the two shift registers receive one piece of data, they automatically move one register bit to the right. In other embodiments, the two shift registers can also be defined to automatically shift one register bit to the left each time a piece of data is received.

The operation process of the autocorrelation operation in this embodiment is as follows: multiply the conjugate value of a data element newly read in the source operand by a conjugate value of a data element previously read in the source operand to obtain a complex OR Product result of a real number; subtracts this product result from the product result corresponding to the previously read data element of the source operand, and corresponding to the previous data element of the most recently read data element of the source operand The autocorrelation results are added together to obtain an autocorrelation result of the destination operand corresponding to the latest read data element in the source operand.

FIG. 3B is a logic block diagram of another embodiment of the autocorrelation operation unit according to the above embodiment. The data elements in the source operand are still complex numbers. The difference from the embodiment in FIG. 3A lies in the position of the conjugate unit 306 and the replacement of the source operand data element shift register 300 . The first shift register is the source operand data element conjugate value shift register 310 , the input source operand is directly conjugated, and then stored in the source operand data element conjugate value shift register 310 . The first register bit and the last register bit of shift register 310 are 311 and 312, respectively.

When the data element in the source operand is a real number, the correlation number processing unit may not need to seek the conjugate, so the correlation number processing unit includes a first shift register, and the length of the first shift register is the same as that in Fig. 3A and Fig. 3B The length of the first shift register is the same, the input terminal of the first shift register inputs the data element of the source operand, and its output terminal is connected to the multiplier, and the input data element is shifted and then multiplied by the current input data element . Correspondingly, the multiplier and the adder are also real number multipliers and real number adders respectively.

For the shift register in the above embodiments, its effective length is determined by the functional configuration information obtained from instruction decoding. That is to say, the autocorrelation operation unit includes two relatively long shift registers, and when actually performing the autocorrelation operation, the source operand data element shift register 300 (or source operand data element shift register 300) is respectively determined according to the functional configuration information. The effective length of the conjugate value shift register 310) and the complex multiplication result shift register 301. As mentioned above, the effective length of the shift register 300 (or 310) is the distance between the two windows of the autocorrelation operation, that is, the distance between the first data elements entering the two windows respectively in Fig. 1, the shift The length of the register 301 is the window length of the autocorrelation operation.

When the effective length of the shift register 300 (or 310 ) is zero, it indicates that the two windows overlap, and the corresponding operation changes from an autocorrelation operation to a power calculation operation.

FIG. 3C is a logic block diagram of an ALU for averaging power operations. When the effective length of the source operand data element shift register 300 or the source operand data element conjugate value shift register 310 is zero, the autocorrelation operation unit can be used to find the average power of a certain number of data elements, assuming that The average power of the data elements in window A, the power of each element actually refers to the square of its absolute value, so the algorithm is to find the square of the absolute value of each element in window A (you can pass the data itself and its conjugate value multiplied together), and then averaged over the number of elements in the window). When calculating the average power of a certain number of data elements, an averaging logic unit 313 needs to be added on the basis of the above embodiments. In addition, the conjugate unit 306 directly calculates the conjugate value of a data element newly read from the source operand, and the complex multiplier 307 performs a complex multiplication operation on a data element newly read from the source operand and its conjugate value to obtain output a real value; the complex multiplication result shift register 301 stores the real multiplication result corresponding to some data elements of the source operand, and every time a new real number multiplication result is generated, the data in the complex multiplication result shift register moves a certain direction. bits, discard a previously stored real number product result corresponding to the data element of the source operand, and simultaneously store a new real number product result into the empty bit register unit generated by shifting in the complex multiplication result shift register. The correlation value register 309 is changed to a power value register 314, and the power value register 314 stores the sum of power corresponding to the previous data element of the latest read data element in the source operand. The complex number adder 309 is changed to a real number adder 315 . Real number adder 315 carries out subtraction operation with a real number multiplication result that is newly produced and a real number product result that is about to be discarded due to shifting in the complex multiplication result shift register, and the previous data element corresponding to the power value register. The power value results are added to obtain the sum of the power corresponding to the latest data element read by the source operand. The averaging logic unit 313 averages the sum of the powers obtained by the real number adder to obtain the average power of some data elements of the source operand. Since the output of the real number adder 315 is the sum of the powers of multiple data elements, the function of the averaging logic unit 313 is to find the average power of the data elements within a certain window length. The easiest way to do this is by shifting to the right.

The operation process of this embodiment is: perform complex multiplication of a data element newly read in the source operand and the conjugate value of a data element newly read in the source operand to obtain a product result of a real number; A product result is subtracted from the product result corresponding to a previously read data element in the source operand, and is added to the sum of the power corresponding to the previous data element of the latest read data element in the source operand, And calculate the average to obtain an average power of the destination operand corresponding to the latest read data element in the source operand.

The same techniques and theories of the present invention can be readily applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of the invention apply to any processor or machine that performs data operations. However, the invention is not limited to processors or machines that perform 64-bit, 32-bit, or 16-bit data operations.

According to one aspect of the present invention, there is provided a machine-readable medium having stored thereon instructions which, when executed by a machine, cause the machine to perform a method comprising: sequentially reading or a data element of a source operand of a real number characteristic data value; determine a correlation result between the newly read plurality of data elements in the source operand and the previously or newly read plurality of data elements in the source operand; store the Associative result, that is, a data element that sequentially stores a plurality of destination operands having data values of complex or real nature.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (9)

1. An autocorrelation operation unit is characterized in that comprising: a correlation number processing unit, a multiplier, an adder, a second shift register and a register, and the correlation number processing unit includes a first shift register, and the first The input end of the shift register is used to input the data elements of the source operand, and its output end is connected to a multiplier, and the input ends of the multiplier are respectively used to input the data elements of the source operand and the result output by the correlation number processing unit, so The output end of the multiplier is connected to the adder and the second shift register respectively, the input end of the adder is also connected to the output end of the second shift register and the output end of the register respectively, and the output end of the adder is connected respectively The input to the register and the data element for the output destination operand. 2. autocorrelation operation unit as claimed in claim 1, is characterized in that: described correlation number processing unit also comprises seeking conjugation unit, and the input end of described conjugation unit is connected the output end of the first shift register, The output terminal of the conjugate unit is connected to the multiplier; or the input terminal of the conjugate unit is used to input the data element of the source operand, and the output terminal is connected to the input terminal of the first shift register, and the first shift register The output terminal of the bit register is connected to the multiplier. 3. autocorrelation computing unit as claimed in claim 1 or 2, is characterized in that: the length of described first shift register is the distance between two windows of autocorrelation operation, the length of described second shift register The length is the window length of the autocorrelation operation. 4. The autocorrelation operation unit according to claim 3, characterized in that: each time the first shift register and the second shift register receive a piece of data, they automatically shift one register bit in a specified direction. 5. autocorrelation operation unit as claimed in claim 1 or 2, is characterized in that: the length of described first shift register is 0, and described autocorrelation operation unit also comprises averaging logic unit, and described averaging logic The input end of the unit is connected to the output end of the adder, and the output end is used to output the destination operand data element. 6. A processor, comprising an algorithm data control unit, characterized in that it also includes: a configuration register and at least one arithmetic and logic operation unit, and the arithmetic and logic operation unit includes at least one according to any one of claims 1 to 5 An autocorrelation operation unit for performing autocorrelation operations, the algorithm data control part is connected to the configuration register, the configuration register is connected to the autocorrelation operation unit, the algorithm data control part executes the autocorrelation operation instruction, and sends the configuration register The first configuration information is sent, and the autocorrelation computing unit configures its own function according to the first configuration information. 7. The processor according to claim 6, wherein the first configuration information includes the number of data elements of the source operand, the window length of the autocorrelation operation, and the distance between two windows. 8. The processor according to claim 6 or 7, characterized in that: it also includes an interconnection logic unit, the configuration register is also connected to the interconnection logic unit, and the algorithm data control part also executes a configuration instruction to the configuration The register sends the second configuration information, and the interconnect logic unit configures the input path of the source operation data and the output path of the destination operation data according to the second configuration information. 9. The processor according to claim 6, wherein the arithmetic data control unit comprises a storage unit for storing instructions or data and a decoding unit for decoding instructions.

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