CN101471129A - Device and method for adjusting chip output current - Google Patents

Abstract

A chip output current adjusting device and method, comprising: the driving circuit is used for outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in another chip to generate an output voltage; and a detection circuit, coupled to the driving circuit, for detecting the output voltage and a reference voltage to generate the control signal; the control signal is used for controlling the parallel number of NMOS transistors or PMOS transistors in the driving circuit so as to adjust the current quantity of the driving current.

Description

Device and method for adjusting chip output current

technical field

The invention relates to a current adjusting device and method, in particular to a chip output current adjusting device and method.

Background technique

Generally speaking, the design of Dynamic Random Access Memory (DRAM) can be divided into several types such as SDR DRAM and DDR DRAM. Among them, the data of SDR DRAM can be accessed once every clock cycle, for example: a data group is transmitted once at the positive edge of the clock. Therefore, SDRDRAM is called a single data rate (SDR) memory module. In addition, for DDR DRAM, it is also a dynamic random access memory like SDR DRAM, but DDR DRAM uses a double data rate (DDR) technology for data access. Through the technology of double-speed data transmission and extraction, DDR DRAM can transmit data groups twice in one clock cycle, that is, once on the positive edge and negative edge of the clock, and the positive edge of the clock cycle is called rising time (rising time). time); the negative edge of the clock cycle is called the falling time (falling time). Among them, in the application of DDR DRAM, one thing to pay attention to is that the rise time and fall time should be kept almost the same, otherwise it will cause distortion of the duty cycle (that is, the duty cycle is not 50%), which will affect the Timing margin to rise time and fall time. Therefore, in order to keep the rising time and the falling time nearly consistent, the charging current and the discharging current must be adjusted, that is, the output current of the driving circuit in the chip needs to be properly calibrated.

In the known method of calibrating the output current, it is usually necessary to add an external resistor on the printed circuit board (PCB) for the chip to perform current correction. However, this method not only needs to add an external resistor but also consumes extra pins to achieve the correcting action. In this way, the cost will be increased. For the trend of miniaturization of semiconductor chips, each pin in the chip is very precious. Therefore, it is urgent to propose a new calibration method to solve the shortcomings of the known technology.

Contents of the invention

In view of this, the present invention proposes a device and method for adjusting chip output current. The device and method proposed by the present invention can save external resistors and complete the control of the drive current output by the chip.

The present invention proposes a chip output current adjusting device comprising: a driving circuit for outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in another chip to generate an output voltage; and A detection circuit, coupled to the driving circuit, used to detect the output voltage and a reference voltage to generate the control signal; wherein, the control signal controls a parallel number of NMOS transistors or PMOS transistors in the driving circuit to adjust The current magnitude of the drive current.

The present invention also provides a method for adjusting the output current of a chip, which includes the following steps: outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in another chip to generate an output voltage; and detecting The output voltage and a reference voltage are used to generate the control signal; wherein, the control signal controls a parallel connection number of NMOS transistors or PMOS transistors to adjust the current amount of the driving current.

The preferred embodiments of the present invention and their effects are described below in conjunction with the accompanying drawings.

Description of drawings

Figure 1: Schematic diagram of the first embodiment of the present invention.

Figure 2: Schematic diagram of the second embodiment of the present invention.

Fig. 3: Schematic diagram of the third embodiment of the present invention.

Fig. 4: Flow chart of the current adjustment method of the present invention.

[Description of main component symbols]

Vdd: working voltage

10: Die termination resistor

20: Data signal pin

30: detection circuit

32: input terminal

34: output terminal

36: Comparator

361: Comparator for PMOS

362: Comparator for NMOS

38: Logic control circuit

381: Logic control circuit for PMOS

382: Logic control circuit for NMOS

40: Drive circuit

42: PMOS

44: NMOS

Detailed ways

First, please refer to FIG. 1 , which is a schematic diagram of a first embodiment of the present invention. The device for adjusting the output current of the memory in the first embodiment includes: a die terminal resistor 10, a data signal (DQ) pin 20, a detection circuit 30 and a drive circuit 40, wherein the detection circuit 30 further includes a comparator 36 and a logic The control circuit 38 , the detection circuit 30 and the output driving circuit 40 are set in a memory control chip, and the chip terminal resistor 10 is set in a memory chip.

The Joint Electronic Engineering Design and Development Association (JEDEC) stipulates many specifications related to electronic engineering. Among them, regarding memory, such as DDR2, the on die termination (ODT) is one of the components that must be included in the memory specified by JEDEC . Die termination resistors are mainly terminators for DDR signals to maintain signal integrity and improve system stability. As the speed of the memory increases day by day, the chip terminal resistor is directly moved into the memory, which can shorten the distance and reduce the working time of the memory. In addition, another advantage of the chip termination resistor technology is that it can reduce the feedback under the high-speed operation of the memory, and improve the performance of the memory and the limit value of the clock.

Therefore, according to an embodiment of the present invention, an on-chip termination resistor (ODT) is used to provide the resistor required for current calibration through a built-in resistor in the memory chip. In this way, through the built-in chip termination resistor, it is used to correct the current output of the memory control terminal, and there is no need to add an additional resistor next to the memory module, which can reduce the number of printed circuit boards (traditionally, an additional resistor is soldered to the A printed circuit board for calibration) and the cost of external resistors.

In the first embodiment, an on-die termination resistor (ODT) built into the memory chip is used to provide a reference resistance value. Herein, the reference resistance value may be 50 ohms, but not limited thereto. In addition, the second chip can be a dynamic random access memory chip (DRAM).

Furthermore, according to one embodiment of the present invention, it is proposed to use the existing data signal pin (Data pin) or clock signal pin (Clock Pin) of the memory chip to replace the additional pin (referred to below as The data signal pin is used as an example for illustration). For 8bit memory, the data signal pins are DQ ₀ ~ DQ ₇ ; for 16bit memory, the data signal pins are DQ ₀ ~ DQ ₁₅ , and only one of the DQ pins is needed to control the output current. Correction. In this way, the problem in the conventional technology that the memory control terminal has no extra pins available can be solved, and at the same time, the cost of adding an extra pin can be solved.

In the first embodiment, one end of the data signal (DQ) pin 20 is coupled to the die termination resistor 10 , and the other end is coupled to the output driver 40 . And the data signal pin 20 outputs a driving current, and the driving current can be used to drive the memory to access data. Wherein, when the driving current flows through the chip termination resistor 10 , an output voltage will be generated on the chip termination resistor 10 .

The detection circuit 30 includes a comparator 36 and a logic control circuit 38 . The comparator 36 has an input terminal 32 and an output terminal 34 . Wherein, the input terminal 32 receives the output voltage of the die termination resistor 10 and the reference voltage for comparing the output voltage and the reference voltage to output a logic value, and the output terminal 34 is connected to the logic control circuit 38 . The logic control circuit 38 is coupled to the comparator 36 for generating a control signal according to the logic value and sending the control signal to the driving circuit 40 . Wherein, the above-mentioned logic control circuit 38 can be a finite state machine (Finite State Machine).

Here, the reference voltage is a programmable reference voltage. Wherein, the reference voltage can be 1/2 of the working voltage (Vdd), 3/4 of the working voltage or 1/4 of the working voltage, which will be described in more detail later, and the reference voltage is not limited to the above.

The driving circuit 40 itself has a resistance value, and the crystal grain terminal resistor 10 provides a reference resistance value, and the output voltage received by the input terminal 32 of the detection circuit 30 is the circuit formed by the driving circuit 40 and the grain terminal resistor 10. The voltage divider of the particle terminal resistor 10. Therefore, the reference voltage can be set as the voltage value of the circuit between the driving circuit 40 and the die termination resistor 10 after the average voltage is divided. Therefore, the detection circuit 30 compares the output voltage with the reference voltage to adjust the driving current output by the data signal pin 20 . That is to say, when the detection circuit 30 compares the output voltage with the reference voltage and finds that the two voltages are different, a logic value will be output from the output terminal 34 . The logic control circuit 38 generates a control signal to the driving circuit 40 according to the logic value, so that the data signal pin 20 can output different driving current values. When different driving current values flow through the chip terminal resistor 10, different output voltages will be generated. At this time, through the detection circuit 30, the new output voltage is compared with the reference voltage, and the above actions are repeated. The driving current output by the data signal pin 20 is adjusted. And when the output voltage is almost the same as the reference voltage, it means that the resistance value of the driving circuit 40 is almost the same as the reference resistance value of the chip terminal resistor 10, so the driving current output by the data signal pin 20 is the required memory driving current.

In addition, as shown in FIG. 1 , the current adjusting device is disposed in the memory control chip, and the memory control chip has a calibration mode and an operation mode. When the memory control chip operates in the calibration mode, the current regulating device is enabled. In contrast, when the memory control chip operates in the working mode, the current regulating device is disabled. Therefore, in the initial state, the memory control chip is operated in the correction mode first, that is, the current adjustment device performs the output current correction of the memory control chip. After a predetermined time, the memory control chip enters the working mode. At this time, the memory control chip Data access is performed on the memory chip. In this way, the operation of the current adjustment device can be started by switching between different modes of the memory control chip.

Please refer to FIG. 2 , which is a schematic diagram of a second embodiment of the present invention. The second embodiment clearly shows that the driving circuit 40 includes at least one PMOS 42 and at least one NMOS 44. In the second implementation, a plurality of PMOS 42 are connected in parallel with each other, and a plurality of NMOS 44 are also connected in parallel with each other, and each PMOS 42 and each NMOS 44 are connected in series.

When the clock cycle is positive, that is, at the rising time, the PMOS 42 is on and belongs to the charging state, and at this time, the NMOS 44 is off; on the contrary, when the clock cycle is negative, that is, at the falling time, the NMOS 44 is on and belongs to the discharging state. State, at this time PMOS 42 is off. Herein, the charge state and the discharge state will be described respectively as follows.

When in the charging state, since the PMOS 42 is on and the NMOS 44 is off, the required adjustment at this time is the parallel resistance value of the PMOS 42. Assumption: the reference resistance value provided by the grain termination resistor 10 is 50 ohms; the working voltage (Vdd) is 1.8 volts; since one end of the grain termination resistance 10 is grounded, the reference voltage is set to 1/2 the working voltage, namely 0.9 volts. Ideally, when the parallel resistance of the PMOS 42 is close to 50 ohms, and the drive current output by the data signal pin 20 flows through the grain termination resistor 10, due to the parallel resistance of the PMOS 42 and the grain termination resistance 10 The values of the reference resistors are almost the same, and the result of voltage division will cause the output voltage on the die terminal resistor 10 to be almost 1/2 of the working voltage, which is almost the same as the reference voltage.

However, due to many factors in the mass production of the semiconductor process, the actual situation will cause the parallel resistance value of the PMOS 42 to be inaccurate as expected, which is why the memory control terminal must be calibrated before use. Continuing to refer to FIG. 2 , assuming that the driving current output by the data signal pin 20 flows through the die termination resistor 10 , the output voltage generated is 1.0 volts. At this time, after the input terminal 32 of the detection circuit 30 receives the input voltage (1.0V), it is compared with the reference voltage (0.9V), and it is found that the input voltage is greater than the reference voltage, that is to say, the reference resistance value of the die terminal resistor 10 is greater than Parallel resistance value of PMOS 42. At this time, the output terminal 34 of the detection circuit 30 will send out a logic value, and the logic control circuit 38 will generate a control signal to the driving circuit 40 according to the logic value. Taking the current example as an example, since the parallel resistance of the PMOS 42 is relatively small, several of the PMOS 42 will be controlled to be turned off to increase the overall parallel resistance of the PMOS 42 . At this time, since the parallel resistance value of the PMOS 42 changes, the driving current output by the data signal pin 20 also changes accordingly, and the output voltage of the adjusted driving current flowing through the die terminal resistor 10 also changes accordingly. Then compare the adjusted output voltage with the reference voltage through the detection circuit 30, then further adjust the parallel resistance value of the PMOS 42, and repeat the above steps until the parallel resistance value of the PMOS 42 is almost equal to the reference resistance value. At this time, the driving current correction of the charging state in the driving circuit 40 is completed.

On the other hand, in the discharge state, the NMOS 44 is on and the PMOS 42 is off. The adjustment method is similar to the above-mentioned charge state. Drive current correction.

From the above description, it can be concluded that the detection circuit 30 adjusts the number of parallel connections of the PMOS 42 and the NMOS 44 respectively, so as to adjust the parallel resistance values of the PMOS 42 and the NMOS 44 respectively, thereby adjusting the driving current output by the data signal pin 20.

In addition, the reference voltage can also be designed as a programmable reference voltage, that is, if one end of the die termination resistor 10 is not grounded or process drift occurs, the user can change the reference voltage value to complete correct output current correction.

相对的，NMOS 44到晶粒终端电阻10的线路中，NMOS 42接地而晶粒终端电阻10连接1/2Vdd，所以参考电压设为1/4Vdd。Please refer to FIG. 4 , which is a schematic diagram of a third embodiment of the present invention. In the above-mentioned second embodiment, one end of the die termination resistor 10 is grounded, so the reference voltage is set to 1/2 of the working voltage. In practical applications, one end of the die terminating resistor 10 is mostly connected to 1/2 of the operating voltage, so the third embodiment illustrates the situation where one end of the die terminating resistor 10 is connected to 1/2 of the operating voltage. In the third embodiment, in the line from PMOS 42 to die termination resistor 10, PMOS 42 is connected to Vdd and die termination resistor 10 is connected to 1/2Vdd, so the reference voltage is set to

In contrast, in the line from the NMOS 44 to the die termination resistor 10 , the NMOS 42 is grounded and the die termination resistor 10 is connected to 1/2Vdd, so the reference voltage is set to 1/4Vdd.

As shown in FIG. 3 , the third embodiment has two comparators, namely a PMOS comparator 361 and an NMOS comparator 362 . At the same time, it also has two logic control circuits, namely a logic control circuit 381 for PMOS and a logic control circuit 382 for NMOS. Wherein, the reference voltage received by the PMOS comparator 361 is 3/4 of the working voltage, and the PMOS logic control circuit 381 is responsible for adjusting the parallel resistance value of the PMOS 42, thereby adjusting the driving current in the charging state. The reference voltage received by the NMOS comparator 362 is 1/4 of the operating voltage, and the NMOS logic control circuit 382 is responsible for adjusting the parallel resistance of the NMOS 44 , thereby adjusting the driving current in the discharge state.

Please refer to FIG. 4 , an embodiment of the flowchart of the current adjustment method of the present invention is applicable to a first chip, and includes the following steps.

Step S10 : outputting a driving current according to the control signal, wherein the driving current flows to a reference resistor in the second chip to generate an output voltage. Here, the first chip may be a control chip, and the second chip may be a memory chip or a dynamic random access memory (DRAM).

Wherein, according to an embodiment of the present invention, the reference resistor is an on-chip termination resistor (ODT), which is set in a memory chip, so there is no need to add an additional external resistor. And the driving current flows through the data signal pin (Data Pin) or the clock signal pin (Clock Pin) of the memory chip.

Step S20: Detect the output voltage and the reference voltage to generate a control signal, and the control signal controls the number of NMOS transistors or PMOS transistors connected in parallel to adjust the amount of the driving current. Wherein, the reference voltage is a programmable reference voltage. Alternatively, the above-mentioned first chip has an operating voltage, and the reference voltage is substantially equal to 1/2 of the operating voltage.

The above step S20 may further include the following steps: comparing the output voltage with the reference voltage to output a logic value; and generating the control signal according to the logic value.

Although the technical content of the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and any modifications and modifications made by those skilled in the art without departing from the spirit of the present invention should be included in the present invention. Within the scope of the present invention, therefore, the scope of protection of the present invention should be defined by the scope of the appended claims.

Claims (18)

1. A current regulating device, disposed in a first chip, the current regulating device comprising: a driving circuit for outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in a second chip to generate an output voltage; and a detection circuit, coupled to the drive circuit, for detecting the output voltage and a reference voltage to generate the control signal; Wherein, the control signal controls a parallel connection number of NMOS transistors or PMOS transistors in the driving circuit, so as to adjust the current amount of the driving current. 2. The current regulating device as claimed in claim 1, wherein the detection circuit comprises: a comparator for comparing the output voltage with the reference voltage to output a logic value; and A logic control circuit, coupled to the comparator, is used to generate the control signal according to the logic value. 3. The current regulating device as claimed in claim 2, wherein the logic control circuit is a finite state machine. 4. The current regulating device as claimed in claim 1, wherein the first chip has a calibration mode and an operation mode; when the first chip operates in the calibration mode, the current regulating device is enabled; and when the When the first chip operates in the working mode, the current regulating device is disabled. 5. The current regulating device as claimed in claim 1, wherein the reference voltage is a programmable reference voltage. 6. The current regulating device as claimed in claim 1, wherein the first chip is a control chip, and the second chip is a memory chip. 7. The current adjusting device as claimed in claim 6, wherein the driving current flows through a data signal pin or a clock signal pin of the memory chip. 8. The current regulating device as claimed in claim 1, wherein the reference resistor is a die termination resistor. 9. The current regulating device as claimed in claim 1, wherein the driving circuit operates at an operating voltage, and the reference voltage is substantially equal to the 1/2 operating voltage. 10. The current regulating device as claimed in claim 1, wherein the second chip is a dynamic random access memory chip. 11. A current adjustment method, suitable for a first chip, the current adjustment method comprising: outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in a second chip to generate an output voltage; and detecting the output voltage and a reference voltage to generate the control signal; Wherein, the control signal controls a parallel connection number of NMOS transistors or PMOS transistors to adjust the current amount of the driving current. 12. The current adjustment method as claimed in claim 11, wherein the detecting step further comprises: comparing the output voltage with the reference voltage to output a logic value; and The control signal is generated according to the logic value. 13. The current adjusting method as claimed in claim 11, wherein the reference voltage is a programmable reference voltage. 14. The current regulating method as claimed in claim 11, wherein the first chip is a control chip, and the second chip is a memory chip. 15. The current adjusting method as claimed in claim 14, wherein the driving current flows through a data signal pin or a clock signal pin of the memory chip. 16. The current regulation method as claimed in claim 11, wherein the reference resistor is a die termination resistor. 17. The current regulating method as claimed in claim 11, wherein the first chip has an operating voltage, and the reference voltage is substantially equal to the 1/2 operating voltage. 18. The current regulating method as claimed in claim 1, wherein the second chip is a dynamic random access memory chip.

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