CN101470170B - JTAG link test method and apparatus - Google Patents

Abstract

The invention provides a JTAG link testing method and its device. Described JTAG link testing method comprises putting one group of all 1 instruction codes to JTAG link; According to described all 1 instruction codes, select 1 shift data register to be connected on each device under test, and described shift data The register captures the state of each device under test; the test vector containing the signature is placed in the shift data register through the JTAG link; the state and test of the device under test captured by each shift data register output by the shift data register The feature code in the vector; according to the state and the feature code of the device under test output by the shift data register, it is judged whether the JTAG link is normal. Through the technical solution provided by the embodiment of the present invention, the test of the JTAG link can be realized simply and conveniently.

Description

JTAG link testing method and device thereof

technical field

The invention relates to the field of electronic technology, in particular to a JTAG link testing method and a device thereof.

Background technique

In order to solve the test problem of VLSI, the Boundary Scan technology was proposed by the Joint Test Action Group (JETAG, JointTest Action Group), which uses the Boundary Scan Cell (BSC, BSC) between the device input and output pins and the core circuit Boundary Scan Description) tests the device and its peripheral circuits, thereby improving the controllability and observability of the device, solving the above-mentioned testing problems brought about by the development of modern electronic technology, and can more conveniently complete the circuit assembled by modern devices board testing. Often this test is called a JTAG link test.

The JTAG link test provided by the prior art is generally based on the fact that the JTAG link of the single board has been determined, and then one or more sets of test vectors corresponding to the JTAG link are used for testing. During the JTAG link test process, input a specific test vector from the input end of the BSC, then observe the test result output by the output end of the BSC, and judge whether the JTAG link is normal according to the test result.

Therefore, in the process of carrying out the invention of the present invention, the inventor has found that there are at least the following problems in the prior art: in the technical solution provided by the prior art, for testing different JTAG links, different test vectors need to be input, so the prior art The provided JTAG link test method is not universal and inconvenient to use.

Contents of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a JTAG link testing method and device thereof, which can avoid the need to input different test vectors for testing different JTAG links.

In order to solve the above technical problems, the purpose of the embodiments of the present invention is achieved through the following technical solutions:

The embodiment of the present invention provides a kind of JTAG link testing method, it comprises:

Putting a group of all 1 instruction codes into the JTAG link, the length of the all 1 instruction codes is greater than or equal to the quantity of the device to be tested;

According to the all-1 instruction code, the JTAG link selects a 1-bit shift data register to be connected to each device under test of the JTAG link, and the shift data register captures the state of each device under test;

The test vector that will comprise feature code is placed in described shift data register by JTAG link, and the length of described test vector is greater than the quantity of device to be tested;

The state of the device under test captured by each shift data register output by the shift data register and the signature code in the test vector;

Judging whether the JTAG link is normal according to the state and the feature code of the device under test output by the shift data register.

The embodiment of the present invention also provides a kind of JTAG link testing device, it comprises:

The input unit is used to insert a group of all-1 instruction codes into the device to be tested, the length of the all-1 instruction code is greater than or equal to the number of devices to be tested, and insert a test vector containing a feature code, said The length of the test vector is greater than the number of devices to be tested;

The instruction register is used to select a 1-bit shift data register to be connected to each device under test according to the all-1 instruction code inserted by the input unit;

The shift data register is used to output the state of the device under test captured by each shift data register and the feature code in the test vector according to the test vector placed by the input unit;

The judging unit is used for judging whether the JTAG link is normal according to the state and the feature code of the device under test output by the shift data register.

The embodiment of the present invention also provides a communication device, including a JTAG link testing device, for testing a JTAG link composed of devices under test, including:

The input unit is used to insert a group of all-1 instruction codes, the length of the all-1 instruction codes is greater than or equal to the number of devices to be tested, and inserts a test vector that includes a feature code, the length of the test vector is greater than the number of devices under test;

The instruction register is used to select a 1-bit shift data register to be connected to each device under test according to the all-1 instruction code inserted by the input unit;

The shift data register is used to output the state of the device under test captured by each shift data register and the feature code in the test vector according to the test vector placed by the input unit;

The judging unit is used for judging whether the JTAG link is normal according to the state and the feature code of the device under test output by the shift data register.

Through the JTAG link testing method and device thereof provided by the embodiments of the present invention, the state of each device under test is captured by the shift data register, and when the shift data register inputs the test vector containing the feature code, the state and the state of the device under test are output. The feature code in the test vector, so according to the output status and feature code of the device under test, it can be judged whether the JTAG link is normal, and the same test vector can be input for different JTAG links, which can realize the JTAG link simply and conveniently. road test.

Description of drawings

Fig. 1 is the flowchart of an embodiment of JTAG link test method of the present invention;

FIG. 2 is a structural diagram of an embodiment of a JTAG link testing device of the present invention.

Detailed ways

Embodiments of the present invention provide a JTAG link testing method and device thereof. In order to make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

Please refer to FIG. 1 , which is a flow chart of the first embodiment of the JTAG link testing method of the present invention. In this embodiment, it is assumed that there are three devices to be tested connected to the JTAG link.

The specific process of JTAG link test includes:

Step 101: inserting a group of all-1 instruction codes into the JTAG link, the length of the all-1 instruction codes is greater than or equal to the number of devices to be tested;

The devices to be tested are connected in series through the JTAG interface to form a JTAG link. Wherein, each device to be tested is connected to a corresponding JTAG interface, and each JTAG interface includes four input interfaces and one output interface. Among them, the four input interfaces are: test data input (TDI, TestDate Input), test clock input (TCK, Test Clock Input), test mode selection (TMS, TestMode Selection Input), test reset (TRST Test Reset Input), The output interface is test data output (TDO, Test Date Output). Data is input to the JTAG interface through the TDI pin; data is output from the JTAG interface through the TDO pin; TMS is used to set the JTAG interface in a specific test mode; TRST is used for test reset, active low.

Therefore, input a set of all 1 instruction codes to the TDI pin in the JTAG link. For all devices, the all-ones instruction code is the BYPASS instruction. The instruction code of all 1s needs to contain enough bits to ensure that the instruction registers between the devices under test on the JTAG link can be moved into instructions of 1 bit, so the length of the instruction code of all 1s be greater than or equal to the number of devices to be tested.

Step 102: According to the all-1 instruction code, select a 1-bit shift data register connected between TDI and TDO of each JTAG interface in the JTAG link, and the selected shift data register captures each waiting The status of the test device;

A boundary-scan register unit is connected between the input and output pins of the device to be tested. Generally, the boundary-scan register unit includes a data register and an instruction register. The instruction register is used to control the data register, and the data register is used to observe and control the input and output of the chip. For the input pin of the device under test, data can be loaded into the input pin through the data register connected to it; for the output pin of the device under test, the data can also be captured (Capture) through the data register connected to it The output signal on the output pin.

In this embodiment, the shift data register with 1 bit can be selected through the BYPASS instruction, so by placing a group of sufficiently long all-1 instruction codes into the JTAG link, it is equivalent to selecting a 1-bit shift data register, and connecting Between TDI and TDO of each JTAG interface in the JTAG link. The state captured by the 1-bit shift data register during data shifting is 0 bit.

Step 103: inserting a test vector that includes a feature code into the shift data register through the JTAG link, the length of the test vector is greater than the number of devices to be tested;

The feature code may contain any one or more bits that are not all 0s. If the number of bits contained in the signature code is greater than the number of devices to be tested, the test vector can only contain the signature code or other bits; if the number of bits included in the signature code is less than the number of devices to be tested, it can be tested Additional bits are added to the vector until the length of the test vector is greater than the number of devices under test. The test vectors are arranged in a right-shift manner. For example, in this embodiment, there are three devices to be tested, and assuming that the feature code is 0101, the test vectors input to the JTAG link can be ... 1110101, ... 0000101 and so on.

The test vectors are input into the JTAG link bit by bit through the TDI interface serially under the drive of the TCK, that is to say, each clock cycle of the TCK inputs a bit in the test vector to the TDI interface. Since a 1-bit shift data register is connected between TDI and TDO of each JTAG interface, the test vector will eventually be input into the shift data register through the TDI interface under the control of TCK. The states and feature codes of the device under test captured by the shift data register will also be serially output bit by bit by the TDO interface.

Step 104: the shift data register outputs the test result, and the test result includes the state of the DUT captured by each shift data register and the signature in the test vector;

The following example specifically describes the process of JTAG link test vector input and test data output:

In this embodiment, there are three devices to be tested connected to the JTAG link, and it is assumed that the test vectors set into the JTAG link are ... 1110101, where 0101 is a feature code.

After the instruction of all 1s is input to the JTAG link, the state captured by the shift register from each device under test is 0.

When the trigger edge of the first clock cycle of TCK arrives, the first bit 1 of the test vector is input into the shift data register corresponding to the first device under test through the TDI interface, and at the same time, the shift data register corresponding to the third device under test The 0 in the bit data register outputs the JTAG link from the TDO interface, so in the first clock cycle of TCK, the bit output from the JTAG link is 0;

When the trigger edge of the second clock cycle of TCK arrives, the second bit 0 of the test vector is input into the shift data register corresponding to the first device under test through the TDI interface. 1 is shifted into the shift data register corresponding to the second device under test, and the 0 originally stored in the second device under test is shifted into the shift data register corresponding to the second device under test. The 0 in the shift data register corresponding to the three devices under test outputs the JTAG link from the TDO interface, so in the second clock cycle of TCK, the bit output from the JTAG link is 0;

When the trigger edge of the third clock cycle of TCK arrives, the third bit 1 of the test vector is input into the shift data register corresponding to the first device under test through the TDI interface. 0 is shifted into the shift data register corresponding to the second device under test, and the 1 originally stored in the second device under test is shifted into the shift data register corresponding to the third device under test. The 0 in the shift data register corresponding to the three devices under test outputs the JTAG link from the TDO interface, so in the third clock cycle of TCK, the bit output from the JTAG link is 0;

When the trigger edge of the fourth clock cycle of TCK arrives, the fourth bit 0 of the test vector is input into the shift data register corresponding to the first device under test through the TDI interface. 1 is shifted into the shift data register corresponding to the second device under test, and the 0 originally stored in the second device under test is shifted into the shift data register corresponding to the third device under test. 1 in the shift data register corresponding to the three devices under test outputs the JTAG link from the TDO interface, so in the third clock cycle of TCK, the bit output from the JTAG link is 1;

By analogy, after 7 TCK cycles, the bits output from the JTAG link are 0101000 in turn.

Step 105: Determine whether the JTAG link is normal according to the status and feature code of the DUT output by the shift data register.

For example, the output test result contains a complete feature code, and is offset by three 0s, and the number of devices under test on the link is 3, so it can be judged that the devices under test are all normal.

Please refer to FIG. 2 , which is a structural diagram of an embodiment of a JTAG link testing device of the present invention. The JTAG link testing device includes an input unit 21 , an instruction register 22 , a shift data register 23 , a test clock input unit 24 , and a judging unit 25 .

The input unit 21 is used to insert a group of all-1 instruction codes into the device to be tested, the length of the all-1 instruction code is greater than or equal to the number of devices to be tested, and insert a test vector containing a feature code , the length of the test vector is greater than the number of devices to be tested.

The feature code may contain any one or more bits that are not all 0s. If the number of bits contained in the signature code is greater than the number of devices to be tested, the test vector can only contain the signature code or other bits; if the number of bits included in the signature code is less than the number of devices to be tested, it can be tested Additional bits are added to the vector until the length of the test vector is greater than the number of devices under test.

The selection unit 22 is configured to select a 1-bit shift data register to be connected to each device under test according to the all-ones instruction code received by the receiving unit 21 .

For all devices, the all-ones instruction code is the BYPASS instruction. The shift data register with 1 bit can be selected through the BYPASS instruction, so by placing a group of sufficiently long all-1 instruction codes into the JTAG test device, it is equivalent to selecting a 1-bit shift data register and connecting it to the JTAG test device .

The shift data register 23 is used to output the state of the DUT captured by each shift data register and the feature code in the test vector according to the test vector placed by the input unit.

The test clock unit 24 is used to generate a test clock; the input unit 21 is specifically the first input unit, which is used to insert a group of all 1 instruction codes, and the length of the all 1 instruction codes is greater than or equal to the length to be tested The quantity of the device, and put into the test vector that comprises feature code, the length of described test vector is greater than the quantity of the device to be tested, and according to described test clock, input in the described test vector to described shift data register 23 successively bits, the shift data register 23 is specifically a first shift data register, and is used to sequentially output the state and signature of the device under test as test results according to the test clock.

After the instruction of all 1s is input to the JTAG link, the state captured by the shift register from each device under test is 0.

The judging unit 25 is used for judging whether the JTAG link is normal according to the state and the feature code of the DUT output by the shift data register.

In addition, an embodiment of the present invention also provides a communication device, including a JTAG link testing device, used for testing a JTAG link composed of devices under test.

Described JTAG link testing device comprises:

The input unit is used to insert a group of all-1 instruction codes, the length of the all-1 instruction codes is greater than or equal to the number of devices to be tested, and inserts a test vector that includes a feature code, the length of the test vector is greater than the number of devices under test;

The instruction register is used to select a 1-bit shift data register to be connected to each device under test according to the all-1 instruction code inserted in the input unit;

The shift data register is used to capture the state of the device under test of each shift data register and the signature in the test vector;

The judging unit is used for judging whether the JTAG link is normal according to the state and feature code of the device under test captured by the shift data register.

Described JTAG link testing device can also further comprise:

a test clock unit, configured to generate a test clock;

The input unit is specifically a first receiving unit, which is used to insert a set of all-1 instruction codes, the length of the all-1 instruction codes is greater than or equal to the number of devices to be tested, and inserts a test vector containing a feature code , the length of the test vector is greater than the number of devices to be tested, and according to the test clock generated by the test clock unit, sequentially input the bits in the test vector to the shift data register,

The shift data register is specifically a first shift data register, which is further used to sequentially output the states and feature codes of the device under test according to the test clock.

Through the JTAG link testing method and device thereof provided by the embodiments of the present invention, the state of each device under test is captured by the shift data register, and when the shift data register inputs the test vector containing the feature code, the state and the state of the device under test are output. The feature code in the test vector, so according to the output status and feature code of the device under test, it can be judged whether the JTAG link is normal, and the same test vector can be input for different JTAG links, which can realize the JTAG link simply and conveniently. road test.

A kind of JTAG link test method and its device provided by the present invention have been introduced in detail above, applied specific example in this paper and explained the principle and implementation mode of the present invention, and the description of the above embodiment is only used to help understand the present invention The technical solution disclosed by the invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be understood as Limitations on the Invention.

Claims (4)

1. a JTAG JTAG link test method is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:

Insert one group of complete 1 order code to the JTAG link, the length of described complete 1 order code is more than or equal to the quantity of tested device;

According to described complete 1 order code, JTAG link selection 1 bit shift data register is connected on each device under test of JTAG link, and the state of described each device under test of shifted data registers capture;

According to test clock, the bit that will comprise in the test vector of condition code is imported in each shifted data register successively by the JTAG link, and the length of described test vector is greater than the quantity of tested device;

According to test clock, export the state of the device under test of catching in each shifted data register and the condition code in the test vector successively;

According to the state and the condition code of the device under test of described shifted data register output, judge whether the JTAG link is normal.

2. JTAG link test method according to claim 1 is characterized in that, described condition code is to comprise one or more bits of non-complete 0 arbitrarily.

3. a JTAG JTAG link test device is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:

The test clock unit is used to produce test clock;

Input block, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and the test clock that produces according to described test clock unit, import bit in the described test vector successively to the shifted data register;

Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;

The shifted data register is used for the test vector of inserting according to input block, according to described test clock, exports the state of device under test of each shifted data registers capture and the condition code in the test vector successively;

Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.

4. a communication facilities comprises JTAG link test device, is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:

The test clock unit is used to produce test clock;

Input block, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and the test clock that produces according to described test clock unit, import bit in the described test vector successively to the shifted data register;

Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;

The shifted data register is used for the test vector of inserting according to input block, according to described test clock, exports the state of device under test of each shifted data registers capture and the condition code in the test vector successively;

Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.

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