CN101465277A - Method and system for setting silicon wafer shallow ditch isolated etching time - Google Patents
Method and system for setting silicon wafer shallow ditch isolated etching time Download PDFInfo
- Publication number
- CN101465277A CN101465277A CNA2007103006635A CN200710300663A CN101465277A CN 101465277 A CN101465277 A CN 101465277A CN A2007103006635 A CNA2007103006635 A CN A2007103006635A CN 200710300663 A CN200710300663 A CN 200710300663A CN 101465277 A CN101465277 A CN 101465277A
- Authority
- CN
- China
- Prior art keywords
- etching
- etched
- etching period
- parameter
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 173
- 238000000034 method Methods 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
- 238000004364 calculation method Methods 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 9
- 238000012937 correction Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005259 measurement Methods 0.000 description 5
- 230000003203 everyday effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Images
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a wafer shallow isolated etching time setting method and a system thereof; the method obtains the time correction parameters based on the etched error rate and corrects the etching time of the nearest etching according to the time correction parameters to obtain the etching time of the current etching. Compared with the prior art, the invention can obtain the error parameters based on the etching errors of the past etchings or several etchings thereinto and then correct the etching time of the nearest etching according to the error parameters, so as to reduce the error rate in mass production and also maximumly reduce the error rate when the etching ability is drifted in mass production.
Description
Technical field
The present invention relates to a kind of wafer shallow and isolate the method and system that the etching period of (Shallow Trench Isolation is hereinafter to be referred as STI) is set.
Background technology
For integrated circuit (Integrated Circuit, hereinafter to be referred as IC) product, the IC product of 0.16 processing procedure particularly, its shallow-trench isolation (Shallow Trench Isolation is hereinafter to be referred as STI) step height (Step height) has very strong getting in touch with the electrical property of product.Therefore, in the process of making IC, need when carrying out the STI etching, strictness control this parameter.
Wafer STI etch depth is determined by etching period.In order accurately to control the STI etch depth, must the accurate control etched time of STI.Must adjust according to the measurement of actual etching value for etched time set.
First kind of mode is early stage STI engraving method, artificially sets etching period by experience, exists the very big risk of falsely dropping like this.In case the wrong STI degree of depth mistake that will cause product of choosing, thereby make product rejection.
Second method is that the actual survey machine result by every day sets the etched time of STI.If but there are many batches of products to carry out the STI etching continuously like this, in case the survey machine result on the same day is inaccurate, continuous scrapping will appear.
The third method is the product STI etching of carrying out small batch every day earlier, and waits for the follow-up degree of depth measurement of these products, if measurement normally carries out follow-up large-scale STI etching again.Though this method can influence operating efficiency, the inferior rate of reduction that can be to a certain degree.But owing to there is inevitable etch capabilities drift when continuous etching, inevitably still can produce deviation when etching continuously in enormous quantities, inferior rate is still very high.
Summary of the invention
At above-mentioned defective of the prior art and problem, the objective of the invention is to propose the method and system that etching period that a kind of wafer shallow isolates is set, in large-scale production constantly according to the error rate correction etching period of etched wafer, and not needing can realize artificial participation, reduce the defect ware rate to greatest extent in the etching continuously in enormous quantities.
In order to achieve the above object, the present invention proposes a kind of method of etching period setting of wafer shallow isolation, comprising:
Step 1, judge whether to be the etching first time, if then step finishes; Otherwise enter step 2;
Step 2, the etched actual depth of basis, predetermined etch depth and etching period are revised this etching period.
Preferred as technique scheme, described step 2 is specially:
Step 21, the etched actual depth of basis, predetermined etch depth calculate etched error amount;
Step 22, obtain the time corrected parameter, and, obtain this etched etching period according to the most approaching once etched etching period of time corrected parameter adjustment according to etched error amount.
Preferred as technique scheme, described step 22 is specially:
Step 221, multiply by its corresponding preset weight, obtain each etching error parameter, and calculate the overall error parameter according to each etching error parameter with each error amount;
Step 222, according to overall error parameter and the most approaching once etched etching period, calculate this etched etching period.
Wherein step 222 is specially:
Step 222, overall error parameter obtain the time corrected parameter divided by predefined parameter, and with a preceding etching period and described time corrected parameter summation, as this etched etching period.
Simultaneously, the invention allows for a kind of said method that uses and carry out the system that etching period is set, comprising:
Storage device, described storage device are used for etched actual depth of storage and etching period;
The etching period calculation element, this module draws this etched etching period according to etched actual grade, desired depth and etching period.
Preferred as technique scheme, the described etching period calculation element that carries out in the system that etching period sets comprises:
Etching error parameter computing module, this module calculates the etching error according to etched actual grade and desired depth, and each moment error be multiply by its corresponding preset weight, calculates etched etching error parameter;
Total etching error parameter computing module, this module calculates total etching error parameter according to the result of calculation of described etching error parameter computing module;
Time corrected Calculation module, total etching error parameter that this module obtains according to described total etching error parameter computing module, and the most approaching once etched etching period calculate this etched etching period.
Preferred as technique scheme, described time corrected Calculation module of carrying out in the system that etching period sets obtains the time corrected parameter with described overall error parameter divided by predefined parameter, and with a preceding etching period and described time corrected parameter summation, as this etched etching period.
Preferred as technique scheme, describedly carry out the system that etching period sets and also comprise:
Interface module, described interface module provides interface, makes describedly to carry out system that etching period sets and can be connected etching machines, and the etching period of described error parameter computing module calculating is sent to described etching machines.
The present invention proposes a kind of method and system of etching period setting of wafer shallow isolation, draw the time corrected parameter according to etched error rate, and immediate once etched etching period is revised to draw this etched etching period by the time corrected parameter.The present invention's prior art of comparing, can according in the past repeatedly the etched etching error of etching or several wherein obtain error parameter, and come etched etching period of the last time is revised with this error parameter, error rate when being reduced in mass production, and can reduce etch capabilities to greatest extent and drift in the error rate that causes when producing in batches.
Description of drawings
The method preferred embodiment schematic flow sheet that Fig. 1 sets for the etching period that the wafer shallow that the present invention proposes is isolated;
The use said method that Fig. 2 proposes for the present invention carries out the structural representation of the system of etching period setting.
Embodiment
The present invention will be further described below in conjunction with accompanying drawing.
The monitoring method idiographic flow of the e-mail passageway that the present invention proposes comprises as shown in Figure 1:
Step a, judge whether to be the etching first time, if then step finishes; Otherwise enter step 2;
Step b, read existing etching record,, calculate each etched error amount according to each etched actual grade and desired depth before this; Error amount is (depth
n-target), depth wherein
nThe n time etched actual grade, target are desired depth;
Step c, set a weight for each etching last time; Be specifically as follows: suppose that the last time is etched to the n time etching, then last etched weight is C
2, and C
2Be set to 0.8; And the 1st etched weight of n-1, n-2...... is C
1, and C
1Be set to 0.2;
Steps d, multiply by its weight, obtain each etching error parameter, and calculate the overall error parameter according to each etching error parameter with each etched error; Being specifically as follows for the first time, etched error parameter is (depth
1-target) * C
1Etched error parameter is (depth for the second time
2-target) * C
1... the n-1 time etched error parameter is (depth
N-1-target) * C
1The n time etched error parameter is (depth
n-target) * C
2Because immediate once etched error is more important for revising etching period, thus in the present embodiment with once immediate, the n time etching just gives higher weight, and the 1st time to the n-1 time etching before this gives lower weight; Certainly, can according to actual conditions revise weighted value with, or each etched weight all gives different weighted values, this is that those skilled in that art are understandable, does not give unnecessary details one by one at this;
Step e, with all error parameter sums as the overall error parameter; It is the overall error parameter X
n={ [(depth
1-target)+(depth
2-target) ...+(depth
N-2-target)+(depth
n-1-target)] * C
1+ (| depthn-target|) * C
2* C
3Error during wherein recent etching is to get its absolute value; C
3Then be the overall error weight, whether C is set
3And C
3Actual value set in can using according to reality, present embodiment just illustrates;
Step f, according to overall error parameter and preceding once etched etching period, calculate this etched etching period; Be specifically as follows: with the overall error parameter divided by predefined parameter as the time corrected parameter, and a preceding etching period deducted described time corrected parameter, as this etched etching period; Be this etched time t
N+1=t
n-X
n/ J, wherein t
nBe immediate once etched etching period, J is predefined parameter, and the J value is 50 in the present embodiment.
Certainly, originally be in the example, C
1, C
2, C
3, J value be adjustable.Etched each time weight (C of while
1, C
2) also can be used for setting according to actual making, give weight C for the 1st to the n-1 time etching error in the present embodiment
1, and the absolute value of immediate the n time etched error gives weight C
2Just illustrate.While C
3, J setting also be so, whether be provided with and concrete value, can decide according to actual conditions.
In order to improve accuracy, in step b, the etching each time before this etching is write down all as parameter correction etching period in the present embodiment.Those skilled in that art can understand, also can be only from wherein several write down as parameter correction etching period, the etched error parameter of the pre-determined number that for example advances recently corrected parameter computing time, or according to the etched error parameter of pre-determined number corrected parameter computing time of error maximum.
The invention allows for a kind of said method of using and carry out the system that etching period is set, its preferred embodiment comprises as shown in Figure 2:
Storage device, described storage device are used for etched actual depth of storage and etching period; This storage device can be specially a stored data base;
The etching period calculation element, this module draws this etched etching period according to etched actual grade, desired depth and etching period; This etching period calculation element can be specially a control system that is connected with storage device, is called STI high-order processing procedure control system (hereinafter to be referred as STI APC);
The system that interface module, interface module are set etching period connects etching machines, receives actual depth and etching period that etching machines is measured, and the etching period that described error parameter computing module is calculated sends to described etching machines; This interface module can be arranged on a module in the STI APC, can be the separate modular of a system also, is used to connect etching period calculation element and STI etching machine, STI measurement platform and ER measurement platform;
Wherein, the STI APC as the etching period calculation element comprises:
Etching error parameter computing module, this module calculates the etching error according to etched actual grade and desired depth; For example: error amount is (depth
n-target), depth wherein
nThe n time etched actual grade, target are desired depth; And to each constantly error multiply by its corresponding preset weight, calculate etched etching error parameter; For example: suppose that the last time is etched to the n time etching, then last etched weight is C
2, and C
2Be set to 0.8; And the 1st etched weight of n-1, n-2...... is C
1, and C
1Be set to 0.2;
Total etching error parameter computing module, this module calculates total etching error parameter according to the result of calculation of described etching error parameter computing module; The overall error parameter X
nAccount form can be specially: X
n={ [(depth
1-target)+(depth
2-target) ...+(depth
N-2-target)+(depth
N-1-target)]
*C
1+ (| depth
n-target|)
*C
2}
*C
3
Time corrected Calculation module, total etching error parameter that this module obtains according to described total etching error parameter computing module, and the most approaching once etched etching period calculate this etched etching period.
The method that a time total etching parameter of corrected parameter basis and an immediate etching period are calculated this etching period has multiple, for example: the overall error parameter is tried to achieve time corrected Calculation module divided by predefined parameter will obtain the time corrected parameter, and with a preceding etching period and described time corrected parameter summation, as this etched etching period.That is: t
N+1=t
n-X
n/ J, wherein t
N+1Be this etched etching period, t
nBe preceding once etched etching period, X
nBe the overall error parameter, J is a predefined parameter, and the value of J can be 50., wherein
Certainly, originally be in the example, C
1, C
2, C
3, J value be adjustable.Etched each time weight (C of while
1, C
2) also can be used for setting according to actual making, give weight C for the 1st to the n-1 time etching error in the present embodiment
1, and the absolute value of immediate the n time etched error gives weight C
2Just illustrate.While C
3, J setting also be so, whether be provided with and concrete value, can decide according to actual conditions.
In order to improve accuracy, the etching each time before this etching is write down all as parameter correction etching period in the present embodiment.Those skilled in that art can understand, also can be only from wherein several write down as parameter correction etching period, the etched error parameter of the pre-determined number that for example advances recently corrected parameter computing time, or according to the etched error parameter of pre-determined number corrected parameter computing time of error maximum.
Certainly, adopt above-mentioned optimal technical scheme just for the ease of understanding to illustrating that the present invention carries out, the present invention also can have other embodiment, protection scope of the present invention is not limited to this.Under the situation that does not deviate from spirit of the present invention and essence thereof, the person of ordinary skill in the field works as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (8)
1, a kind of method of etching period setting of wafer shallow isolation comprises:
Step 1, judge whether to be the etching first time, if then step finishes; Otherwise enter step 2;
Step 2, the etched actual depth of basis, predetermined etch depth and etching period are revised this etching period.
2, the method for the etching period setting of wafer shallow isolation according to claim 1 is characterized in that described step 2 is specially:
Step 21, the etched actual depth of basis, predetermined etch depth calculate etched error amount;
Step 22, obtain the time corrected parameter, and, obtain this etched etching period according to the most approaching once etched etching period of time corrected parameter adjustment according to etched error amount.
3, the method for the etching period setting of wafer shallow isolation according to claim 2 is characterized in that described step 22 is specially:
Step 221, multiply by its corresponding preset weight, obtain each etching error parameter, and calculate the overall error parameter according to each etching error parameter with each error amount;
Step 222, according to overall error parameter and the most approaching once etched etching period, calculate this etched etching period.
4, the method for the etching period setting of wafer shallow isolation according to claim 3 is characterized in that step 222 is specially:
Step 222, overall error parameter obtain the time corrected parameter divided by predefined parameter, and with a preceding etching period and described time corrected parameter summation, as this etched etching period.
5, a kind of said method that uses carries out the system that etching period is set, and comprising:
Storage device, described storage device are used for etched actual depth of storage and etching period;
The etching period calculation element, this module draws this etched etching period according to etched actual grade, desired depth and etching period.
6, according to claim 5ly carry out the system that etching period is set, it is characterized in that, the described etching period calculation element that carries out in the system that etching period sets comprises:
Etching error parameter computing module, this module calculates the etching error according to etched actual grade and desired depth, and each etching error be multiply by its corresponding preset weight, calculates etched etching error parameter;
Total etching error parameter computing module, this module calculates total etching error parameter according to the result of calculation of described etching error parameter computing module;
Time corrected Calculation module, total etching error parameter that this module obtains according to described total etching error parameter computing module, and the most approaching once etched etching period calculate this etched etching period.
7, the system that carries out the etching period setting according to claim 6, it is characterized in that, described time corrected Calculation module of carrying out in the system that etching period sets obtains the time corrected parameter with described overall error parameter divided by predefined parameter, and with a preceding etching period and described time corrected parameter summation, as this etched etching period.
8, the system that carries out the etching period setting according to claim 5 is characterized in that, the described system that carries out the etching period setting also comprises:
Interface module, described interface module provides interface, makes describedly to carry out system that etching period sets and can be connected etching machines, and the etching period of described error parameter computing module calculating is sent to described etching machines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007103006635A CN101465277A (en) | 2007-12-19 | 2007-12-19 | Method and system for setting silicon wafer shallow ditch isolated etching time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007103006635A CN101465277A (en) | 2007-12-19 | 2007-12-19 | Method and system for setting silicon wafer shallow ditch isolated etching time |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101465277A true CN101465277A (en) | 2009-06-24 |
Family
ID=40805779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007103006635A Pending CN101465277A (en) | 2007-12-19 | 2007-12-19 | Method and system for setting silicon wafer shallow ditch isolated etching time |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101465277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063063A (en) * | 2009-11-11 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor manufacturing method and system |
| CN107316821A (en) * | 2016-04-27 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of depth Detection of Stability method |
-
2007
- 2007-12-19 CN CNA2007103006635A patent/CN101465277A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063063A (en) * | 2009-11-11 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor manufacturing method and system |
| US8239056B2 (en) | 2009-11-11 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced process control for new tapeout product |
| CN102063063B (en) * | 2009-11-11 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Semiconductor manufacturing method and system |
| CN107316821A (en) * | 2016-04-27 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of depth Detection of Stability method |
| CN107316821B (en) * | 2016-04-27 | 2021-03-12 | 中芯国际集成电路制造(上海)有限公司 | Depth stability detection method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6368884B1 (en) | Die-based in-fab process monitoring and analysis system for semiconductor processing | |
| JP3957964B2 (en) | Lot dispatching method and lot dispatching system | |
| CN110928264B (en) | Data processing, data processing apparatus, and computer-readable recording medium | |
| KR20020087047A (en) | Method for determining optimal process targets in microelectronic fabrication | |
| CN103885423A (en) | Statistical process control system and method for wafer acceptance test | |
| CN118131718B (en) | Automatic control system for chip manufacturing production line | |
| CN104465368B (en) | A kind of contact hole etching device and lithographic method | |
| CN113376969A (en) | Overlay error compensation method, exposure system, server and readable storage medium | |
| CN101465277A (en) | Method and system for setting silicon wafer shallow ditch isolated etching time | |
| CN110928265B (en) | Data processing method, device and system, and computer readable recording medium | |
| CN109560025A (en) | Acid tank formula wet-etching technology | |
| US7171641B2 (en) | Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system | |
| CN103869795A (en) | SPC strategy establishing method | |
| US6376261B1 (en) | Method for varying nitride strip makeup process based on field oxide loss and defect count | |
| CN104701211B (en) | Inspect the method for measurement of frequency by random samples according to integrated circuit manufacture process Capability index adjust automatically | |
| CN103199046B (en) | Wafer notch edge center prealignment method | |
| CN100549680C (en) | Be used to produce the method and system of solar cell | |
| US8406904B2 (en) | Two-dimensional multi-products multi-tools advanced process control | |
| CN114415594B (en) | Tool life management system and method | |
| CN102800564B (en) | Method and system for avoiding error in semiconductor process menu debugging process | |
| US10691028B2 (en) | Overlay variance stabilization methods and systems | |
| CN104103544A (en) | Wafer defect monitoring method | |
| CN103186052B (en) | Lithography parameter optimization method | |
| CN114783865B (en) | Scribing and cutting method and system | |
| CN115320106B (en) | Method for calibrating size of 3D printer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090624 |