CN101464912B - Transistor relative precision model method - Google Patents

Abstract

The invention discloses a model method for relative accuracy of a transistor, relative accuracy model parameter is extracted by measuring the current values at various bias points of Vds and Vgs of two adjacent transistors, summarizing dimensions of various transistors and the current differences thereof under various bias voltages, selecting appropriate model parameters, defining an accurate model parameter formula for description and adopting a certain model parameter extraction method, so that the model can reflect various dimensions and current difference of the adjacent transistors. The invention ensures that modeling is performed on various device dimensions and current standard deviation under various voltage bias conditions, thereby improving the work efficiency and the accuracy of the design of an analog integrated circuit.

Description

Transistor relative accuracy model method

Technical field

The present invention relates to a kind of semiconductor devices SPICE (Simulation Program withIntegrated Circuit Emphasis) model method, relate in particular to a kind of transistor relative accuracy model method.

Background technology

The method of existing relative accuracy provides the corresponding relation of electrical characteristics key parameter and characteristic quantity substantially, and key parameter comprises threshold voltage VTH and saturation current Idsat, and the deviser estimates according to measured data.

Also have a kind of method to be: the experimental data of this technology relative accuracy of test reflection, and sum up the standard deviation of difference Δ Idsat of standard deviation, saturation current of the difference Δ Vt of threshold voltage and the relation of device size.On the basis of common SPICE device model, wherein VTH0, TOX, U0 parameter are revised, set up corresponding relative accuracy model; In a relative accuracy model and common SPICE model generalization to a model file.

Existing adjacent transistor relative accuracy model generally provides the relative accuracy model of 2 of threshold voltage VTH and saturation current Idsat, the relative accuracy model of device under other bias condition can only estimate that this method can not satisfy the accuracy requirement of Analog Circuit Design.

Summary of the invention

Technical matters to be solved by this invention provides a kind of transistor relative accuracy model method, can carry out modelling to the current standard deviation under different components size, the different voltage bias condition, thereby improve the work efficiency and the accuracy of Analogous Integrated Electronic Circuits design.

For solving the problems of the technologies described above, the technical scheme of transistor relative accuracy model method of the present invention is to comprise the steps

Test different components size, comprise the width W of transistor channel and the length L of transistor channel, test the current value of adjacent transistor under the different bias condition, the data of different chip units on the test considerable wafer, and, count the 3sigma value of Δ Id according to the electric current difference DELTA Id of the paired chip of these data computation;

To VTH0, TOX, K1, U0, RDSW, LINT, seven model parameters of WINT are carried out modelling, wherein

Param＝Param_org+Δparam；

$\mathrm{\ΔVTH}0=\frac{A1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔTOX}=\frac{B1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔK}1=\frac{C1}{\sqrt{W\·L\·M}}+1;$

$\mathrm{\ΔU}0=\frac{D1}{\sqrt{W\·L\·M}}+1;$

$\mathrm{\ΔRDSW}=\frac{E1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔLINT}=\frac{F1}{\sqrt{W\·M}};$

$\mathrm{\ΔWINT}=\frac{G1}{\sqrt{L\·M}};$

Wherein Param is VTH0, TOX, K1, U0, RDSW, LINT, seven model parameters of WINT, Param_org is VTH0, TOX, K1, U0, RDSW, LINT, the value of seven model parameters of WINT in general models, Δ param is Δ VTH0, Δ TOX, Δ K1, Δ U0, Δ RDSW, Δ LINT, seven model parameters of Δ WINT, A1, B1, C1, D1, E1, F1, G1 is a undetermined coefficient, and M is the parallel transistor number, according to the data of different chip units on the considerable wafer of being tested described undetermined coefficient is carried out match; The order that described undetermined coefficient is carried out match is,

At first, determine A1, B1, C1, D1 at the transistorized measured data of Large;

At the transistorized measured data of narrow, determine G1 then;

At the transistorized measured data of short, determine F1 again;

At the transistorized measured data of small, determine E1 at last.

The present invention carries out modelling to the current standard deviation under different components size, the different voltage bias condition, has improved the work efficiency and the accuracy of Analogous Integrated Electronic Circuits design.

Embodiment

The model of transistor relative accuracy characteristic to circuit in Analog Circuit Design plays a very important role, because semiconductor technology homogeneity, the influence of equipment, identical transistor its electrical characteristics of diverse location in silicon chip there are differences, the relative accuracy model is used to reflect this species diversity, and the statistical error of characteristics of transistor parameter is described the transistor relative accuracy model that generation can emulation with formula.

The relative accuracy model is most important to be the transistor that solves different physical sizes (Width channel width/Length channel length), the corresponding selection of parameter of the statistic bias of its electrical characteristics VTH (threshold voltage)/Idsat (saturation current) and parameter approximate description formula, can derive following formula by simple transformation to the transistor current formula:

Id=β (Vgs-Vt) ², wherein

Wherein Id represents transistor drain terminal electric current, μ ₀Be carrier mobility, Cox is a gate capacitance, and W and L represent channel width and channel length respectively.

${{\mathrm{\σ}}_{\frac{\mathrm{\ΔId}}{\mathrm{Id}}}}^2=\frac{{{\mathrm{\σ}}_{\mathrm{\β}}}^2}{{\mathrm{\β}}^2}+{{\mathrm{\σ}}_{\mathrm{Vt}}}^2{\left[\frac{2}{\mathrm{Vgs}-\mathrm{Vt}}\right]}^2;$

${\mathrm{\Δ}}_{\mathrm{Id}}={\mathrm{\Δ}}_{\mathrm{\β}}\left[\frac{\mathrm{\δId}}{\mathrm{\δ\β}}\right]+{\mathrm{\Δ}}_{\mathrm{vt}}\left[\frac{\mathrm{\δId}}{\mathrm{\δVt}}\right];$

Δ _Id＝Δ _β(Vgs-Vt) ²+Δ _vt(-2·β·(Vgs-Vt)；

$\frac{{\mathrm{\Δ}}_{\mathrm{Id}}}{\mathrm{Id}}=\frac{{\mathrm{\Δ}}_{\mathrm{\β}}}{\mathrm{\β}}+{\mathrm{\Δ}}_{\mathrm{vt}}[-\frac{2}{\mathrm{Vgs}-\mathrm{Vt}}];$

${{\mathrm{\σ}}_{\frac{\mathrm{\ΔId}}{\mathrm{Id}}}}^2={\left[\frac{{\mathrm{\σ}}_{\mathrm{\β}\%}}{100}\right]}^2+{{\mathrm{\σ}}_{\mathrm{Vt}}}^2{\left[\frac{2}{\mathrm{Vgst}}\right]}^2;$

Vgst=Vgs-Vt wherein, ${\mathrm{\σ}}_{\mathrm{\β}\%}=\frac{\mathrm{Coeff}1}{\sqrt{W\·L}},$ ${\mathrm{\σ}}_{\mathrm{Vt}}=\frac{\mathrm{Coeff}2}{\sqrt{W\·L}}.$

From

As can be seen, the standard deviation of electric current independent with other model parameter, the standard deviation of electric current can be expressed as two variablees---transistor channel area (W * L) and the relation of Vgst; Equally, the standard deviation of electric current is because certain several state-variable causes in theory, comprise oxide thickness (Tox), polysilicon width difference (Leff, Weff), ion injects deviation (Nch), flat-band voltage (VFB) etc., the deviation of these state-variables can be reflected on the model parameter, sets up a kind of corresponding relation.

The invention provides a kind of transistor relative accuracy model method, comprise the steps:

Test different components size, comprise the width W of transistor channel and the length L of transistor channel, test the current value of adjacent transistor under the different bias condition, transistor on the wafer or chip all are to occur in pairs, the data of different chip units on the test considerable wafer, and, count the 3sigma value of Δ Id according to the electric current difference DELTA Id of the paired chip of these data computation;

To VTH0, Tox, K1, U0, RDSW, LINT, seven model parameters of WINT are carried out modelling, wherein

Param＝Param_org+Δparam；

$\mathrm{\ΔVTH}0=\frac{A1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔTOX}=\frac{B1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔK}1=\frac{C1}{\sqrt{W\·L\·M}}+1;$

$\mathrm{\ΔU}0=\frac{D1}{\sqrt{W\·L\·M}}+1;$

$\mathrm{\ΔRDSW}=\frac{E1}{\sqrt{W\·L\·M}};$

$\mathrm{\ΔLINT}=\frac{F1}{\sqrt{W\·M}};$

$\mathrm{\ΔWINT}=\frac{G1}{\sqrt{L\·M}};$

Wherein Param is VTH0, Tox, K1, U0, RDSW, LINT, seven model parameters of WINT, Param_org is VTH0, Tox, K1, U0, RDSW, LINT, the value of seven model parameters of WINT in general models, Δ param is Δ VTH0, Δ Tox, Δ K1, Δ U0, Δ RDSW, Δ LINT, seven model parameters of Δ WINT, A1, B1, C1, D1, E1, F1, G1 is a undetermined coefficient, and M is the parallel transistor number, according to the data of different chip units on the considerable wafer of being tested described undetermined coefficient is carried out match.Described undetermined coefficient is carried out match can be realized by corresponding eda software.

The span of the length L product of the width W of described transistor channel and transistor channel from the design rule minimum value to 10000um ²

Described different bias condition is the combination of the difference Vgst of gate source voltage difference Vds and gate voltage and cut-in voltage.

The order that described undetermined coefficient is carried out match is:

At first, determine A1, B1, C1, D1 at the transistorized measured data of Large;

At the transistorized measured data of narrow, determine G1 then;

At the transistorized measured data of short, determine F1 again;

At the transistorized measured data of small, determine E1 at last.

Transistor model is made the SUBCKT form, on conventional model based, revise mutually deserved parameter, make the relative accuracy model, as follows:

.lib?mismatch

.subckt?nfets?d?g?s?b

+wf＝10e-6?lf＝0.13e-6?nf＝1?as＝asn?ad＝adn?ps＝psn?pd＝pdn

.PARAM

+Mis_VTH0N＝’A1/sqrt(WF*LF*NF)’

+Mis_U0N＝’D1*/sqrt(WF*LF*NF)+1’

+Mis_K1N＝’C1/sqrt(WF*LF*NF)+1’

+Mis_TOXN＝’B1/sqrt(WF*LF*NF)’

+Mis_RDSW＝’E1/sqrt(WF*LF*NF)+1’

+Mis_LINT＝’F1/sqrt(WF*NF)’

+Mis_WINT＝’G1/sqrt(LF*NF)’

mds?d?g?s?b?nfet?l＝lf?w＝wf?m＝nf

+as＝asn?ad＝adn?ps＝psn?pd＝pdn

.lib″mosfet.lib″core_model

.ends?nfets

.endl?mismatch

.LIB?core_model

.MODEL?NFET?NMOS

+tox＝’2.8e-009+Mis_VTH0N’

+wint＝‘1.182e-008+Mis_WINT’

+lint＝’5e-009+Mis_LINT’

+vth0＝’0.60+Mis_VTH0N’

+k1＝‘0.6931*Mis_K1N

+u0＝‘0.05075*Mis_U0N’

+rdsw＝‘330*Mis_RDSW’

.ENDL?core_model

In sum, the present invention is by measuring the current value of different Vds of adjacent transistor and Vgs bias point, conclude different crystal pipe size, its electric current difference under the different bias voltages, by choosing the proper model parameter, defining accurately, the model parameter formula is described, and by certain model parameter extraction method, extract the relative accuracy model parameter, make this model can reflect different size, the electric current difference of the adjacent transistor under the different bias voltages is to the different components size, current standard deviation under the different voltage bias conditions is carried out modelling, has improved the work efficiency and the accuracy of Analogous Integrated Electronic Circuits design.

Claims (3)

1. transistor relative accuracy model method, it is characterized in that, comprise the steps: to test the different components size, comprise the width W of transistor channel and the length L of transistor channel, test the current value of adjacent transistor under the different bias condition, the data of different chip units on the test considerable wafer, and, count the 3sigma value of Δ Id according to the electric current difference DELTA Id of the paired chip of these data computation;

To VTH0, Tox, K1, U0, RDSW, LINT, seven model parameters of WINT are carried out modelling, wherein

Param＝Param_org+Δparam；

Wherein Param is VTH0, Tox, K1, U0, RDSW, LINT, seven model parameters of WINT, Param_org is VTH0, Tox, K1, U0, RDSW, LINT, the value of seven model parameters of WINT in general models, Δ param is Δ VTH0, Δ Tox, Δ K1, Δ U0, Δ RDSW, Δ LINT, seven model parameters of Δ WINT, A1, B1, C1, D1, E1, F1, G1 is a undetermined coefficient, and M is the parallel transistor number, according to the data of different chip units on the considerable wafer of being tested described undetermined coefficient is carried out match; The order that described undetermined coefficient is carried out match is,

At first, determine A1, B1, C1, D1 at the transistorized measured data of Large;

At the transistorized measured data of narrow, determine G1 then;

At the transistorized measured data of short, determine F1 again;

At the transistorized measured data of small, determine E1 at last.

2. transistor relative accuracy model method according to claim 1 is characterized in that, the span of the length L product of the width W of described transistor channel and transistor channel from the design rule minimum value to 10000um ²

3. transistor relative accuracy model method according to claim 1 is characterized in that, described different bias condition are the combination of the difference Vgst of gate source voltage difference Vds and gate voltage and cut-in voltage.