CN101458304A - Embedded boundary scanning technique verification platform - Google Patents
Embedded boundary scanning technique verification platform Download PDFInfo
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- CN101458304A CN101458304A CNA2008102079262A CN200810207926A CN101458304A CN 101458304 A CN101458304 A CN 101458304A CN A2008102079262 A CNA2008102079262 A CN A2008102079262A CN 200810207926 A CN200810207926 A CN 200810207926A CN 101458304 A CN101458304 A CN 101458304A
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Abstract
The invention relates to an embedded boundary scan technology testing platform, which comprises a plurality of embedded module test and maintenance bus interface units connected with a TM bus and a JTAG link interface; the embedded module test and maintenance bus interface unit is provided with a JTAG interface; the JTAG interface is connected with the JTAG link interface; a principal and subordinate communication protocol is used between the embedded module test and maintenance bus interface units. As an improvement, the invention also comprises a bus monitor; a plurality of embedded module test and maintenance bus interface units are connected with the bus monitor. In the invention, built-in self-testing and functional circuits are divided, therefore, wire connection and welding faults can be detected well before the normal work, state monitoring and fault positioning can be carried out during the working process, thus not only meeting the requirement of a module during the production debug, but also meeting the requirement of on-site maintenance in use.
Description
Technical field
The invention belongs to integrated circuit (IC) design and embedded testing technical field, particularly boundary scan technique.
Background technology
Along with growing field use software and microprocessor are controlled various embedded devices, complicated day by day system is tested fast and effectively seem important further.In order to reduce the guarantee expense, test macro must be implemented centralized management, united and coordinating, improves test mass by embedded diagnostic data, walks architecture, standardized road for development.Along with the complexity of development of technology and system is more and more higher, reliability, maintainability and comprehensive coverage work become the important component part of development engineering.
Boundary scan technique is based on IEEE std 1149.1 standards (IEEE Standard TestAccess Port and Boundary-Scan Architecture, be test access port and boundary-scan architecture), sometimes IEEE std 1149.1 standards are just called JTAG.This standard is developed in the eighties in 20th century by the combined testing action group (JTAG) that forms of several companies in North America and Europe.It can be tested in many levels, device programming and debugging, is used widely in Electronic Design.External ASSET, CORELIS, all there is the boundary scan technique test products in companies such as JTAG Tech., are used for the production test robotization, the information-based field of quality management.
Module testing and Maintenance bus (module test and maintenance bus), promptly the TM bus also claims TM, along with developing rapidly of integrated circuit produces.IEEE has issued standard 1149.5Module Test and Maintenance Bus Protocol " module testing and Maintenance bus agreement " in nineteen ninety-five.On the basis of adopting by equation foreign standard, worked out national military standard GJB 5440 in 2005, and implemented by Commission of Science, Technology and Industry for National Defence's issue in 2005.
TM bus and boundary scan agreement all are the testing standards of IEEE 1149 series, and 1149.5 (TM buses) lay particular emphasis on module testing, are the subsystem buses; 1149.1 (test access port and boundary-scan architecture) lays particular emphasis on boundary scan and chip-scale test.1149.1 a kind of port as TM has detailed using method in standard.
TM and boundary scan technique can will be sent to from aircraft (avionics system, gearing etc.) gathered data prediction and the diagnostic system, are used for electronic equipment from detecting.From the logistics support angle, embedded boundary scanning technique verification platform is that bridge is erected in factory, overhaul base, relaying level and base level maintenance, realizes data sharing.
Because the diversity of the design of functional module, the general purpose test equipment of various functional modules not being tested in the prior art, when function module design changes, need the corresponding testing apparatus of special development to test the workload of the test of this increase and complexity.
Summary of the invention
The objective of the invention is to, a kind of embedded boundary scanning technique verification platform is provided, to solve the device interconnection of band jtag port, detect weld defects, discrete signal and JTAG device are carried out the state sampling, and problems such as fault analysis and diagnosis are to improve the airborne products design level.
The present invention adopts following technical scheme:
A kind of embedded boundary scanning technique verification platform, comprise: a plurality of embedded module tests and maintenance bus interface unit and the JTAG LI(link interface) that are connected by the TM bus, described a plurality of embedded module test and maintenance bus interface unit are provided with jtag interface, described jtag interface is connected with described JTAG LI(link interface), adopts the master-slave communication stipulations between described embedded module test and the maintenance bus interface unit.
As a kind of improvement of the present invention, also comprise bus monitor, described a plurality of embedded module tests are connected with described bus monitor with the maintenance bus interface unit.As another improvement of the present invention, comprise primary module in described a plurality of embedded module test and the maintenance bus interface unit and from module, described primary module and partly be arranged in same chip from the logical process of module is describedly distinguished by the module identifier of input from module.
One improve as of the present invention, one in described a plurality of embedded module tests and the maintenance bus interface unit is the backup primary module again, when primary module breaks down, during the primary module function on of this backup primary module, substitutes the primary module that breaks down.
As a kind of optimal way of the present invention, the quantity of described embedded module test and maintenance bus interface unit is 3, is respectively primary module, backup primary module and from module, described primary module, backup primary module and be equipped with the RS232 interface from module.
One improve again as of the present invention, described primary module comprises internal register group, the transmission fifo buffer that microprocessor is connected with the microprocessor communication and receives fifo buffer, the bag control state machine that is connected with described internal register group, transmission fifo buffer and the communication of reception fifo buffer, be connected in transmitter, collision detection module and receiver between described bag control state machine and the TM bus, described transmitter, collision detection module and receiver are connected with signal lines in the TM bus.
One improve again as of the present invention, describedly comprise the internal register group that microprocessor is connected with the microprocessor communication from module, send fifo buffer and receive fifo buffer, with described internal register group, send fifo buffer and receive the bag control state machine that the fifo buffer communication is connected, be connected in the transmitter between described bag control state machine and the TM bus, collision detection module and receiver, described transmitter, the collision detection module is connected with signal lines in the TM bus with receiver, also is connected with boundary scan interface on the described microprocessor, input discrete magnitude port and output discrete magnitude port.
The present invention can finely must detect line and solder failure realizing Built-in Self Test and functional circuit separately before operate as normal, carry out condition monitoring and localization of fault in the course of work.
The present invention both can satisfy the needs of module in producing debugging as external automatic test equipment (ATE), can satisfy the needs of the field maintemance in the use again.ATE can discern different from module, finishes test and safeguards.Therefore, just can produce a kind of " omnipotent ATE " in large quantity,, various distinct devices be tested and safeguarded by the on-line loaded of test vector.
Description of drawings
Fig. 1 is the embedded boundary scanning technique verification platform structural representation.
Connection diagram when Fig. 2 uses for embedded boundary scanning technique verification platform of the present invention.
Fig. 3 is the primary module structural representation.
Fig. 4 is from the modular structure synoptic diagram.
Embodiment
As shown in Figure 1, a kind of embedded boundary scanning technique verification platform, comprise a plurality of embedded module tests and maintenance bus interface unit (the bus interface unit that are connected by the TM bus, be called for short BIU) and the JTAG LI(link interface), described a plurality of embedded module test and maintenance bus interface unit are provided with jtag interface, and described jtag interface is connected with described JTAG LI(link interface).
Wherein, also comprise bus monitor, described a plurality of embedded module tests are connected with described bus monitor with the maintenance bus interface unit.
Wherein, described TM bus is the serial core bus with multi-site topological structure, is made up of four essential signal wires and an optional signal wire in the following table:
| Signal name | I/O | Explanation |
| MCLK | Input | The TM bus clock |
| MCTL | I/O | The total line traffic control of TM |
| MMD | I/O | TM bus master data |
| MSD | I/O | The TM bus is from module data |
| MPR | I/O | The TM bus is suspended (optional) |
Wherein, adopt the master-slave communication stipulations between the described BIU.Any time has only a BIU to obtain ownership, and the BIU of acquire the right of control is a primary module, and remaining BIU is from module, by the TM bus detecting information is sent to primary module from module, primary module can by with serial ports and upper machine communication.Adopt the full duplex asynchronous communication interface of RS232 to be connected between described embedded boundary scanning technique verification platform and the host computer.
Above-mentioned embedded boundary scanning technique verification platform work journey is as follows:
As shown in Figure 2, the tested module of tested end is connected with the described JTAG LI(link interface) of embedded boundary scanning technique verification platform, and described embedded boundary scanning technique verification platform is connected with host computer.Embedded software on embedded boundary scanning technique verification platform operation sheet, operation communications protocol software on host computer and embedded boundary scanning technique verification platform.
Wherein, to generate software be a series of codes that BSDL (Boundary Scan Description) file according to the device of band edge circle scanning port and circuit connecting relation produce to test vector.Embedded software is write boundary scan testing access port from module to these codes on the sheet, tested module is tested, the data of returning are also passed through the TM bus transfer to main plate through the module of associating, collecting data and the anticipation value returned by primary module compares, obtain failure condition, be sent to host computer, host computer fit applications software display working condition directly perceived.The present invention with finish merely FLASH data load patent of invention different be, defined data transfer format here, data and test result all transmit according to specific data layout, observe the agreement in the communications protocol software between host computer and the verification platform.
Wherein, distinguish by the module identifier of input from module.Described bus monitor is regularly monitored the activity on the TM bus, and when sending " master " signal, corresponding BIU is as current primary module work, when send " from " during signal, corresponding BIU as current from module work.When system to reliability requirement than condition with higher under, might need primary module to have redundancy feature, so just can when primary module breaks down, the ownership of TM be transferred on the another one BIU.Be among the BIU one and be the backup primary module, when primary module did not break down, the primary module function of this backup primary module did not start.When primary module broke down, the primary module function on of this backup primary module substituted the primary module that breaks down.Data analysis is finished by the microprocessor on the primary module.
Can hang 250 BIU in theory on the TM bus, the present invention preferably is provided with 3 BIU.3 BIU are respectively primary module, backup primary module and from module.The backup primary module is when the primary module function is not activated, as from module work.On these 3 BIU one road RS232 interface is arranged respectively, be used for and upper machine communication and programming FLASH, the program downloads of programmable chip.
As shown in Figure 3, described primary module comprises: the internal register group that microprocessor is connected with the microprocessor communication, transmission FIFO (first-in first-out) impact damper and reception fifo buffer, the bag control state machine that is connected with described internal register group, transmission fifo buffer and the communication of reception fifo buffer, be connected in transmitter, collision detection module and receiver between described bag control state machine and the TM bus, described transmitter, collision detection module and receiver are connected with signal lines in the TM bus.Wherein, described transmitter is used for converting parallel signal to serial signal, and described receiver is used for converting serial signal to parallel signal.
Wherein, described internal register group comprises startup register, interrupt register, transmit status register, accepting state register, length bag register, principal and subordinate's enable register etc., respectively to being applied to deposit contents such as startup, interruption, transmit status, state, length package informatin, principal and subordinate's enable information.
The protocol chip of described primary module adopts top-down design philosophy, promptly at first on the basis of digestion IEEE1149.5 agreement, the interface and the function of dividing each submodule are carried out independently logical design, at last all submodules are linked up and carry out comprehensive simulating, placement-and-routing.
The function that described primary module is realized is:
1, detects whether MMD, MCTL conflict is arranged on the bus, withdraw from if having then, to guarantee a having only primary module on the bus;
2, guarantee the normal startup of message sequence, the end of control messages;
3, the correct look-at-me that receives from module;
4, the MSD signal is changed into parallel data and be sent to host computer, to be further analyzed.
The concrete course of work of described primary module is: described microprocessor is write the message of needs test in sequence and is sent in the fifo buffer, initiation message is handled and is transmitted, described bag control state machine is controlled described transmitter and 16 parallel bit data are converted to serial 17 bit data is sent to MMD signal wire on the TM bus, drives MCTL simultaneously; Described receiver receives the MSD and the MPR signal of TM bus, described bag control state machine is when the end of message, or occur that MSD interrupts or send interruption during other error situations, described microprocessor receives fifo buffer by visit and the internal register group is controlled and the read test result.
Described function from module is divided with primary module similar, and the embedded program of promptly described microprocessor operation on module and primary module corresponds to the primary module program respectively and from modular program.Increased boundary scan interface and input, output discrete magnitude port on the basis of described primary module, these three kinds of interfaces have been contained most of interface type.Described from modular structure as shown in Figure 4.
Particularly, describedly comprise: the internal register group that microprocessor is connected with the microprocessor communication from module, send fifo buffer and receive fifo buffer, with described internal register group, send fifo buffer and receive the bag control state machine that the fifo buffer communication is connected, be connected in the transmitter between described bag control state machine and the TM bus, collision detection module and receiver, described transmitter, the collision detection module is connected with signal lines in the TM bus with receiver, also is connected with boundary scan interface on the described microprocessor, input discrete magnitude port and output discrete magnitude port.
The described function of finishing from module has:
1. accept the data on the bus, and can be on the MSD of TM bus and MPR signal wire transmission information;
2. the processing primary module sends to the command information from module;
3. produce according to specific circumstances and interrupt application;
4. when unripe transmission data, can produce and suspend the application signal;
5. whether the electronic system that detects the place backboard is working properly.
From the concrete course of work of module be: described MCTL and MMD signal on module monitors TM bus in case find enabling signal, receives the MMD signal on the TM bus, by the microprocessor judges type of message and make response; And will be to described internal register group from the state recording of module; When having little time deal with data, send MPR from module; When the situation of needs interruption taking place, send signal by MSD from module.
Claims (9)
1, a kind of embedded boundary scanning technique verification platform, it is characterized in that comprising: a plurality of embedded module tests and maintenance bus interface unit and the JTAG LI(link interface) that are connected by the TM bus, described a plurality of embedded module test and maintenance bus interface unit are provided with jtag interface, described jtag interface is connected with described JTAG LI(link interface), adopts the master-slave communication stipulations between described embedded module test and the maintenance bus interface unit.
2, embedded boundary scanning technique verification platform according to claim 1 is characterized in that: also comprise bus monitor, described a plurality of embedded module tests are connected with described bus monitor with the maintenance bus interface unit.
3, embedded boundary scanning technique verification platform according to claim 2 is characterized in that:
Comprise primary module in described a plurality of embedded module test and the maintenance bus interface unit and from module, described primary module and partly be arranged in same chip from the logical process of module is describedly distinguished by the module identifier of input from module.
4, embedded boundary scanning technique verification platform according to claim 3 is characterized in that:
One in described a plurality of embedded module test and the maintenance bus interface unit is the backup primary module, when primary module did not break down, this backup primary module was from module, when primary module breaks down, the primary module function on of this backup primary module substitutes the primary module that breaks down.
5, embedded boundary scanning technique verification platform according to claim 4 is characterized in that:
The quantity of described embedded module test and maintenance bus interface unit is 3, is respectively primary module, backup primary module and from module, described primary module, backup primary module and be equipped with the RS232 interface from module.
6, embedded boundary scanning technique verification platform according to claim 5, it is characterized in that: described primary module comprises the internal register group that microprocessor is connected with the microprocessor communication, send fifo buffer and receive fifo buffer, with described internal register group, send fifo buffer and receive the bag control state machine that the fifo buffer communication is connected, be connected in the transmitter between described bag control state machine and the TM bus, collision detection module and receiver, described transmitter, the collision detection module is connected with signal lines in the TM bus with receiver.
7, embedded boundary scanning technique verification platform according to claim 6, it is characterized in that: described internal register group comprises startup register, interrupt register, transmit status register, accepting state register, length bag register, principal and subordinate's enable register etc., respectively to being applied to deposit startup, interruption, transmit status, state, length package informatin, principal and subordinate's enable information content.
8, according to claim 6 or 7 described embedded boundary scanning technique verification platforms, it is characterized in that: describedly comprise the internal register group that microprocessor is connected with the microprocessor communication from module, send fifo buffer and receive fifo buffer, with described internal register group, send fifo buffer and receive the bag control state machine that the fifo buffer communication is connected, be connected in the transmitter between described bag control state machine and the TM bus, collision detection module and receiver, described transmitter, the collision detection module is connected with signal lines in the TM bus with receiver, also is connected with boundary scan interface on the described microprocessor, input discrete magnitude port and output discrete magnitude port.
9, embedded boundary scanning technique verification platform according to claim 8, it is characterized in that: described internal register group comprises startup register, interrupt register, transmit status register, accepting state register, length bag register, principal and subordinate's enable register, respectively to being applied to deposit startup, interruption, transmit status, state, length package informatin, principal and subordinate's enable information content.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706552B (en) * | 2009-07-02 | 2011-09-28 | 苏州国芯科技有限公司 | Configurable on-chip testing module supporting encapsulation of different pins of chip |
| CN101458305B (en) * | 2008-12-26 | 2012-07-04 | 中国航空无线电电子研究所 | Embedded module test and maintenance bus system |
| CN105068445A (en) * | 2015-07-31 | 2015-11-18 | 中国航空无线电电子研究所 | Multifunctional signal route adaption matrix |
| CN105512064A (en) * | 2014-09-26 | 2016-04-20 | 中国航空工业第六一八研究所 | Online loading system for configuration information of communication controller and method for same |
| CN108628710A (en) * | 2017-03-24 | 2018-10-09 | 联发科技股份有限公司 | Test controller, bus system and test method |
| CN111239593A (en) * | 2018-11-29 | 2020-06-05 | 恩智浦有限公司 | Test system with embedded tester |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN112328502A (en) * | 2020-11-30 | 2021-02-05 | 中国航空工业集团公司西安航空计算技术研究所 | High-coverage data processing module testing method and device |
| CN114113990A (en) * | 2021-08-31 | 2022-03-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
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2008
- 2008-12-26 CN CNA2008102079262A patent/CN101458304A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458305B (en) * | 2008-12-26 | 2012-07-04 | 中国航空无线电电子研究所 | Embedded module test and maintenance bus system |
| CN101706552B (en) * | 2009-07-02 | 2011-09-28 | 苏州国芯科技有限公司 | Configurable on-chip testing module supporting encapsulation of different pins of chip |
| CN105512064A (en) * | 2014-09-26 | 2016-04-20 | 中国航空工业第六一八研究所 | Online loading system for configuration information of communication controller and method for same |
| CN105068445A (en) * | 2015-07-31 | 2015-11-18 | 中国航空无线电电子研究所 | Multifunctional signal route adaption matrix |
| CN108628710A (en) * | 2017-03-24 | 2018-10-09 | 联发科技股份有限公司 | Test controller, bus system and test method |
| CN111239593A (en) * | 2018-11-29 | 2020-06-05 | 恩智浦有限公司 | Test system with embedded tester |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
| CN112328502A (en) * | 2020-11-30 | 2021-02-05 | 中国航空工业集团公司西安航空计算技术研究所 | High-coverage data processing module testing method and device |
| CN114113990A (en) * | 2021-08-31 | 2022-03-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
| CN114113990B (en) * | 2021-08-31 | 2023-08-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
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