CN101452956A

CN101452956A - High voltage PMOS device and production method

Info

Publication number: CN101452956A
Application number: CNA2007100943833A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-12-06
Filing date: 2007-12-06
Publication date: 2009-06-10
Anticipated expiration: 2027-12-06
Also published as: CN101452956B

Abstract

The invention discloses a high-voltage PMOS device and a manufacture method thereof. A double-work-function gate is used to replace the prior single-work-function gate, and the double-work-function gate consists of a P+ doped polysilicon gate part closet to a source-end direction and an N+ doped polysilicon gate part close to a drain-end direction, so as to remarkably increase the drive current of a high-voltage PMOS transistor and then improve the drive capability and speed of the PMOS device under the circumstance of ensuring that the threshold voltage, breakdown voltage, cutoff current and other characteristics of the PMOS device remain the same. Therefore, the contradiction between the drive current and the breakdown voltage is solved.

Description

High voltage PMOS device and manufacture method

Technical field

The present invention relates to a kind of high voltage PMOS device, the invention still further relates to a kind of manufacture method of described high voltage PMOS device for this reason with high drive current.

Background technology

High voltage PMOS device all adopts the buried channel structure usually, promptly uses heavy doping N type polysilicon bar and buried channel, to improve hole mobility, increases the drive current of device.In order further to improve drive current, generally realize, but these means all can be subjected to the restriction of device creepage and puncture voltage by reducing methods such as gate oxide thickness, shortening channel length or reduction drift zone resistance.And thin gate oxide thickness can cause bigger GIDL effect, brings big leakage current; Short channel length can reduce the puncture voltage of raceway groove; Lower drift zone resistance then can reduce the puncture voltage of drain terminal knot.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of high voltage PMOS device, can increase the drive current of PMOS device, and then improve its driving force under the constant situation of the characteristics such as threshold voltage, puncture voltage and cut-off current that keep the PMOS device; For this reason, the present invention also provides a kind of manufacture method of described high voltage PMOS device.

For solving the problems of the technologies described above, the invention provides a kind of high voltage PMOS device, comprise the double work function grid, and described double work function grid are by forming near the P+ doped polycrystalline silicon gate part of source extreme direction with near the N+ doped polycrystalline silicon gate part of drain terminal direction.

The present invention also provides a kind of manufacture method of described high voltage PMOS device, comprising:

The deposit polysilicon gate, and carry out the N+ ion from described polycrystalline silicon gate surface and inject, make described polysilicon gate become the operation of N+ doped polysilicon gate;

Select the P+ source and drain areas of described high voltage PMOS device and polysilicon gate near the subregion of drain terminal by photoresist, carry out the operation that the P+ ion injects then; And,

Remove described photoresist, and silicon chip is carried out the operation of high annealing.

The present invention is owing to adopted technique scheme, has such beneficial effect, promptly use the double work function grid to replace traditional single work function grid, and described double work function grid are made by constituting near the P+ doped polycrystalline silicon gate part of source extreme direction and the N+ doped polycrystalline silicon gate part of close drain terminal direction, can be thereby guaranteed at the threshold voltage that keeps the PMOS device, under the constant situation of characteristic such as puncture voltage and cut-off current, enlarge markedly the drive current of high voltage PMOS transistor, and then improved the driving force and the speed of PMOS device, solved the contradiction between drive current and the puncture voltage.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the sectional structure chart by the high voltage PMOS device of prior art manufacturing;

Fig. 2 is the schematic flow sheet according to an embodiment of high voltage PMOS device manufacture method of the present invention;

Fig. 3 a-3g is according to the sectional structure chart in the method manufacturing high voltage PMOS device process shown in Figure 2.

Embodiment

In one embodiment, as shown in Figure 2, high voltage PMOS device manufacture method of the present invention may further comprise the steps:

The first step is injected buried channel and the P-drift region that forms high voltage PMOS device by ion on silicon substrate, cross-section structure at this moment is shown in Fig. 3 a.

In second step, at silicon substrate grown on top one deck gate oxide, structure at this moment is shown in Fig. 3 b.

The 3rd step, deposit one deck polysilicon gate on gate oxide, and carry out the N+ ion from described polycrystalline silicon gate surface and inject, inject ion dosage be 1e15cm ^-2～3e15cm ^-2, make described polysilicon gate become pure N+ doped polysilicon gate, cross-section structure at this moment is shown in Fig. 3 c.

The 4th step, use known photoetching technique, described polysilicon gate is carried out etching, form the grid of device, cross-section structure at this moment is shown in Fig. 3 d.

The 5th step formed monox lateral wall in the both sides of described grid, and structure at this moment is shown in Fig. 3 e.

The 6th step, select the subregion of the P+ source and drain areas and the close drain terminal of polysilicon gate of described high voltage PMOS device by photoresist, carrying out the P+ ion then injects, the dosage of the P+ ion that is injected will be even as big as compensating the N type impurity of described pure N+ doped polysilicon gate, and the dosage that at this moment injects ion generally speaking is 4e15cm ^-2～6e15cm ^-2Thereby in the source and drain areas that has formed described high voltage PMOS device, polysilicon gate has been divided into the part of the P+ doped polysilicon gate with close source extreme direction and near the N+ doped polycrystalline silicon gate part of drain terminal direction, cross-section structure at this moment is shown in Fig. 3 f.Wherein, the polysilicon gate that photoresist is selected is near the subregion of drain terminal, should guarantee that last N+ doped polycrystalline silicon gate part that forms and the length ratio between the P+ doped polycrystalline silicon gate part require consistent with Devices Characteristics, for example higher if desired PMOS drive current then should suitably increase the length of described P+ doped polycrystalline silicon gate part as required.

The 7th step, to remove photoresist, and silicon chip is carried out high temperature rapid thermal annealing, annealing temperature is 1000～1100 ℃, and annealing time is 10～25 seconds, finally finishes the making of double work function grid, and cross-section structure at this moment is shown in Fig. 3 g.

Certainly, the method of manufacturing high voltage PMOS transistor of the present invention is not limited to the foregoing description, one of ordinary skill in the art should it will also be appreciated that realization has other alternatives of the high voltage PMOS device of following structure: promptly have the double work function grid, and described double work function grid comprise near the P+ doped polycrystalline silicon gate part of source extreme direction and the N+ doped polycrystalline silicon gate part of close drain terminal direction.And the length ratio between N+ doped polysilicon gate and the P+ doped polysilicon gate requires decision by Devices Characteristics.For the PMOS transistor of this structure, because threshold voltage is controlled by the N+ doped polysilicon gate, therefore described threshold voltage can remain unchanged; And because the raceway groove of P+ doped polysilicon gate control has lower threshold voltage, this just is equivalent to and has shortened length of effective channel, thereby has increased the drive current of PMOS device; Simultaneously,, therefore when increasing drive current, can not increase device creepage, so yet punch through voltage that can the leakage of reduction source because high voltage PMOS transistor of the present invention do not do any variation to channel doping.So, in sum, the present invention has enlarged markedly drive current under the constant situation of the characteristics such as threshold voltage, puncture voltage and cut-off current that keep high voltage PMOS device, improve the driving force and the speed of PMOS device, solved the contradiction between drive current and the puncture voltage.

Claims

1, a kind of high voltage PMOS device is characterized in that, comprises the double work function grid, and described double work function grid are by forming near the P+ doped polycrystalline silicon gate part of source extreme direction with near the N+ doped polycrystalline silicon gate part of drain terminal direction.

According to the described high voltage PMOS device of claim 1, it is characterized in that 2, the length ratio in the described double work function grid between P+ doped polycrystalline silicon gate part and the N+ doped polycrystalline silicon gate part depends on the characteristic requirement of described high voltage PMOS device.

3, the manufacture method of the described high voltage PMOS device of a kind of claim 1 is characterized in that, comprising:

The deposit polysilicon gate, and carry out the N+ ion from described polycrystalline silicon gate surface and inject, make described polysilicon gate become the operation of pure N+ doped polysilicon gate;

Remove described photoresist, and the operation that silicon chip is annealed.

According to the manufacture method of the described high voltage PMOS device of claim 3, it is characterized in that 4, the dosage of the N+ ion that is injected is 1e15cm ^-2～3e15cm ^-2

According to the manufacture method of claim 3 or 4 described high voltage PMOS devices, it is characterized in that 5, the dosage of the P+ ion that is injected will be even as big as compensating the N type impurity of described pure N+ doped polysilicon gate.

According to the manufacture method of the described high voltage PMOS device of claim 5, it is characterized in that 6, the dosage of the P+ ion that is injected is 4e15cm ^-2～6e15cm ^-2