CN101452863B - Manufacturing method using compliant layer in package structure with reconfigured crystal grains - Google Patents

Abstract

A packaging structure for reconfiguring a die includes: a die having a plurality of solder pads disposed on an active surface thereof; a packaging body covering the five surfaces of the die; a plurality of bump structures formed by polymer materials disposed in an array on the active surface of the die; a plurality of patterned metal wire segments, one end of which is electrically connected to the plurality of solder pads on the active surface of the die, and the other end of which extends in a fan-out manner and covers each bump structure; and a protective layer, which is used to cover each patterned metal wire segment and a portion of the patterned polymer material layer, and expose the bumps and the patterned metal wire segments covering the bump structures.

Description

Fabrication Method Using Compliant Layer in Die Reconfigured Package Structure

technical field

The invention relates to a semiconductor packaging method, in particular to forming polymer bumps and metal layers on crystal grains to replace tin balls as conductive elements.

Background technique

Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor die (Dice) must have diversified functional requirements, so that the semiconductor die must be configured with more input/output pads ( I/Opads), so that the density of metal pins (pins) has also increased rapidly. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. The ball array package has the advantage of higher density than the lead frame package. In addition, its solder balls are less prone to damage and deformation.

With the popularity of 3C products, such as: cell phone (CellPhone), personal digital assistant (PDA) or iPod, etc., it is necessary to put many complex system chips into a very small space, so in order to solve this problem , a packaging technology called "wafer level package (WLP)" has been developed, which can package the chip before cutting the chip into individual dies. US Patent Publication No. 5,323,051 discloses this "wafer level packaging" technology. However, this "wafer-level packaging" technology increases the number of pads (pads) on the active surface of the die, making the pitch of the pads (pads) too small, in addition to causing problems with signal coupling or signal interference, Also, problems such as reduced reliability of the package may be caused due to the too small pitch of the pads. Therefore, when the die is further shrunk, none of the aforementioned packaging technologies can satisfy.

In order to solve this problem, U.S. Patent No. 7,196,408 has disclosed a wafer that will complete the semiconductor process. After testing and cutting, the test result is a good die (good die) is relocated on another substrate. Then, the packaging process is carried out, so that these relocated dies have a wider spacing, so the pads on the dies can be properly allocated, for example, using the lateral extension (fan out) technology, so it can Effectively solve the problem of signal coupling or signal interference caused by too small spacing.

However, in order to enable the semiconductor chip to have a smaller and thinner packaging structure, the wafer will be thinned before wafer dicing, such as backside lapping to thin the wafer to 2-20mil, Then cut into individual grains. This thinned die is reconfigured on another substrate, and then a plurality of dies are formed into a package package by injection molding; because the die is very thin, the package is also very thin , so when the package is detached from the substrate, the stress of the package itself will cause the package to warp, increasing the difficulty of the subsequent cutting process.

In addition, after the wafer is diced, when it is reconfigured on another substrate, because the size of the new substrate is larger than the original size, it will not be aligned in the subsequent ball planting process, and the reliability of the packaging structure will be reduced.

Contents of the invention

In view of the problems of ball planting alignment and package warpage described in the background of the invention, the present invention provides an alignment mark using the backside of the die, and a metal layer (UBM) is formed on the die as a conductive element and The packaging structure and method for reconfiguring the grains electrically connected to the pads, and the method for reconfiguring and packaging a plurality of grains. Therefore, the main purpose of the present invention is to configure the adhesive layer on the substrate, and the crystal grains can be accurately placed on the adhesive layer of the substrate by using the plurality of alignment marks configured on the back of the substrate, and the metal layer ( UBM) are respectively used as conductive elements and are electrically connected to the pads to carry out the packaging method of grain reconfiguration, so that in the subsequent process, the ball planting process can be aligned, and the package itself can overcome the stress and After the package is detached from the substrate, it will remain flat, which can effectively improve the yield and reliability of manufacturing and can be applied to low-voltage components, such as memory components, such as RAM.

Another main purpose of the present invention is to provide a kind of packaging method of grain reconfiguration, and it can reconfigure the crystal grain cut out of 12-inch wafer on the substrate of 8-inch wafer, can effectively utilize the 8-inch wafer like this The existing packaging equipment does not need to re-establish the packaging equipment for 12-inch wafers, which can reduce the packaging cost of 12-inch wafers.

Another main purpose of the present invention is to provide a packaging method for grain reconfiguration, so that the chips that are packaged are all "known good dies" (Known good die), which can save packaging materials, so it can also reduce The cost of the process.

Another main purpose of the present invention is to provide a packaging method for grain reconfiguration, so that the chips that are packaged are all "known good dies", which can save packaging materials, so it can also reduce The cost of the process.

According to the above, the present invention provides a packaging method for die reconfiguration, including: providing a plurality of dies, each die has an active surface and a plurality of pads are arranged on the active face; picking and placing the plurality of dies On a substrate, each crystal grain connects the active surface with an adhesive layer disposed on the substrate in a flip-chip manner; a polymer material layer is formed on the substrate and part of the crystal grain; the covering mold device is placed on the On the polymer material layer, to planarize the polymer material layer, and make the polymer material layer fill between a plurality of crystal grains and cover each crystal grain; separate from the mold device to expose the surface of the polymer material layer; separating the substrate to expose the active surface of each die and each pad to form a package; forming a first sacrificial layer to cover the active face of each die and each pad; forming a first Two sacrificial layers are on the first sacrificial layer; part of the second sacrificial layer and the first sacrificial layer are removed to form a stepped structure, and a plurality of welding pads are formed at a plurality of pads corresponding to the active surface of each crystal grain Holes to expose each pad; form a plurality of patterned metal line segments on the second sacrificial layer and the first sacrificial layer, and form electrical connections with a plurality of pads on the active surface of each die ; forming a patterned protective layer to cover a plurality of patterned metal line segments and exposing part of the patterned metal line segments on the second sacrificial layer; and dicing the package to form a plurality of independently completed Packaged crystal grains, wherein the five sides of each crystal grain are covered by polymer material layers.

According to the packaging method for crystal grain reconfiguration, the present invention also discloses a wafer-level chip packaging structure, which includes: a chip with a plurality of solder pads on its active surface, and a package covering five surfaces of the chip. , a patterned polymer material layer and a plurality of patterned metal wire segments covering part of the patterned polymer material layer, the plurality of patterned metal wire segments are electrically connected to the active surface of each crystal grain A plurality of welding pads are characterized in that: the patterned polymer material layer forms a stepped structure extending outwards (fan out) on the active surface of the crystal grain and a part of the outer area, wherein the outward extending There is a higher structure in the stepped structure at the end point of the die, and a hole is formed at a plurality of pads relative to the active surface of the die to expose each pad; a plurality of patterned metal line segments are formed in the pattern On the polymerized polymer material layer, so that the plurality of pads on the active surface of each crystal grain are electrically connected to the plurality of patterned metal line segments on the ladder-shaped polymer material layer; and a protective layer, To cover a plurality of patterned metal line segments and a part of the patterned polymer material layer, and expose a surface of a plurality of patterned metal line segments on the higher patterned polymer material layer in the ladder structure .

Description of drawings

In order to have a further understanding of the purpose, structure, features, and functions of the present invention, the following examples and accompanying drawings are described in detail below, wherein:

Figure 1 is a schematic diagram representing the prior art;

2 is a top view of a packaging structure on the backside of a substrate with alignment marks according to the technology disclosed in the present invention; and

3A to 3G are schematic diagrams of various steps of a packaging structure formed by a packaging method using die reconfiguration of wafer alignment marks according to the technology disclosed in the present invention.

Detailed ways

The direction of the present invention discussed here is a packaging method for reconfiguration of dies, a method of reconfiguring a plurality of dies on another substrate and then packaging them. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Clearly, the practice of the invention is not limited to specific details of the manner in which chips are stacked, with which those skilled in the art are familiar. On the other hand, well-known chip formation methods and detailed steps of back-end processes such as chip thinning are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. Subsequent patent scope shall prevail.

In the modern semiconductor packaging process, a wafer (wafer) that has completed the front end process (Front End Process) is first subjected to a thinning process (Thinning Process), for example, the thickness of the chip is ground to between 2-20mil; and then , carry out the cutting (sawing process) of the wafer to form grains one by one; then, use a pick and place device (pick and place) to place the grains one by one on another substrate 100, as shown in FIG. 1 Show. Obviously, the grain spacing area on the substrate 100 is larger than that of the grains 110. Therefore, these relocated grains 110 can have a wider spacing, so the bonding pads on the grains 110 can be properly placed. distribute. In addition, the packaging method used in this embodiment can reconfigure the crystal grains 110 cut from the 12-inch wafer on the substrate 100 of the 8-inch wafer, so that the existing packaging equipment for the 8-inch wafer can be effectively used, and There is no need to re-establish packaging equipment for 12-inch wafers, which can reduce packaging costs for 12-inch wafers. Then it should be emphasized that the embodiment of the present invention does not limit the use of the substrate 100 with an 8-inch wafer size, as long as it can provide the function of bearing, for example: glass, quartz, ceramics, circuit board or metal foil (metal foil) etc. , can be used as the substrate 100 of this embodiment, so the shape of the substrate 100 is not limited.

Please refer to FIG. 2 , which is a top view of a substrate with alignment marks on its backside. As shown in FIG. 2 , a plurality of alignment marks 202 are arranged on the upper surface of the wafer substrate in the x-y direction on the back side. Known by the previous statement, when a wafer (not shown in the figure) forms a plurality of crystal grains after cutting, and then these crystal grains are arranged one by one on the new substrate 20 again, due to the gap between the new substrates 20 The grain spacing area is larger than the reconfigured grain, and the ball mount step (ball mount) of the subsequent packaging process will not be aligned, and the conductive element (not shown in the figure) will be accurately formed on the backside of the die. required position, resulting in reduced reliability of the package structure. Therefore, in a specific embodiment of the present invention, the manner of forming the alignment mark 202 can utilize a photo-etching (photo-etching) process, which is to form a plurality of alignment marks 202 on the backside of the substrate 20 in the x-y direction, And its shape is the symbol of the cross. In addition, the method of forming the alignment marks 202 also includes using a laser mark process to form a plurality of alignment marks 202 on the backside of the substrate 20 .

Next, FIG. 3A to FIG. 3G are schematic diagrams showing various steps of the embodiment of the die reconfiguration disclosed in the present invention. First, as shown in FIG. 3A, a wafer (not shown in the figure) configured with a plurality of crystal grains is cut to form a plurality of crystal grains 210. Each crystal grain 210 has an active surface and is positioned on the active surface. A plurality of welding pads 212 are arranged on the substrate 20, and then a plurality of crystal grains 210 are reconfigured on the new substrate 20; wherein, an adhesive layer 30 is arranged on the substrate 20, and the adhesive layer 30 is an elastic adhesive material , such as silicon rubber (silicon rubber), silicone resin (silicon resin), elastic PU, porous PU, acrylic rubber (acrylic rubber) or die cutting glue, etc. Next, using a pick-and-place device (not shown in the figure), the die 210 is placed one by one and attached to the adhesive layer 30 on the substrate 20, wherein the die 210 is flip chip (flip chip) and according to the substrate 20 A plurality of alignment marks on the back side connect the pads 212 on the active surface to the adhesive layer 30 on the substrate 20 . Next, also referring to FIG. 3A , coat a polymer material layer 40 such as polyimide on the substrate 20 and part of the crystal grains 210 , and use a mold device 500 to flatten the polymer material layer 40 so that the polymer material layer 40 forms a planarized surface, and the polymer material layer 40 is filled between the crystal grains 210 and the five sides of each crystal grain 210 are covered by the polymer material layer 40 .

Next, a baking procedure may be selectively performed on the planarized polymer material layer 40 to cure the polymer material layer 40 . Then, carry out the demoulding process, the mold device 500 is separated from the cured polymer material layer 40, to expose the surface of the planarized polymer material layer 40; then, use a cutting knife (not shown in the figure) in A plurality of cutting lines 410 are formed on the surface of the polymer material layer 40, as shown in FIG. 3B; the depth of each cutting line 410 is 0.5-1 mil (mil), and the width of the cutting line 410 is 5 to 25 microns . In a preferred embodiment, the dicing lines 410 can be perpendicular to each other and can be used as a reference line when actually dicing the die.

Finally, the polymer material layer 40 is separated from the substrate 20, for example, the polymer material layer 40 and the substrate 20 are put into a groove of deionized water (not shown in the figure), so that the polymer material layer 40 is bonded to the substrate 20. Layer 30 and substrate 20 are separated from each other to form a package; the package covers five sides of each die 210 and only exposes the pads 212 on the active surface of each die 210 . Since there are many dicing lines 410 on the back of the package relative to the active surface of the die 210, when the first polymer material layer 40 is peeled off from the substrate 20, the stress on the package will be absorbed by these dicing lines 410. The formed area is offset, so the problem of package warpage can be effectively solved.

Next, as shown in FIG. 3C, a first sacrificial layer (dummy layer) 50 and a second sacrificial layer 52 are formed on a plurality of pads 212 on the active surface of each crystal grain 210, wherein the first sacrificial layer 50 and the second sacrificial layer The material of the sacrificial layer 52 can be polyimide or polymer material. Next, part of the second sacrificial layer 52 and part of the first sacrificial layer 50 are removed to form a stepped structure, and a plurality of holes 60 are formed at a plurality of pads 212 corresponding to the active surface of each die 210 , to expose each pad 212; here, the step of removing part of the second sacrificial layer 52 and part of the first sacrificial layer 50 to form a stepped structure includes: forming a pattern on the second sacrificial layer 52 a photoresist layer (not shown in the figure); then, carry out an etching step, such as wet etching, with the first sacrificial layer 50 as an etch stop layer (etch stop layer), etch to remove part of the second sacrificial layer 52; then, use the remaining second sacrificial layer 52 as an etching mask, etch to remove part of the first sacrificial layer 50, and form a plurality of holes 60 corresponding to a plurality of welding pads 212, and expose A plurality of pads 212 . Here, the patterned second sacrificial layer 52 and the first sacrificial layer 50 are located on the active surface of each crystal grain 210 and a part of its outer area forms a stepped structure extending outwards (fan out), wherein the outer portion The higher structure is the second sacrificial layer 52, as shown in FIG. 3D.

Next, as shown in FIG. 3E , a plurality of patterned metal line segments 70 are formed on the second sacrificial layer 52 and the first sacrificial layer 50 , and each patterned metal line segment 70 is connected to the active surface of each crystal grain 210 A plurality of welding pads 212 on the upper part form an electrical connection; wherein the step of forming the patterned metal line segment 70 includes: forming a metal layer (not shown in the figure) to cover between the second sacrificial layer 52 and the first sacrificial layer 50 above; using semiconductor process technology, such as development and etching, first, a patterned photoresist layer (not shown in the figure) is formed on the metal layer; etching is used to remove part of the metal layer and remain on the second sacrificial layer layer 52 and the metal layer on the plurality of bonding pads 212 to form a plurality of patterned metal line segments 70; and stripping the patterned photoresist layer. In addition, the metal line segment can be a UBM metal layer, and its material can be Ti/Cu or TiW/Cu; and the thickness of the UBM metal layer 70 formed on the patterned second sacrificial layer 52 is about 5 micrometers.

Then, as shown in FIG. 3F, a protective layer 80 is formed to cover the structure shown in FIG. 3E; next, a patterned photoresist layer (not shown in the figure) is first formed using semiconductor process technology, such as developing and etching. middle) on the passivation layer 80; etch to remove part of the passivation layer 80 to expose a plurality of patterned metal line segments 70 on the second sacrificial layer 52; and strip the patterned photoresist layer. Here, the patterned metal line segment 70 on the second sacrificial layer 52 and the second sacrificial layer 52 can be regarded as a solder ball, but the patterned metal line segment 70 can be electrically connected to the pad 212, which omits the solder ball. In the general redistribution process (RDL), after the metal line segment is formed, it is also necessary to perform a step of ball planting on the metal line segment. Therefore, in this chip reconfiguration package structure, the pattern on the second sacrificial layer 52 The thinned metal line segment 70 can replace the solder ball as the conductive element. Finally, the package body is diced to form a plurality of independent packaged dies, as shown in FIG. 3G .

In addition, the method of forming a plurality of patterned metal line segments 70 can also form a seed layer on the surfaces of the second sacrificial layer 52, the first sacrificial layer 50 and the plurality of holes 60 after forming the stepped structure. (seed layer) (not shown in the figure), and then form a metal layer on the seed layer by electroplating, and then use semiconductor process technology, such as development and etching, to form a patterned photoresist layer ( not shown in the figure), etch to remove part of the metal layer and the seed layer; peel off the patterned photoresist layer to form a plurality of patterned metal line segments 70 on the surface of the second sacrificial layer 52, as a conductive element.

Although the present invention is disclosed above with the foregoing preferred embodiments, it is not intended to limit the present invention. Any person familiar with the similar technology can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of patent protection of the present invention must be defined by the scope of claims attached to this specification.

Claims (6)

1. the method for packing that crystal grain reconfigures is characterized in that, comprising:

A plurality of crystal grain are provided, and each this crystal grain has on an active face and this active face and disposes a plurality of weld pads, and each this crystal grain is the normal crystal grain of known function;

Pick and place on described a plurality of crystal grain to one substrate, each this crystal grain is to cover crystal type the adhesion coating that this active face and is disposed on this substrate to be connected, and wherein a back side of a back side of this substrate and each this crystal grain all disposes a plurality of registration marks;

Form a polymer material layer on this substrate and the described a plurality of crystal grain of part;

Cover a die device to this polymer material layer,, make this polymer material layer riddle described a plurality of intergranule and coat each this crystal grain with this polymer material layer of planarization;

Break away from this die device, to expose a surface of this polymer material layer;

Break away from this substrate, with this active face and each this weld pad that exposes each this crystal grain, to form a packaging body;

Form one first sacrifice layer this active face and each this weld pad to cover each this crystal grain;

Form one second sacrifice layer on this first sacrifice layer;

Remove part this second sacrifice layer and this first sacrifice layer forming a step structure, and form a plurality of holes, to expose each this weld pad at described a plurality of weld pads place with respect to this active face of each this crystal grain;

The metal wire sections that forms a plurality of patternings and forms described a plurality of weld pads on this active face of the end of metal wire sections of described a plurality of patternings and each this crystal grain to electrically connect on this second sacrifice layer and this first sacrifice layer;

Form a patterned protective layer, with the part that covers described a plurality of pattern metal line segments and expose the metal wire sections that is positioned at the described a plurality of patternings of part on this second sacrifice layer; And

Cut this packaging body, to form a plurality of crystal grain of independently finishing encapsulation separately.

2. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, wherein removes this second sacrifice layer and this first sacrifice layer and comprises with the step that formation has this step structure of height:

Form a patterning photoresist layer on this second sacrifice layer;

With this first sacrifice layer is etch stop layer, is etched with to remove this second sacrifice layer of part; And

With this second sacrifice layer of part is shielding, removes this first sacrifice layer of part and forms described a plurality of hole in the described a plurality of weld pads place with respect to this active face of each this crystal grain, to expose each this weld pad.

3. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, wherein removes this first sacrifice layer and this second sacrifice layer is to be formed by a wet etch process.

4. the method for packing that crystal grain as claimed in claim 1 reconfigures is characterized in that, the metal wire sections that wherein forms described a plurality of patternings comprises:

Form a metal level to cover on this second sacrifice layer and this first sacrifice layer;

The photoresist layer that forms a patterning is on this metal level;

Remove this metal level of part, to be retained in the metal level on this second sacrifice layer and the described weld pad, to form the metal wire sections of described patterning.

5. the method for packing that crystal grain as claimed in claim 4 reconfigures is characterized in that, wherein removing this metal level of part is to utilize Wet-type etching.

6. the encapsulating structure that crystal grain reconfigures is characterized in that, comprising:

One crystal grain disposes a plurality of weld pads on the one active face, wherein this each this crystal grain is that the known normally functioning crystal grain and a back side of each this crystal grain all dispose a plurality of registration marks;

One packaging body coats five faces of this crystal grain and exposes this active face of this crystal grain;

The formed projection cube structure of a plurality of macromolecular materials is disposed at array way on the active face of this crystal grain;

The metal wire sections of a plurality of patternings, a plurality of weld pads on the active face of one end and this crystal grain electrically connect, and its other end then extends in the fan-out mode and is covered on each this projection cube structure; And

One protective layer in order to metal wire sections and the part packaging body that covers described patterning, and exposes this projection and is covered in the metal wire sections of the described a plurality of patternings on this projection cube structure.

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