CN101452428A - DMA data-transmission method and system - Google Patents
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Abstract
The invention discloses a data transmission method for DMA, which comprises the following steps: S1, a CPU configures data transmission information of the DMA inside the CPU; S2, the DMA transmits first segment of data to a target address from a source address, and the length of the transmitted data satisfies an initial data length; S3, a transmission fragment number is updated, whether the updated transmission fragment number satisfies an end threshold is judged, the CPU is notified of the finishing of data transmission if the updated transmission fragment number satisfies the end threshold, and the following steps are executed if not so; S4, a source address and a target address of the transmission of next segment of data and the transmission length of the data are calculated; and S5, the transmission of the next segment of data is finished, and the operation returns to the step S3.
Description
Technical field
The present invention relates to the technical field of DMA data transmission, relate in particular to data transmission method and the system of a kind of DMA.
Background technology
DMA (Direct Memory Access, direct memory access (DMA)) is meant at storer and I/O equipment room and directly transmits data, is a kind of mode of being finished input-output operation fully by hardware.When adopting dma mode transmission data, need a special device to coordinate the data transmission of Peripheral Interface and internal storage, this special device is called dma controller, is called for short DMAC.DMAC takes over control to bus fully from CPU, and exchanges data is without CPU, and directly carries out between internal memory and I/O equipment.In the inside of DMAC, several registers are arranged: address register, deposit the memory unit address of depositing the IO data when DMA transmits; Byte counter is deposited the byte number of DMA transmission; Control register is deposited the DMA transmission mode of being set by CPU, control command etc.; Status register: deposit the current state of DMAC, comprise having or not the DMA request, whether finish etc.
At present, dma controller mostly adopts following dual mode to carry out data transmission:
1) stops the CPU access memory: when external unit requires to transmit a batch data, send out a signal by dma controller and give CPU, after CPU obtains this signal, abdicate the control of bus, at this moment dma controller just obtains bus control right, afterwards, begins to carry out data and transmits; Behind a collection of Data Transfer Done, dma controller notice CPU can use internal memory, and bus control right is given back CPU.
2) cycle stealing: when I/O equipment does not have the DMA request, the CPU follow procedure requires access memory, in case I/O equipment has the DMA request, then dma controller is diverted one or several cpu cycle, but the process that the cycle stealing each time of I/O equipment all has the application bus control right, sets up bus control right and give back bus control right.
As can be seen, because DMA is arranged on the outside of CPU, thereby DMA need finish replacing of access control power through bus with CPU.And bus width is limited, when the needs data quantity transmitted is very big, CPU just must wait for that the long time just can recapture bus control right, and the program of handling as CPU takies resource more for a long time, and DMA needs also to wait for that the long period could obtain bus control right.And, in order to guarantee CPU and DMA effective transmission at the enterprising line data of bus, no matter adopt the transmission mode of above-mentioned which kind of DMA, DMA need give back bus control right to CPU after data transmission is finished, for example, and with interrupt mode notice CPU, in this case, if DMA need transmit multiple segment data, then can after every segment data end of transmission (EOT), all notify CPU, thereby greatly influence the work efficiency of CPU.
In a word, those skilled in the art press for the data transmission method that develops a kind of DMA, to reduce taking of bus bandwidth, improve the data transmission efficiency of DMA and and guarantee the work efficiency of CPU.
Summary of the invention
Technical matters to be solved by this invention provides data transmission method and the system of a kind of DMA, can reduce taking of bus bandwidth, improves the data transmission efficiency of DMA and and guarantees the work efficiency of CPU.
In order to address the above problem, the invention discloses the data transmission method of a kind of DMA, may further comprise the steps:
Step S1, CPU dispose the data transmission information of its inner DMA, described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Step S2, DMA transfer to destination address with described first segment data from described source address, and the first segment data length of described transmission meets described data initial length;
Step S3, the described span line numerical value of renewal, and judge whether the span line numerical value after upgrading satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out following steps;
The source address of step S4, described first segment data of foundation and source address incrementation parameter calculate the source address of one piece of data transmission down, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data transmission down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Step S5, finish down the transmission of one piece of data, and return step S3.
Preferably, the step of described renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value increases progressively.
Preferably, the step of described renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value successively decreases.
Further, described source address is CPU external source address, and described destination address is CPU internal object address.
Preferably, the mode of described notice CPU is an interrupt mode.
The invention also discloses the data transmission system of a kind of DMA, comprise CPU and the DMA that is arranged at CPU inside, described CPU comprises:
Dispensing unit is used to dispose the data transmission information of the inner DMA of CPU, and described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Described DMA comprises:
First transmission unit is used for DMA described first segment data is transferred to destination address from described source address, and the first segment data length of described transmission meets described data initial length;
The count update unit is used to upgrade described span line numerical value, and triggers judging unit;
Judging unit is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
Computing unit, be used for calculating the source address of one piece of data down according to the source address and the source address incrementation parameter of described first segment data, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Second transmission unit is used to finish down the transmission of one piece of data, and calls the count update unit.
Preferably, the step of described count update unit renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value increases progressively.
Preferably, the step of described count update unit renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value successively decreases.
Further, described source address is CPU external source address, and described destination address is CPU internal object address.
The invention discloses a kind of DMA, described DMA is arranged at CPU inside, comprising:
Source address register is used to preserve the source address of first segment data of configuration;
Target address register is used to preserve the destination address of first segment data of configuration;
The source address increment register is used to preserve the source address incrementation parameter of configuration;
The destination address increment register is used to preserve the destination address incrementation parameter of configuration;
The tcp seq number register is used to preserve the span line numerical value of configuration;
The data length register is used to preserve the data initial length;
The data length increment register is used to preserve the data length incrementation parameter of configuration;
Described DMA also comprises:
First transmission unit is used for DMA described first segment data is transferred to destination address from described source address, and the first segment data length of described transmission meets described data initial length;
The count update unit is used to upgrade described span line numerical value, and triggers judging unit;
Judging unit is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
Computing unit, be used for calculating the source address of one piece of data down according to the source address and the source address incrementation parameter of described first segment data, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Second transmission unit is used to finish down the transmission of one piece of data, and calls the count update unit.
Compared with prior art, the present invention has the following advantages:
Dma controller of the present invention is located at CPU inside, like this when carrying out data transmission, just finished replacing of access control power by the connection line of CPU inside between dma controller and the CPU, thereby saved bus resource, reduced taking of bus bandwidth, transmit required parameter and realized that in the inner unit such as count update, judgement, calculating that increase of dma controller dma controller interrupts the transmission that a time CPU just finishes multiple segment data by CPU configuration dma controller in addition, improved the work efficiency of CPU and DMA.
Description of drawings
Fig. 1 is the process flow diagram of the data transmission method embodiment of a kind of DMA of the present invention;
Fig. 2 is the structured flowchart of the data transmission system embodiment of a kind of DMA of the present invention;
Fig. 3 system shown in Figure 2 for the present invention uses carries out the process flow diagram of DMA data transmission embodiment;
Fig. 4 is provided with the structured flowchart of the CPU embodiment of DMA for a kind of inside of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following example is used to illustrate the present invention, but is not used for limiting the scope of the invention.
The core idea of the embodiment of the invention is: the dma controller that will be provided with unit such as transmission, calculating renewal, judgement, calculating is arranged on CPU inside, realized that CPU does not alternately need just can finish by bus with the access right of dma controller, saved bus resource, and realized that dma controller interrupts the transmission that a time CPU just finishes multiple segment data, has improved the work efficiency of CPU and DMA.
With reference to figure 1, show the flow chart of steps of the data transmission method embodiment 1 of a kind of DMA of the present invention, specifically can may further comprise the steps:
Step 101, CPU dispose the data transmission information of its inner DMA, described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Dma controller is arranged on CPU inside, when carrying out data transmission, has just finished replacing of access control power by the connection line of CPU inside between dma controller and the CPU, saved bus resource.
Step 102, DMA transfer to destination address with described first segment data from described source address, and the first segment data length of described transmission meets described data initial length;
The destination address that the source address of first segment data and first segment data will be transferred to is known, CPU disposes the source address parameter of first segment data according to the source address of first section transmission data storage, and CPU disposes the destination address of first segment data according to the destination address of storage first segment data that sets in advance; The information of data initial length is known, is disposed to DMA by CPU.
DMA extracts this segment data from the source address of first segment data, and this segment data is transferred to the destination address of first segment data of CPU configuration.According to data initial length information, DMA extracts from the source address of first segment data and meets the data of data initial length information, and the data transmission that meets the data initial length that will extract is to the destination address of first segment data of CPU configuration.
Step 103, the described span line numerical value of renewal, and judge whether the span line numerical value after upgrading satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out following steps;
The mode of notice cpu data end of transmission can adopt the mode of interruption.
Before carrying out data transmission, the data hop count of transmission also is known, and the span line numerical value according to known hop count CPU disposes its inner DMA disposes span line numerical value according to known hop count.
In another preferred embodiment of the present invention, the step of upgrading span line numerical value comprises: transmitted one piece of data, span line numerical value increases progressively.Supposing to finish threshold value is 10, and span line numerical value is 5, and every transmission finishes one piece of data, and span line numerical value adds 1, promptly transmitted first segment data after, span line numerical value is 6, after having passed 5 segment datas, span line numerical value is 10.
In another preferred embodiment of the present invention, the step of upgrading span line numerical value comprises: transmitted one piece of data, span line numerical value successively decreases.Supposing to finish threshold value is 0, and span line numerical value is 5, and every transmission finishes one piece of data, and span line numerical value subtracts 1, promptly transmitted first segment data after, span line numerical value is 4, after having passed 5 segment datas, span line numerical value is 0.
Certainly, it all is feasible that those skilled in the art adopt any count update mode of the prior art, for example, adopts the method for counter, just repeats no more here.
The source address of step 104, described first segment data of foundation and source address incrementation parameter calculate the source address of one piece of data transmission down, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data transmission down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Can be according to formula: the source address+source address incrementation parameter of source address=the preceding paragraph data transmission of following one piece of data transmission obtains down the source address that one piece of data transmits; Just
Source address+source address the incrementation parameter of the source address of second segment data transmission=first segment data transmission; In like manner,
Destination address+source address the incrementation parameter of the destination address of second segment data transmission=first segment data transmission,
Can be according to formula: the transmission length+data length incrementation parameter of transmission length=the preceding paragraph data of following one piece of data obtains down the transmission length of one piece of data;
The transmission length of second segment data=data initial length+data length incrementation parameter.
Step 105, finish down the transmission of one piece of data, and return step 103.
In the whole data transmission, described source address is the external source address of CPU, and described destination address is CPU internal object address.
For making those skilled in the art understand the present invention better, below further specify embodiment of the invention DMA data transmission procedure by a concrete example.
At first, the source address that CPU disposes inner DMA is 0 x 10000000, destination address is 0 x 00000000, the source address increment is 0 x 10000000, the destination address increment is 0x00001000, and the data initial length is 0 x, 100,256 bytes, the data length increment is 0 x 100, and span line numerical value is 0x2.
Promptly for the first time during data transmission, transmit one piece of data from CPU external address 0 x 10000000 to home address 0 x 00000000, data length is 0x100,256 bytes; Behind the DTD, span line numerical value subtracts 1 for the first time, and span line numerical value is updated to 0 x 1; For the second time transmit one piece of data from CPU external address 0 x 20000000 to home address 0 x 00001000 during data transmission, data length is 0 x 200,512 bytes, behind the DTD, span line numerical value subtracts 1, and at this moment span line numerical value is updated to 0, satisfies the end threshold value that presets, by interrupt mode notice CPU, the CPU handling interrupt is learnt and has been finished dma operation one time.
With reference to figure 2, show the structured flowchart of the data transmission system embodiment of a kind of DMA of the present invention, specifically can comprise with lower unit:
Described CPU comprises: CPU dispensing unit 201, be used to dispose the data transmission information of the inner DMA of CPU, described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Described DMA comprises:
Judging unit 204 is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
In another preferred embodiment of the present invention, the step that described count update unit 203 upgrades span line numerical value comprises: transmitted one piece of data, span line numerical value increases progressively.Supposing to finish threshold value is 10, and span line numerical value is 5, and every transmission finishes one piece of data, and span line numerical value adds 1, promptly transmitted first segment data after, span line numerical value is 6, after having passed 5 segment datas, span line numerical value is 10.
In another preferred embodiment of the present invention, the step that described count update unit 203 upgrades span line numerical value comprises: transmitted one piece of data, span line numerical value successively decreases.Supposing to finish threshold value is 0, and span line numerical value is 5, and every transmission finishes one piece of data, and span line numerical value subtracts 1, promptly transmitted first segment data after, span line numerical value is 4, after having passed 5 segment datas, span line numerical value is 0.
With reference to figure 3, show and use the process flow diagram that preferred embodiment shown in Figure 2 carries out the DMA data transmission, specifically can may further comprise the steps:
The dispensing unit of step 301, described CPU, the data transmission information of the inner DMA of configuration CPU, described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
First transmission unit of step 302, described DMA transfers to destination address with described first segment data from described source address, and the first segment data length of described transmission meets described data initial length;
Whether the span line numerical value after step 304, judgment unit judges are upgraded satisfies is finished threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
With reference to figure 4, show the structured flowchart that a kind of inside is provided with the CPU embodiment of DMA, specifically can comprise:
Source address increment register 403 is used to preserve the source address incrementation parameter of configuration;
Destination address increment register 404 is used to preserve the destination address incrementation parameter of configuration;
Tcp seq number register 405 is used to preserve the span line numerical value of configuration;
Data length increment register 412 is used to preserve the data length incrementation parameter of configuration;
Described DMA also comprises:
Judging unit 408 is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit 409;
Below by an object lesson process of using DMA of the present invention and carrying out data transmission is described: the source address that CPU disposes inner DMA is 0 x 10000000 and is stored in source address register 401, the configuration destination address is 0 x 00000000 and is stored in target address register 402, the source address increment is that 0 x 10000000 is stored in source address increment register 403, the destination address increment is that 0 x 00001000 is stored in destination address increment register 404, the data initial length is 0 x 100,256 bytes, be stored in data length register 411, the data length increment is 0 x 100, be stored in data length increment register 412, data transmission segment numerical value is that 0 x 2 is stored in the tcp seq number register.
Promptly for the first time during data transmission, from source address register 401, access source address 0 x 10000000, take out the data of storage according to this source address, from target address register 402, access destination address 0 x 00000000, from data length register 411, access data initial length information, transmit one piece of data from source address 0 x 10000000 to destination address 0 x 00000000, data length is 0x100,256 bytes; For the first time behind the DTD, the span line numerical value in the tcp seq number register 405 subtracts 1 and be updated to 0x1; For the second time during data transmission according to accessing stored parameters in source address register 401, source address increment register 403 and the data length increment register 412, can pass through formula according to these parameters:
Following one piece of data source address=the preceding paragraph data source address+source address incrementation parameter obtains second section transmission data source address.
According to stored parameters in target address register 402 and the destination address increment register 404, can pass through formula according to these parameters:
Destination address+destination address the incrementation parameter of following one piece of data destination address=the preceding paragraph data obtains second section destination address of transmitting data.
According to data length register 411 be stored in stored parameters in the data length increment register 412, can pass through formula according to these parameters
Transmission length+data length the incrementation parameter of transmission length=the preceding paragraph data of following one piece of data obtains down the transmission length of one piece of data.
Transmit one piece of data from source address 0 x 20000000 of CPU second hop count to destination address 0 x 00001000 of second segment data, data length is 0 x 200,512 bytes, behind the DTD, span line numerical value in the tcp seq number register 405 subtracts 1 and be updated to 0, satisfy default end threshold value, by interrupt mode notice CPU, the CPU handling interrupt is learnt and has been finished dma operation one time.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.For system embodiment, because it is similar substantially to method embodiment, so description is fairly simple, relevant part gets final product referring to the part explanation of method embodiment.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1, the data transmission method of a kind of DMA is characterized in that, described DMA is the DMA that is arranged at CPU inside, and described method comprises:
Step S1, CPU dispose the data transmission information of its inner DMA, described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Step S2, DMA transfer to destination address with described first segment data from described source address, and the first segment data length of described transmission meets described data initial length;
Step S3, the described span line numerical value of renewal, and judge whether the span line numerical value after upgrading satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out following steps;
The source address of step S4, described first segment data of foundation and source address incrementation parameter calculate the source address of one piece of data transmission down, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data transmission down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Step S5, finish down the transmission of one piece of data, and return step S3.
2, method according to claim 1 is characterized in that: the step of described renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value increases progressively.
3, method according to claim 1 is characterized in that: the step of described renewal span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value successively decreases.
4, according to described each method of claim 1-3, it is characterized in that: described source address is CPU external source address, and described destination address is CPU internal object address.
5, method according to claim 4 is characterized in that, the mode of described notice CPU is an interrupt mode.
6, the data transmission system of a kind of DMA is characterized in that, comprises CPU and the DMA that is arranged at CPU inside, and described CPU comprises:
Dispensing unit is used to dispose the data transmission information of the inner DMA of CPU, and described data transmission information comprises the source address and the destination address of first segment data, source address incrementation parameter and destination address incrementation parameter, data initial length and data length incrementation parameter, and, span line numerical value;
Described DMA comprises:
First transmission unit is used for DMA described first segment data is transferred to destination address from described source address, and the first segment data length of described transmission meets described data initial length;
The count update unit is used to upgrade described span line numerical value, and triggers judging unit;
Judging unit is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
Computing unit, be used for calculating the source address of one piece of data down according to the source address and the source address incrementation parameter of described first segment data, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Second transmission unit is used to finish down the transmission of one piece of data, and calls the count update unit.
7, system according to claim 6 is characterized in that: the step that described count update unit upgrades span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value increases progressively.
8, system according to claim 6 is characterized in that: the step that described count update unit upgrades span line numerical value comprises: every transmission finishes one piece of data, and span line numerical value successively decreases.
9, according to described each system of claim 6-8, it is characterized in that: described source address is CPU external source address, and described destination address is CPU internal object address.
10, a kind of DMA is characterized in that, described DMA is arranged at CPU inside, comprising:
Source address register is used to preserve the source address of first segment data of configuration;
Target address register is used to preserve the destination address of first segment data of configuration;
The source address increment register is used to preserve the source address incrementation parameter of configuration;
The destination address increment register is used to preserve the destination address incrementation parameter of configuration;
The tcp seq number register is used to preserve the span line numerical value of configuration;
The data length register is used to preserve the data initial length;
The data length increment register is used to preserve the data length incrementation parameter of configuration;
Described DMA also comprises:
First transmission unit is used for DMA described first segment data is transferred to destination address from described source address, and the first segment data length of described transmission meets described data initial length;
The count update unit is used to upgrade described span line numerical value, and triggers judging unit;
Judging unit is used to judge whether the span line numerical value after the renewal satisfies the end threshold value; If then notify the cpu data end of transmission; If not, then carry out computing unit;
Computing unit, be used for calculating the source address of one piece of data down according to the source address and the source address incrementation parameter of described first segment data, and, destination address and destination address incrementation parameter according to described first segment data calculate the destination address of one piece of data down, calculate the transmission length of one piece of data down according to described data initial length and data length incrementation parameter;
Second transmission unit is used to finish down the transmission of one piece of data, and calls the count update unit.
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| CNA2008102266659A CN101452428A (en) | 2008-11-19 | 2008-11-19 | DMA data-transmission method and system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102857735A (en) * | 2011-06-30 | 2013-01-02 | 上海无线电设备研究所 | Real-time video synchronous automatic detection and recovery method |
| CN103119573A (en) * | 2010-09-21 | 2013-05-22 | 三菱电机株式会社 | DMA controller and data readout device |
| CN110166430A (en) * | 2019-04-15 | 2019-08-23 | 珠海全志科技股份有限公司 | A kind of method and system optimizing MTP protocol strategy |
| CN113868039A (en) * | 2021-08-30 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | A test method, device and related equipment |
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2008
- 2008-11-19 CN CNA2008102266659A patent/CN101452428A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103119573A (en) * | 2010-09-21 | 2013-05-22 | 三菱电机株式会社 | DMA controller and data readout device |
| CN102857735A (en) * | 2011-06-30 | 2013-01-02 | 上海无线电设备研究所 | Real-time video synchronous automatic detection and recovery method |
| CN110166430A (en) * | 2019-04-15 | 2019-08-23 | 珠海全志科技股份有限公司 | A kind of method and system optimizing MTP protocol strategy |
| CN110166430B (en) * | 2019-04-15 | 2021-11-30 | 珠海全志科技股份有限公司 | Method and system for optimizing MTP (multiple time transfer protocol) strategy |
| CN113868039A (en) * | 2021-08-30 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | A test method, device and related equipment |
| CN113868039B (en) * | 2021-08-30 | 2024-02-09 | 浪潮电子信息产业股份有限公司 | Test method, device and related equipment |
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