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CN101447861B - IEEE 1588 time synchronization system and implementation method thereof - Google Patents

IEEE 1588 time synchronization system and implementation method thereof Download PDF

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CN101447861B
CN101447861B CN 200810187676 CN200810187676A CN101447861B CN 101447861 B CN101447861 B CN 101447861B CN 200810187676 CN200810187676 CN 200810187676 CN 200810187676 A CN200810187676 A CN 200810187676A CN 101447861 B CN101447861 B CN 101447861B
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time
message
module
timestamp
sync
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CN101447861A (en
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刘立华
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ZTE Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

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Abstract

本发明公开了一种IEEE 1588时间同步系统，通过增设时间戳处理模块，使用该模块内的时间戳报文收发子模块、时间戳报文解析子模块、时间戳报文生成子模块、本地时间记录寄存器及RTC校正/时间读写模块，并结合交换机(Swtich)模块、物理层芯片(PHY)模块以及实时时钟(RTC)模块等外围部件形成一个硬件系统，使用中通过采用主、从同步的一对一、或一对多的方式，能够实现IEEE 1588v2协议所要求的高精度时间同步。本发明还公开了一种IEEE 1588时间同步的实现方法，通过对主、从设备的时间信息进行实时处理，能够实现所述时间同步系统的功能。采用本发明对高速以太网建设有积极的促进作用。

Figure 200810187676

The invention discloses an IEEE 1588 time synchronization system. By adding a time stamp processing module, the time stamp message sending and receiving submodule, the time stamp message parsing submodule, the time stamp message generating submodule and the local time are used in the module. Record registers and RTC correction/time reading and writing modules, combined with peripheral components such as switch (Swtich) modules, physical layer chip (PHY) modules, and real-time clock (RTC) modules to form a hardware system. One-to-one or one-to-many methods can realize the high-precision time synchronization required by the IEEE 1588v2 protocol. The invention also discloses a method for implementing IEEE 1588 time synchronization, which can realize the function of the time synchronization system by processing the time information of the master and slave devices in real time. The adoption of the present invention has a positive effect on promoting the construction of the high-speed Ethernet.

Figure 200810187676

Description

IEEE 1588 clock synchronization systems and its implementation
Technical field
The present invention relates to the Time synchronization technique of Institute of Electrical and Electronics Engineers (IEEE) 1588 agreements, relate in particular to a kind of multiport IEEE 1588 clock synchronization systems and its implementation.
Background technology
The full name of IEEE 1588 is the precision interval clock synchronous protocol of networking measurement and control system, is commonly referred to chronometer time agreement (PTP, Precision Time Protocol).The purpose of the general IEEE of use 1588 chronometer time agreements is the time synchronized that keep in Ethernet between the different node.Also need the time synchronized of widely applying requirement very accurate in factory automation, measurement and communication, this can exceed the scope that the solution in the standard software mode can provide usually.
The IEEE1588 standard has stipulated to be dispersed in clock synchronization to a high accuracy of independent operating on the separate node in measurement and the control system and the agreement of accuracy.And these clocks mutual communication in a communication network, by this basic format, this agreement will form tree-like management, makes master and slave synchronized relation of intrasystem these clock generating.Here, described Frequency Synchronization and two notions of time synchronized of comprising synchronously.So-called Frequency Synchronization is that clock is synchronous, is meant on frequency between the signal or the phase place to keep certain strict particular kind of relationship, and occurs with same Mean Speed its corresponding significant instant, moves with identical speed to keep equipment all in the communication network.And there are two kinds of implications " time " described in the time synchronized: the moment and the time interval.The former be meant continuous passage time certain in a flash, the latter is meant the gaps between two moments are constantly.The operation of time synchronized is exactly according to the time adjusting device clock internal that receives and the moment.The principle of adjustment and control of time synchronized is similar to the principle of adjustment and control of clock to Frequency Synchronization, and it had not only been regulated and control the frequency of clock but also had regulated and control the phase place of clock, simultaneously with the phase place of clock with numeric representation, constantly promptly.Different with Frequency Synchronization is, time synchronized is accepted discrete temporal information, discontinuous adjusting device clock, and the adjusting of equipment clock phase-locked loop control is periodic.Time synchronized has two main functions: time service and punctual.Describe with popular words, time service is exactly " his-and-hers watches ".By irregular his-and-hers watches action, with this locality moment and etalon time Phase synchronization; Punctual is exactly above-mentioned Frequency Synchronization, guarantees in the gap of his-and-hers watches, local constantly not too big with the etalon time deviation.The purpose of time synchronized will be delivered to each control point exactly with time reference exactly, transmit not difficult, and difficult precision at the passing time that requires to reach.
Current, communication network and professional IPization, packetizing are trends of the times, but service network especially mobile service is still essential to synchronous requirement, and the transmission network after the packetizing still needs to possess the synchronisation requirement that perfect clock synchronization ability satisfies related service.Under the application scenes of radio communication, business is IPization, no longer needs the Time Division Multiplexing interface, but still needs clock, needs this moment a kind of sequential grouping (ToP, Timing over Packet) technology to realize.Described ToP technology is timing information to be put into the grouping bag according to certain encapsulation format transmit, and in receiving terminal recovered clock from bag, evades the damage that brings in the transport process by algorithm and encapsulation format as far as possible.IEEE 1588 standards promptly are one of more common ToP technology, can satisfy time and phase locked requirement preferably.This standard can reach very high precision through improving, this has corresponding introduction in the IEEE 1588v2 version that is about to issue, from present development, adopting the IEEE 1588v2 technology time of carrying out to transmit based on Packet Transport Network is the solution developing direction of setting up time synchronization network from now on.
IEEE 1588 principal and subordinate's clock synchronization principles are as follows: master clock regularly sends the Sync message, sends the actual transmitting time T1 that the Followup message is announced last message subsequently, from the T2 time of advent of clock record Sync message; Send Delay Req message from clock constantly at T3, the master clock recorded message T4 time of advent, and it is sent to from clock by response message Delay Resp.According to T1, T2, T3 and T4, can calculate the time delay of link between two clocks and the time deviation of two clocks, adjust in view of the above from the output of time of clock, thereby realize master clock and from the time synchronized of clock.IEEE 1588v2 can realize Frequency Synchronization and time synchronized simultaneously, wherein time synchronized can reach the submicrosecond class precision, consensus standardization is better, can support the different manufacturers butt joint,, require the two-way time delay of intermediate line link to be consistent owing to come passing time information by joining day label in message, the inconsistent meeting of time delay causes the phase measurement deviation, thereby time precision is affected, and in addition, time precision also can be subjected to the influence of factors such as packet loss.And use software to realize the setting of IEEE 1588 protocol stacks, also can cause protocol stack to handle the shake of time-delay because of the multitask of software processes flow process and operating system, therefore, if adopt software mode to realize that IEEE 1588v2 agreement will be difficult to reach the synchronous requirement of transmission split-second precision of expection.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of hardware multiport IEEE 1588 clock synchronization systems and its implementation, to satisfy the desired synchronization accuracy of IEEE 1588v2.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of IEEE1588 clock synchronization system comprises switch (Switch) module, phy chip (PHY) module, CPU administration module and real-time clock (RTC) module; This system also comprises the timestamp processing module; Wherein:
The Switch module is used for after the IEEE1588 timestamp packet filtering from a plurality of PHY module ports, and the time of delivery (TOD) is stabbed processing module;
The PHY module is used to discern described IEEE1588 message, and to provide the timestamp message to receive index signal and timestamp message transmission index signal to described timestamp processing module;
The CPU administration module is used to manage described clock synchronization system;
The RTC module is used to provide local clock, comes dynamic calibration RTC according to receiving synchronised clock; And
The timestamp processing module is used to realize the parsing to IEEE 1588 timestamp messages, obtains lock in time, to proofread and correct the local real-time clock of RTC; Also be used to produce IEEE 1588 messages and send to other equipment.
Described Switch module has a plurality of ports, the corresponding described PHY module of each port.
Comprise further in the described timestamp processing module that timestamp packet sending and receiving submodule, timestamp packet parsing submodule, timestamp message generate submodule, local zone time record register and RTC correction/time module for reading and writing; Wherein:
Timestamp packet sending and receiving submodule is used for receiving or transmitting time is stabbed message, and the logging timestamp message receives or the correct time of transmission;
Timestamp packet parsing submodule is used for stabbing type according to the record judgement time of timestamp message content and local zone time record register;
The timestamp message generates submodule, is used for rise time stamp message, and inserts Sync, FllowUp, Delay Request or Delay Response message classification logotype in described timestamp message;
Local zone time record register is used to write down the time that transmission/time of reception stabs message; Also be used for receiving simultaneously and handle and many timestamp message is received index signal and the timestamp message sends index signal, and read and write in the RTC correction/time under the effect of the orthochronous that submodule provided, provide required temporal information to timestamp message generation submodule and timestamp packet parsing submodule;
RTC correction/time module for reading and writing is used to calibrate local RTC or reads, revises local zone time.
Further comprise the cpu i/f submodule in the described timestamp processing module, be used for described timestamp processing module being carried out read-write operation by the CPU administration module.
A kind of method that adopts the described IEEE1588 clock synchronization system of claim 1 to realize time synchronized is separately positioned on this clock synchronization system in main equipment and the slave unit, and this method comprises:
A, main equipment send Sync message and FollowUp message to slave unit in turn by self built-in timestamp processing module, and described slave unit receives this Sync message and the recorder time is Ts2, receives this FollowUp message and write down main equipment and send Sync message time T m2;
B, described slave unit send the DelayRequest message to described main equipment, and the record transmitting time is Ts3; Described main equipment receives and resolves this DelayRequest message, and replys the DelayResponse message to described slave unit, and it is Tm3 that described slave unit record main equipment receives the DelayRequest message time; Calculate circuit time delay value Delay according to respective formula then;
C, described slave unit continue to receive Sync message and the FollowUp message that described main equipment is sent in turn, and described slave unit receives this Sync message and the recorder time is Ts4, receives this FollowUp message and write down main equipment that to send the Sync message time be Tm4; Utilize time delay value Delay and calculate time offset Offset between slave unit and the main equipment, utilize described Offset value that the local zone time of slave unit is proofreaied and correct then according to default time offset computing formula.
Further comprise after the described step C:
D, described slave unit continue to receive Sync message and the FollowUp message that described main equipment is sent in turn, described slave unit receives this Sync message and the recorder time is Ts5, receives this FollowUp message and write down main equipment that to send the Sync message time be Tm5, utilizes formula then:
Offset＝Ts5-Tm5-Delay；
Whether the value of verifying this Offset is zero, as if Offset=0, then finishes the time synchronism calibration process of main equipment, slave unit; Otherwise, return execution in step A.
Wherein, the timestamp processing module of the described main equipment of steps A to the process of slave unit transmission Sync message and FollowUp message is in turn:
The timestamp message of described main equipment generates submodule and produces the IEEE1588 message that carries the Sync message, by timestamp packet sending and receiving submodule to the Switch module forwards, described Switch module is transmitted to the PHY module with the Sync message by exchange interaction, and sends the described IEEE1588 message that contains the Sync message by described PHY module to slave unit; Simultaneously, stab message to the local zone time record register transmitting time of described main equipment when described IEEE1588 message passes through the PHY module and send index signal, write down the transmitting time of Sync message by the local zone time record register of described main equipment, described timestamp message generates submodule and reads the temporal information that described local zone time record register and RTC correction/time reads and writes submodule, and in timestamp message generation submodule, generate the FollowUp message, the Sync transmitting time is put among the FollowUp, by timestamp packet sending and receiving submodule, Switch module and PHY module send to slave unit, and write down the time that sends Follow Up message.
The process that the described slave unit of steps A receives described Sync message and the described FollowUp message of reception respectively is:
After described slave unit receives the IEEE1588 message that has Sync message or FollowUp message classification by the PHY module, described PHY module is stabbed message to the local zone time record register transmitting time of self and is received index signal, writes down the time of advent that register writes down corresponding message by described local zone time; And give the timestamp processing module by the Switch module forwards with described Sync message or FollowUp message, be transmitted to timestamp packet parsing submodule after receiving by timestamp packet sending and receiving submodule and judge the message classification and carry out record.
The formula of the described computational scheme time delay value of step B Delay is:
Delay＝((Ts2-Tm2)+(Ts3-Tm3))/2；
Wherein, Ts3 is described slave unit sends a transmitting time from the DelayRequest message to main equipment;
Tm3 is the time that described main equipment receives the DelayResponse message.
The computing formula of the described default time offset Offset of step C is:
Offset＝Ts4-Tm4-Delay；
Wherein, Ts4 is that slave unit receives the time of reception that main equipment is sent the Sync message subsequently;
Tm4 is the local zone time that main equipment sends the Sync message;
Delay is the circuit time delay value between main equipment, the slave unit.
The described process of utilizing described Offset value that the local zone time of slave unit is proofreaied and correct of step C is:
Described slave unit time for reading is stabbed the time offset Offset in the packet parsing submodule, reads and writes submodule adjustment PLL module by the RTC corrections/time, is adjusted into time of local RTC consistent with the main equipment Time Synchronization Network.
IEEE 1588 clock synchronization systems provided by the present invention and its implementation have the following advantages:
The present invention is by adopting the timestamp processing module of example, in hardware, and use timestamp packet sending and receiving submodule, timestamp packet parsing submodule, timestamp message in this module to generate submodule, local zone time record register and RTC correction/time module for reading and writing the Sync in the IEEE1588 message, FllowUp, DelayRequest and Delay Response message are handled in real time, thereby guaranteed to adopt the split-second precision between the equipment of this clock synchronization system synchronous.
In addition, pass through to adopt the Switch module in the system of the present invention, be used a plurality of PHY modules, and the real-time of assurance parallel processing, can realize providing the mode of IEEE1588 message a plurality of equipment to be carried out the correction of time synchronized with multiport, thereby, the Ethernet construction that adopts the IEEE1588 agreement there is positive facilitation.
Description of drawings
Fig. 1 is the structural representation of IEEE 1588 clock synchronization systems in the embodiment of the invention;
Fig. 2 is the measurement and the complete synchronous procurement process schematic diagram of existing IEEE 1588 protocol transmission time delays;
Fig. 3 is the implementation procedure schematic diagram of embodiment of the invention IEEE 1588 method for synchronizing time.
Embodiment
Below in conjunction with accompanying drawing and embodiments of the invention method of the present invention is described in further detail.
Fig. 1 is the structural representation of IEEE 1588 clock synchronization systems in the embodiment of the invention, as shown in Figure 1, this clock synchronization system comprises timestamp processing module 10, switch (Swtich) module 11, central processing unit (CPU) administration module 12, physical chip (PHY) module 13 and real-time clock (RTC) module 14; Wherein, also comprise cpu i/f submodule 100 in the described timestamp processing module 10, timestamp packet sending and receiving submodule 101, timestamp packet parsing submodule 102, the timestamp message generates submodule 103, local zone time record register 104 and RTC correction/time module for reading and writing 105.
Timestamp processing module 10 is used to realize the parsing to IEEE 1588 timestamp messages, obtains lock in time, to proofread and correct the local real-time clock of RTC; Also be used to send IEEE 1588 messages and offer other equipment.Wherein:
Cpu i/f submodule 100 is used for carrying out read-write operation by 12 pairs of described timestamp processing modules 10 of CPU administration module.
Timestamp packet sending and receiving submodule 101 is used for receiving or transmitting time is stabbed message.
Timestamp packet parsing submodule 102 is used for stabbing type according to the record judgement time of timestamp message content and local zone time record register; Here, described timestamp has Delay Response message, other are used to finish the types such as message of normal forwarding process.
The timestamp message generates submodule 103, is used for rise time stamp message, and inserts message classification logotypes such as Sync, FllowUp, Delay Request or Delay Response in described timestamp message;
Local zone time record register 104 is used to write down the time that PHY module transmission/time of reception stabs message; Described local zone time record register 104 can receive and handle many to timestamp message reception index signal and timestamp message transmission index signal simultaneously.And can proofread and correct at RTC/effect of the orthochronous that time read-write submodule 105 is provided under, generate submodule 103 and timestamp packet parsing submodule 102 provides required temporal information to the timestamp message.
RTC correction/time module for reading and writing 105 is used to calibrate local RTC or reads, revises local zone time.
Swtich module 11, be used for timestamp packet filtering with a plurality of ports after, the time of delivery (TOD) is stabbed processing module 10.
CPU administration module 12 is used to manage described clock synchronization system.
PHY module 13 is used to discern IEEE1588 timestamp message, offers timestamp processing module 10.Described PHY module 13 provides the timestamp message to receive index signal and timestamp message transmission index signal to described timestamp processing module 10, is specially: the PHY module sends index signal to the local zone time record register 104 transmitting times stamp message reception index signal or the timestamp message of described timestamp processing module 10.Here, transmission that described PHY module provides and reception index signal are to stab the correct time of message by the PHY module in order to allow the local zone time register record the time, time-delay between main equipment PHY module and the slave unit PHY module is only the time-delay that we will calculate, because this time-delay is a constant time lag, if calculating time-delay through the Switch module, that is just inaccurate.Described PHY module 13 can promptly can dispose N, N 〉=1 according to actual needs for single or multiple.
RTC module 14 is used to clock synchronization system that the synchronous time is provided.
The clock synchronization system of the embodiment of the invention at first obtains IEEE 1588 time message by PHY module 13, the local zone time that provides timestamp processing module message to arrive; Then IEEE 1588 time message are forwarded to the timestamp processing module by Swtich module 11, carry out message identification and the calculating of time, thereby obtain the high precision synchronous time.
Fig. 2 is the measurement and the complete synchronous procurement process schematic diagram of existing IEEE 1588 protocol transmission time delays, as shown in Figure 2, master clock (Master) and from there being circuit time delay (Line Delay) between the clock (Slave), Tm is the local zone time of Master, Ts is the local zone time of Slave.The current time of Master is 1070s when supposing initial state, and the current time of Slave is 1009s.According to IEEE 1588 agreements, the Master timed sending, as sending one subsynchronous (Sync) message every 2 seconds (can determine the time interval) according to actual conditions, send subsequently and follow the actual transmitting time Tmn that (Follow up) message is announced last message, by the Tsn time of advent of Slave record Sync message.As shown in Figure 2, Slave is at Ts3 forward delay interval request (Delay Request) constantly message, the time T m3 that the Master recorded message arrives, and it is sent to Slave by time-delay response (Delay Response) message, calculate circuit delay Delay=((Ts2-Tm2)+(Ts3-Tm3))/2=0+ (the 1082-1080)/2=1s between Master and the Slave; Slave calculates time offset Offset=Ts4-Tm4-Delay=1083-1083-1=-1 between Master and the Slave according to follow-up Follow up message, calculate time difference Adjust Time=Ts-Offset=Ts-(the 1)=1s that adjust according to time offset Offset then, in view of the above, in the moment that next time interval Follow up message arrives Slave is calibrated, making time offset is zero, be Offset=Ts5-Tm5-1=0, finish the time synchronized adjustment process of Master and Slave.
Fig. 3 is the implementation procedure schematic diagram of IEEE 1588 method for synchronizing time in the embodiment of the invention, as shown in Figure 3, supposes that opposite equip. is a main equipment, and slave unit is a slave unit.Respectively be provided with a timestamp processing module 10 in main equipment and the slave unit.Be that example describes with what send out the IEEE1588 message mutually between main equipment and slave unit to slave unit time synchronized adjustment process below, this method comprises:
Step 301: main equipment sends the IEEE1588 message by Ethernet to slave unit.
Here, the structure of the timestamp processing module 10 in the timestamp processing module 10 in the main equipment and the slave unit, effect are identical, and only hypothesis is a standard with time of main equipment in the present embodiment.Described main equipment sends submodule 101 by the timestamp message and sends the IEEE1588 message to the Switch11 module, is transmitted to the PHY module 13 of self again after the exchange by Switch11, sends to the PHY module 13 of slave unit then by Ethernet.
The above IEEE1588 message is generated by the timestamp message of main equipment and generates submodule 103 is read and write the temporal information of submodule 105 in conjunction with the RTC correction/time of main equipment after, and the timestamp message generation submodule 103 by main equipment sends timestamp packet sending and receiving submodule 101 to, sends to Switch module 11 again.
Step 302: slave unit receives described IEEE1588 message by PHY module 13, and transmits to the local zone time record register 104 of Switch module 11 and timestamp processing module 10, distinguishes execution in step 303 and step 304 then.
Step 303: be transmitted to the timestamp packet sending and receiving submodule 101 of timestamp processing module 10 behind the described IEEE1588 message of described Switch module 11 receptions by exchange, execution in step 305 then.
Step 304: described local zone time record register 104 is received behind the described IEEE1588 message the described message of record time of advent, and execution in step 306 then.
Step 305: resolve described IEEE1588 message by timestamp packet parsing submodule 102, judge whether message, if then execution in step 306 into Sync; Otherwise, execution in step 307.
Step 306: the time by local zone time record register 104 record Sync messages and IEEE1588 message are arrived, be designated as Ts (n), wherein, n 〉=1.
Here, all timestamp messages arrive the time that all will write down arrival or send in the local zone time register when PHY module or process PHY module send; When using certain time, from described local zone time record register, obtain and described message time information corresponding again when described message elapsed time stamp analyzing sub-module and according to the needs that message is resolved.
Step 307: judge further whether described IEEE1588 message is Follow Up message, if then execution in step 308; Otherwise, execution in step 309.
Step 308: obtain the time that main equipment sends the Sync message, Tm (n) by analytic message.
Step 309: judge whether described IEEE1588 message is the Response message, if then execution in step 310; Otherwise, this packet loss is finished this timestamp message receiving course.
Step 310: by analytic message, obtain the time that main equipment receives Delay Request message, be designated as Tm (n+1).
More than be sent to the basic process of slave unit from main equipment for the IEEE1588 message, can insert different identification informations in the described IEEE1588 message, message classification with difference IEEE1588, for example, insert Sync message, FollowUp message, Delay Request message or Delay Response message.Finishing the process of proofreading and correct lock in time with the IEEE1588 message interaction below is that example is described respectively:
1, main equipment sends the process of Sync message and Follow Up message to slave unit:
The timestamp message of main equipment generates submodule 103 and produces the IEEE1588 message that carries the Sync message, transmit to Switch module 11 by timestamp packet sending and receiving submodule 101, described Switch module 11 is transmitted to PHY module 13 with the Sync message by exchange interaction, sends the IEEE1588 message that contains the Sync message to slave unit by described PHY module 13; Simultaneously, described IEEE1588 message need stab message to local zone time record register 104 transmitting times of described main equipment during by PHY module 13 and send index signal, write down the transmitting time Tm2 of Sync messages by the local zone time record register 104 of described main equipment, the timestamp message generates submodule 103 and reads the temporal information that described local zone time record register 104 and RTC correction/time reads and writes submodule 105, and in timestamp message generation submodule 103, in the IEEE1588 message, add Follow Up message classification, by timestamp packet sending and receiving submodule 101, Switch module 11 reaches by PHY module 13 and sends to slave unit.
Then, receive this Sync message and the recorder time is Ts2, receives this FollowUp message and write down main equipment that to send the Sync message time be Tm2 by described slave unit, after described slave unit receives the message that has Sync message or FollowUp message by PHY module 13, described PHY module 13 is stabbed message to local zone time record register 104 transmitting times of self and is received index signal, by the time of advent of described local zone time record register 104 these messages of record; And described Sync message or FollowUp message be transmitted to timestamp processing module 10 by Switch module 11, be transmitted to timestamp packet parsing submodule 102 after receiving by timestamp packet sending and receiving submodule 101 and judge the message classification and carry out record.
2, slave unit sends the process of Delay Request message to main equipment:
When slave unit carries the IEEE1588 message of Delay Request message to the main equipment transmission, interocclusal record register 104 is write down the transmitting time Ts3 of described Delay Request message when local, and sending to Switch module 11 by timestamp packet sending and receiving submodule 101, the PHY module 13 that sends to slave unit after handling through exchange sends described Delay Request message to main equipment.
3, main equipment is replied the process of Delay Response message to slave unit:
After the PHY module 13 of main equipment receives the Delay Request message of slave unit, stab the message index signal by PHY module 13 to local zone time record register 104 transmitting times, the Tm3 time of advent by described local zone time record register 104 record Delay Request messages, and instruction time stab message and generate submodule 103 and in the IEEE1588 message, adds Delay Response message, pass through timestamp packet sending and receiving submodule 101, Switch module 11 and PHY module 13 again and send to slave unit.
4, slave unit receives the process of the Delay Response message that main equipment returns:
After slave unit receives the Delay Response message that main equipment returns, according to formula:
Delay＝((Ts2-Tm2)+(Ts3-Tm3))/2(1)
Calculate the circuit time delay between main equipment, the slave unit, and this time delay value is stored in the timestamp packet parsing submodule 102 of slave unit.
5, slave unit is according to adjusting the process of local zone time with the time offset of main equipment:
At this moment, the timestamp message that slave unit continues to receive by main equipment generates Sync message and the Follow Up message that submodule 103 sends, the parsing of the timestamp packet parsing submodule 102 by slave unit, the time that record Sync message arrives is Ts4 and writes down the time T m4 that main equipment sends the Sync message; The timestamp packet parsing submodule 102 of slave unit is according to formula:
Offset＝Ts4-Tm4-Delay(2)
Calculate the time offset from the master clock of clock and main equipment of slave unit, it is the time difference, described slave unit can utilize this correcting local time time difference at this moment, be that described slave unit time for reading is stabbed the time offset Offset in the packet parsing submodule 102, read and write submodule 105 by the RTC correction/time and adjust the PLL module, time of local RTC is adjusted into consistent with the main equipment Time Synchronization Network, thereby obtain the high-precise synchronization time that the real-time clock with main equipment is consistent.
After slave unit has been proofreaied and correct local zone time, also need a process that acknowledging time is synchronous, that is:
Slave unit continue to receive the Sync message and the Follow Up message that send to timestamp message generation submodule 103 of autonomous device, the parsing of the timestamp packet parsing submodule 102 by slave unit, the time that record Sync message arrives is Ts5, and the record main equipment sends the time T m5 of Sync message; Whether the value of checking Offset=Ts5-Tm5-Delay is zero, if Offset=0, then the time synchronized of main equipment, slave unit is verified; If empirical tests Offset ≠ 0, time synchronism calibration procedure failure this time then need re-execute the time synchronism calibration process of this method.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims (9)

1.一种IEEE 1588时间同步系统，包括交换机(Switch)模块、物理芯片(PHY)模块、CPU管理模块以及实时时钟(RTC)模块；其特征在于，该系统还包括时间戳处理模块；其中：1. A kind of IEEE 1588 time synchronization system, comprises switch (Switch) module, physical chip (PHY) module, CPU management module and real-time clock (RTC) module; It is characterized in that, this system also includes time stamp processing module; Wherein: Switch模块，用于将来自多个PHY模块端口的IEEE 1588时间戳报文过滤后，送到时间戳处理模块；The Switch module is used to filter the IEEE 1588 timestamp messages from multiple PHY module ports and send them to the timestamp processing module; PHY模块，用于识别所述IEEE 1588时间戳报文，并向所述时间戳处理模块提供时间戳报文接收指示信号及时间戳报文发送指示信号；The PHY module is used to identify the IEEE 1588 time stamp message, and provides the time stamp message receiving indication signal and the time stamp message sending indication signal to the time stamp processing module; CPU管理模块，用于管理所述时间同步系统；A CPU management module, configured to manage the time synchronization system; RTC模块，用于提供本地时钟；以及RTC module for providing a local clock; and 时间戳处理模块，用于实现对IEEE 1588时间戳报文的解析，获得同步时间，以校正RTC本地实时时钟；还用于产生IEEE 1588时间戳报文、并向其他设备发送。The timestamp processing module is used to analyze the IEEE 1588 timestamp message and obtain the synchronization time to correct the RTC local real-time clock; it is also used to generate the IEEE 1588 timestamp message and send it to other devices. 2.根据权利要求1所述的时间同步系统，其特征在于，所述Switch模块具有多个端口，每个端口对应一个所述PHY模块。2. The time synchronization system according to claim 1, wherein the Switch module has a plurality of ports, and each port corresponds to one of the PHY modules. 3.根据权利要求1所述的时间同步系统，其特征在于，所述时间戳处理模块中进一步包括时间戳报文收发子模块、时间戳报文解析子模块、时间戳报文生成子模块、本地时间记录寄存器以及RTC校正/时间读写模块；其中：3. The time synchronization system according to claim 1, wherein the timestamp processing module further comprises a timestamp message sending and receiving submodule, a timestamp message parsing submodule, a timestamp message generating submodule, Local time recording register and RTC correction/time reading and writing module; where: 时间戳报文收发子模块，用于接收或发送时间戳报文，并记录时间戳报文接收或发送的准确时间；The time stamp message sending and receiving sub-module is used to receive or send the time stamp message, and record the accurate time when the time stamp message is received or sent; 时间戳报文解析子模块，用于根据时间戳报文内容及本地时间记录寄存器的记录判断时间戳类型；The timestamp message analysis sub-module is used to judge the timestamp type according to the timestamp message content and the records of the local time record register; 时间戳报文生成子模块，用于生成时间戳报文，并在所述时间戳报文中填入Sync、FllowUp、Delay Request或Delay Response报文类别标识；Timestamp message generation submodule is used to generate timestamp message, and fills in Sync, FlowUp, Delay Request or Delay Response message category identification in described timestamp message; 本地时间记录寄存器，用于记录发送/接收时间戳报文的时间；还用于同时接收并处理多对时间戳报文接收指示信号和时间戳报文发送指示信号，并在RTC校正/时间读写子模块所提供的正确时间的作用下，向时间戳报文生成子模块和时间戳报文解析子模块提供所需的时间信息；The local time recording register is used to record the time of sending/receiving timestamp messages; it is also used to receive and process multiple pairs of timestamp message receiving indication signals and timestamp message sending indication signals at the same time, and is used for RTC correction/time reading Under the action of the correct time provided by the write sub-module, provide the required time information to the timestamp message generation sub-module and the timestamp message analysis sub-module; RTC校正/时间读写模块，用于校准本地RTC或读取、修改本地时间。RTC correction/time reading and writing module, used to calibrate the local RTC or read and modify the local time. 4.根据权利要求1或3所述的时间同步系统，其特征在于，所述时间戳处理模块中进一步包括CPU接口子模块，用于通过CPU管理模块对所述时间戳处理模块进行读写操作。4. The time synchronization system according to claim 1 or 3, wherein the timestamp processing module further comprises a CPU interface submodule for performing read and write operations on the timestamp processing module through a CPU management module . 5.一种采用权利要求1所述IEEE 1588时间同步系统实现时间同步的方法，将该时间同步系统分别设置在主设备和从设备中，其特征在于，该方法包括：5. a method adopting the described IEEE 1588 time synchronization system of claim 1 to realize time synchronization, the time synchronization system is respectively arranged in master equipment and slave equipment, it is characterized in that, the method comprises: A、主设备通过自身内置的时间戳处理模块顺次向从设备发送Sync报文和FollowUp报文，所述从设备接收该Sync报文并记录接收时间为Ts2、接收该FollowUp报文并记录主设备发送Sync报文时间Tm2；A, master device sends Sync message and FollowUp message to slave device sequentially through its own built-in time stamp processing module, and described slave device receives this Sync message and records receiving time as Ts2, receives this FollowUp message and records master The device sends the Sync message time Tm2; B、所述从设备向所述主设备发送DelayRequest报文，记录发送时间为Ts3；所述主设备接收并解析该DelayRequest报文，并向所述从设备回复DelayResponse报文，所述从设备记录主设备接收DelayRequest报文时间为Tm3；然后依据公式Delay＝((Ts2-Tm2)+(Ts3-Tm3))/2计算出主设备、从设备之间的线路时延值Delay；B. The slave device sends a DelayRequest message to the master device, and the record sending time is Ts3; the master device receives and parses the DelayRequest message, and replies a DelayResponse message to the slave device, and the slave device records The time for the master device to receive the DelayRequest message is Tm3; then calculate the line delay value Delay between the master device and the slave device according to the formula Delay=((Ts2-Tm2)+(Ts3-Tm3))/2; C、所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文，所述从设备接收该Sync报文并记录接收时间为Ts4、接收该FollowUp报文并记录主设备发送Sync报文的本地时间为Tm4；利用时延值Delay并按照预设的时间偏移量计算公式Offset＝Ts4-Tm4-Delay算出从设备与主设备之间的时间偏移量Offset，然后利用所述Offset值对从设备的本地时间进行校正。C, the slave device continues to receive the Sync message and the FollowUp message sent by the master device in sequence, the slave device receives the Sync message and records the receiving time as Ts4, receives the FollowUp message and records the master device The local time for sending the Sync message is Tm4; use the delay value Delay and calculate the time offset Offset between the slave device and the master device according to the preset time offset calculation formula Offset=Ts4-Tm4-Delay, and then use The Offset value corrects the local time of the slave device. 6.根据权利要求5所述的实现时间同步的方法，其特征在于，所述步骤C之后进一步包括：6. The method for realizing time synchronization according to claim 5, characterized in that, after the step C, further comprising: D、所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文，所述从设备接收该Sync报文并记录接收时间为Ts5、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm5，然后利用公式：D, the slave device continues to receive the Sync message and the FollowUp message sent by the master device in sequence, the slave device receives the Sync message and records the receiving time as Ts5, receives the FollowUp message and records the master device The time to send the Sync message is Tm5, and then use the formula: Offset＝Ts5-Tm5-Delay；Offset=Ts5-Tm5-Delay; 验证该Offset的值是否为零，若Offset＝0，则结束主设备、从设备的时间同步校正过程；否则，返回执行步骤A。Verify whether the value of the Offset is zero, if Offset=0, end the time synchronization correction process of the master device and the slave device; otherwise, return to step A. 7.根据权利要求5所述的实现时间同步的方法，其特征在于，步骤A所述主设备的时间戳处理模块顺次向从设备发送Sync报文和FollowUp报文的过程为：7. the method for realizing time synchronization according to claim 5, is characterized in that, the process of the timestamp processing module of the master device described in step A sending Sync message and FollowUp message to slave device sequentially is: 所述主设备的时间戳报文生成子模块产生携带有Sync报文的IEEE 1588时间戳报文，通过时间戳报文收发子模块向Switch模块转发，所述Switch模块将Sync报文通过交换作用转发给PHY模块，并由所述PHY模块向从设备发送所述含有Sync报文的IEEE 1588时间戳报文；同时，所述IEEE 1588时间戳报文通过PHY模块时向所述主设备的本地时间记录寄存器发送时间戳报文发送指示信号，由所述主设备的本地时间记录寄存器记录Sync报文的发送时间，所述时间戳报文生成子模块读取所述本地时间记录寄存器和RTC校正/时间读写子模块的时间信息，并在时间戳报文生成子模块中生成FollowUp报文，把Sync发送时间放到FollowUp中，通过时间戳报文收发子模块、Switch模块及PHY模块向从设备发送，并记下发送FollowUp报文的时间。The timestamp message generating submodule of the master device generates an IEEE 1588 timestamp message carrying a Sync message, and forwards it to the Switch module through the timestamp message sending and receiving submodule, and the Switch module passes the Sync message through the switching function Forward to the PHY module, and send the IEEE 1588 timestamp message containing the Sync message to the slave device by the PHY module; at the same time, when the IEEE 1588 timestamp message passes through the PHY module, the local The time record register sends a time stamp message sending indication signal, the sending time of the Sync message is recorded by the local time record register of the master device, and the time stamp message generating submodule reads the local time record register and RTC correction /Time read and write the time information of the sub-module, and generate a FollowUp message in the timestamp message generation sub-module, put the Sync sending time in the FollowUp, send and receive the sub-module, the Switch module and the PHY module through the timestamp message to the slave The device sends and records the time when the FollowUp packet is sent. 8.根据权利要求5所述的实现时间同步的方法，其特征在于，步骤A所述从设备分别接收所述Sync报文和接收所述FollowUp报文的过程为：8. the method for realizing time synchronization according to claim 5, is characterized in that, the described process of receiving described Sync message and receiving described FollowUp message from equipment described in step A is: 所述从设备通过PHY模块接收到带有Sync报文或FollowUp报文类别的IEEE 1588时间戳报文后，所述PHY模块向自身的本地时间记录寄存器发送时间戳报文接收指示信号，由所述本地时间记录寄存器记录相应报文的到达时间；并将所述Sync报文或FollowUp报文通过Switch模块转发给时间戳处理模块，通过时间戳报文收发子模块接收后转发给时间戳报文解析子模块判断出报文类别进行记录。After the slave device receives the IEEE 1588 time stamp message with the Sync message or the FollowUp message category through the PHY module, the PHY module sends the time stamp message reception indication signal to its local time record register, and is determined by the Described local time recording register records the arrival time of corresponding message; And described Sync message or FollowUp message is forwarded to timestamp processing module by Switch module, forwards to timestamp message after receiving by timestamp message sending and receiving sub-module The parsing sub-module determines the type of the message and records it. 9.根据权利要求5所述的实现时间同步的方法，其特征在于，步骤C所述利用所述Offset值对从设备的本地时间进行校正的过程为：9. The method for realizing time synchronization according to claim 5, characterized in that, the process of utilizing the Offset value described in step C to correct the local time of the slave device is: 所述从设备读取时间戳报文解析子模块中的时间偏移量Offset，通过RTC校正/时间读写子模块调整PLL模块，将本地RTC的时间调整为与主设备时间同步网络一致。The slave device reads the time offset Offset in the time stamp message analysis submodule, adjusts the PLL module through the RTC correction/time reading and writing submodule, and adjusts the time of the local RTC to be consistent with the time synchronization network of the master device.
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