CN101447514A - Metal oxide semiconductor field effect transistor - Google Patents
Metal oxide semiconductor field effect transistor Download PDFInfo
- Publication number
- CN101447514A CN101447514A CNA2008102049695A CN200810204969A CN101447514A CN 101447514 A CN101447514 A CN 101447514A CN A2008102049695 A CNA2008102049695 A CN A2008102049695A CN 200810204969 A CN200810204969 A CN 200810204969A CN 101447514 A CN101447514 A CN 101447514A
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- Prior art keywords
- effect transistor
- field effect
- dielectric layer
- grid
- mos field
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- 230000005669 field effect Effects 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 3
- 150000004706 metal oxides Chemical class 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012212 insulator Substances 0.000 claims description 27
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a metal oxide semiconductor field effect transistor which comprises a semiconductor substrate, a grid insulation dielectric layer which is arranged on the surface of the semiconductor substrate, a grid which is piled on the grid insulation dielectric layer and a source electrode area and a drain electrode area which are arranged in the surface area of the semiconductor substrate at two sides of the grid and are separated by a channel region. A first part of the grid insulation dielectric layer is close to the drain electrode area, a second part thereof is close to the source electrode area, and the thickness of the first part is thicker than the thickness of the second part. The thickness of the second part near the source electrode area of the metal oxide semiconductor field effect transistor is thinner, thereby improving the control capacity of the grid on the channel, increasing saturation current, improving the drive capacity of the apparatus and also reducing the area of the apparatus. The thickness of the first part near the drain electrode area is thicker, thereby controlling leakage current caused by GIDL effect.
Description
Technical field
The present invention relates to a kind of semiconductor device, specifically, relate to a kind of mos field effect transistor.
Background technology
The applied environment of mos field effect transistor (MOSFET) is complicated day by day, need under different voltage conditions, carry out work, such as in memory peripheral circuit, usually need a MOSFET under " shutoff " state, to drain and bear a higher voltage (as 12V), and grid all only bears normal operating voltage (as 3.3V) with drain electrode when " unlatching " state.When applying a high voltage in drain electrode, because gate-induced drain leaks (gate-induced-drain leakage GIDL) effect, drain electrode can produce very big leakage current, causes device power consumption to rise, and influences the working life of device.
The thickness of gate insulator dielectric layer has direct relation near the size of the leakage current that the GIDL effect causes and the drain electrode, and the thickness of gate insulator dielectric layer is big more near the drain electrode, and the leakage current that the GIDL effect causes is more little.Therefore, in order to solve leakage problem, existing method is all used thicker gate insulator dielectric layer to whole M OSFET.But this method has shortcoming clearly, and after promptly the gate insulator medium thickness of MOSFET became greatly, grid was to the control ability variation of raceway groove, and threshold voltage raises, and causes the saturation current of device to reduce.In order to reach the driving force that needs, device needs very big area.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of mos field effect transistor is provided, under different voltage conditions, improves grid to the raceway groove control ability, overcome the leakage problem that exists in the mos field effect transistor simultaneously.
For solving the problems of the technologies described above, the invention provides a kind of mos field effect transistor, comprising:
Semiconductor substrate;
The gate insulator dielectric layer is positioned on the described semiconductor substrate surface;
Grid is superimposed upon described gate insulator dielectric layer upper surface;
Source region and drain region are arranged in the semiconductor substrate surface zone of described grid both sides, and described source region and drain region are separated by channel region;
The first of described gate insulator dielectric layer is near described drain region, and second portion is near described source region, and the thickness of first is greater than the thickness of second portion.
Further, described mos field effect transistor also comprises grid curb wall, and described grid curb wall is positioned at described grid both sides.
Further, between described source region and the described channel region, be provided with lightly mixed drain area (LDD) between described drain region and the described channel region.
Further, the lightly mixed drain area that forms between the lightly mixed drain area that forms between described source region and the described channel region and described drain region and the described channel region has different doping conditions.
Further, the thickness range of the first of described gate insulator dielectric layer is 3～200 nanometers.
Further, the thickness range of the second portion of described gate insulator dielectric layer is 1～50 nanometer.
Further, described grid is N type or the P type polysilicon bar utmost point or metal gates.
Further, described gate insulator dielectric layer is the oxide of silicon, the nitrogen oxide of silicon, the dielectric layer of HfO2 or other high-ks.
Compare with traditional mos field effect transistor, the thickness of its gate insulator dielectric layer first of mos field effect transistor that the present invention proposes is greater than the thickness of second portion, the benefit of this structure is: one: near the second portion thinner thickness of source region, improved the control ability of grid to raceway groove, increase saturation current, improve the driving force of device, also reduce device area.Two: the first's thickness near the drain region is thicker, suppresses the leakage current that the GIDL effect causes.
Description of drawings
Fig. 1 is the structural representation of mos field effect transistor in the embodiment of the invention;
Fig. 2 is the schematic diagram that mos field effect transistor is opened in the embodiment of the invention;
Fig. 3 is the schematic diagram that mos field effect transistor turn-offs in the embodiment of the invention.
Embodiment
For clearer understanding technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
See also Fig. 1, Fig. 1 is the MOSFET structure schematic diagram in the embodiment of the invention, this mos field effect transistor comprises Semiconductor substrate 1, described Semiconductor substrate 1 surface is provided with gate insulator dielectric layer 2, described gate insulator dielectric layer 2 is the oxide of silicon, the nitrogen oxide of silicon, the dielectric layer of HfO2 or other high-ks, in the present embodiment, described gate insulator dielectric layer 2 is the oxide silicon dioxide of silicon.
Described gate insulator dielectric layer 2 is made up of two parts, and first 20 is near described drain regions 6, and second portion 21 is near described source regions 5, and the thickness of first 20 is greater than the thickness of second portion 21.First 20 and the described gate insulator dielectric layer 2 of second portion 21 one-body molded common formations, wherein, first's 20 selectable thickness ranges are 1～50 nanometer, and second portion 21 selectable thickness ranges are 3～200 nanometers, and length range is 0.02～1 micron.
Because described first 20 is different with the thickness of second portion 21, near the thinner thickness of the second portion 20 of source region 5, improve the control ability of 3 pairs of channel regions of described grid, threshold voltage reduces, increase the saturation current of device, improved driving force device.Under the condition of the identical driving force of maintenance, the required chip area of device is also reduced.
Referring to shown in Figure 2, Fig. 2 is the schematic diagram that mos field effect transistor is opened in the embodiment of the invention.Mos field effect transistor in the present embodiment is applied in connects word line in the flush memory device, when memory cell being carried out " reading " operation, in the source region 5, to apply voltage respectively be 0V, 3.3V, 3.3V for drain region 6, grid 3, can between raceway groove, form electric current, finish " reading " operation.Simultaneously,, improved the driving force of device, also improved device operation speed, improved the performance of device greatly owing to the thickness attenuation.
Because the leakage current that causes of GIDL effect is only relevant with near the thickness of the gate insulator dielectric layer 2 in drain region, thickness that promptly should the zone is big more, the leakage current that the GIDL effect causes is just more little, therefore, in the present embodiment, first 20 near described drain region 6 is thicker, has well overcome the leakage current that the GIDL effect causes.
Referring to shown in Figure 3, Fig. 3 is the schematic diagram that mos field effect transistor turn-offs in the embodiment of the invention.When memory cell being carried out " wiping " operation, the drain electrode of the mos field effect transistor in the present embodiment need connect word line.The grid of the mos field effect transistor in the present embodiment and voltage that source electrode applies are 0V in this case, and transistor is " shutoff " state.But because " wiping " action need high voltage, drain electrode need be born the high pressure of 12V.Because near the thickness of the gate insulator dielectric layer 21 the drain electrode is thicker, can suppress the leakage current that the GIDL effect causes, thereby reduce the power consumption of circuit, and it is breakdown to prevent to drain.
This gate insulator dielectric layer first 20 structure different with the thickness of second portion 21 improved the performance of device greatly, can work under different voltage conditions, also avoided increasing extra circuit or device, simplified the design of circuit.
Between described source region 5 and the described channel region, be provided with lightly mixed drain area 7 (LDD) between described drain region 6 and the described raceway groove, the lightly mixed drain area 8 that forms between the lightly mixed drain area 7 that forms between described source region 5 and the described channel region and described drain region 6 and the described channel region has different doping conditions.In actual production process, can impose according to the use needs of device different doping contents, different ionic type, implant energy or arbitrarily wherein various combination form different lightly mixed drain areas.In the present embodiment, lightly mixed drain area 7 uses heavier doping content to reduce the series resistance that source region 5 and lightly mixed drain area 7 form, and improves transistorized saturation current; Lightly mixed drain area 8 uses lighter doping content to improve the puncture voltage of drain region 6.
This LDD structure can reduce the drain terminal maximum field of device effectively, has effectively suppressed hot carrier's effect, thereby can slow down the degeneration of device, prolongs the useful life of device.
More than show and described basic principle of the present invention, principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (8)
1. mos field effect transistor comprises:
Semiconductor substrate;
The gate insulator dielectric layer is positioned on the described semiconductor substrate surface;
Grid is superimposed upon described gate insulator dielectric layer upper surface;
Source region and drain region are arranged in the semiconductor substrate surface zone of described grid both sides, and described source region and drain region are separated by channel region;
It is characterized in that: the first of described gate insulator dielectric layer is near described drain region, and second portion is near described source region, and the thickness of first is greater than the thickness of second portion.
2. mos field effect transistor as claimed in claim 1 is characterized in that: described mos field effect transistor also comprises grid curb wall, and described grid curb wall is positioned at described grid both sides.
3. mos field effect transistor as claimed in claim 1 or 2 is characterized in that: between described source region and the described channel region, be provided with lightly mixed drain area between described drain region and the described channel region.
4. mos field effect transistor as claimed in claim 3 is characterized in that: the lightly mixed drain area that forms between the lightly mixed drain area that forms between described source region and the described channel region and described drain region and the described channel region has different doping conditions.
5. mos field effect transistor as claimed in claim 1 is characterized in that: the thickness range of the first of described gate insulator dielectric layer is 3～200 nanometers.
6. mos field effect transistor as claimed in claim 1 is characterized in that: the thickness range of the second portion of described gate insulator dielectric layer is 1～50 nanometer.
7. mos field effect transistor as claimed in claim 1 is characterized in that: described grid is N type or the P type polysilicon bar utmost point or metal gates.
8. mos field effect transistor as claimed in claim 1 is characterized in that: described gate insulator dielectric layer is the oxide of silicon, the nitrogen oxide of silicon, the dielectric layer of HfO2 or other high-ks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102049695A CN101447514B (en) | 2008-12-30 | 2008-12-30 | Metal oxide semiconductor field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102049695A CN101447514B (en) | 2008-12-30 | 2008-12-30 | Metal oxide semiconductor field effect transistor |
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| CN101447514A true CN101447514A (en) | 2009-06-03 |
| CN101447514B CN101447514B (en) | 2012-06-20 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610525A (en) * | 2012-03-22 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing leakage of gate-induced drain electrode of semiconductor device |
| CN111627992A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN111627993A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Gate structure and method of making the same |
| CN116153972A (en) * | 2023-04-18 | 2023-05-23 | 合肥晶合集成电路股份有限公司 | A kind of semiconductor device and its manufacturing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164537A (en) * | 2000-11-29 | 2002-06-07 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| US6506642B1 (en) * | 2001-12-19 | 2003-01-14 | Advanced Micro Devices, Inc. | Removable spacer technique |
| US7138691B2 (en) * | 2004-01-22 | 2006-11-21 | International Business Machines Corporation | Selective nitridation of gate oxides |
| US7011980B1 (en) * | 2005-05-09 | 2006-03-14 | International Business Machines Corporation | Method and structures for measuring gate tunneling leakage parameters of field effect transistors |
-
2008
- 2008-12-30 CN CN2008102049695A patent/CN101447514B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610525A (en) * | 2012-03-22 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing leakage of gate-induced drain electrode of semiconductor device |
| CN111627992A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
| CN111627993A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Gate structure and method of making the same |
| CN116153972A (en) * | 2023-04-18 | 2023-05-23 | 合肥晶合集成电路股份有限公司 | A kind of semiconductor device and its manufacturing method |
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| Publication number | Publication date |
|---|---|
| CN101447514B (en) | 2012-06-20 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |