CN101443731A - Circular register arrays of a computer - Google Patents
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- CN101443731A CN101443731A CNA2007800171060A CN200780017106A CN101443731A CN 101443731 A CN101443731 A CN 101443731A CN A2007800171060 A CNA2007800171060 A CN A2007800171060A CN 200780017106 A CN200780017106 A CN 200780017106A CN 101443731 A CN101443731 A CN 101443731A
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- 238000003491 array Methods 0.000 title abstract description 11
- 238000000034 method Methods 0.000 claims description 16
- 230000002457 bidirectional effect Effects 0.000 claims description 10
- 230000003139 buffering effect Effects 0.000 claims description 4
- 230000003252 repetitive effect Effects 0.000 claims description 2
- 238000006073 displacement reaction Methods 0.000 claims 2
- 230000008676 import Effects 0.000 claims 1
- 238000004891 communication Methods 0.000 description 12
- 230000009977 dual effect Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
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- 125000004122 cyclic group Chemical group 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
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Abstract
A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.
Description
Technical field
The present invention relates to computing machine and computer processor field, relate more specifically to more effectively use the method and apparatus of the storehouse in the storehouse computer processor.
Background technology
The processor complexity that the processor complexity that stack machine provides provides far below complex instruction set computer (CISC) (CISC), and the overall system complexity that provides is lower than the overall system complexity that Reduced Instruction Set Computer (RICS) or CISC machine provide.They are not needing complicated compiler or high-speed cache control hardware to obtain to have realized under the high performance situation low processor complexity and overall system complexity.In numerous programmed environments, at given price, they have also reached competitive original (raw) performance and senior (superior) performance.Their initial successful applications are in real-time embedded controling environment, and they far surpass other design method in this field.Previous storehouse was retained in the program storage mostly, and the stack machine that upgrades to be storehouse kept independently memory chip or or even sheet on storage area.These stack machines provide subroutine call ability and remarkable Interrupt Process and the task performance of handoffs that is exceedingly fast.
Yet, do not have the hardware detection of stack overflow or underflow case.Stack overflow occur in do not have enough numbers register can with and the result also continue to be pressed in the storehouse, make when bottom register is rewritten.Stack underflow occurs in all register and becomes empty, and the pop-up a stack that continues has produced unintentionally or incorrect as a result the time.Some other stack processor are used stack pointer and memory management, thereby when stack pointer exceeds the memory range that distributes for this storehouse erroneous condition are carried out mark.The U.S. Patent No. 6,367,005 of authorizing people such as Zahir discloses a kind of register stack engine, and it preserves the enough registers of storage space for register stack, so that how available register to be provided under the situation of stack overflow.Under the situation of stack underflow, register stack engine also postpones microprocessor, can recover up to this engine till the register of proper number.
The U.S. Patent No. 6,219,685 of authorizing Story discloses a kind of method that operating result and threshold value are compared.Yet this method is not distinguished round down and becomes result of threshold value (may cause overflow unusual) and the result who just equals threshold value.Discern overflow or underflow case by the disclosed another kind of method read-write hardware flags of Story.Yet instruction must be carried out in proper order, and any instruction of following the register read/write all can not carry out before read/write operation is finished, and this makes process slow.
Use the storehouse in the storer, overflow or overflow and may rewrite stack item is perhaps used the stack item that is not intended to as a storehouse part.Need a kind of improving one's methods of overflow and underflow in the storehouse that reduce or eliminate.
Summary of the invention
The object of the present invention is to provide a kind of like this equipment and method, promptly wherein the data stack of dual stack processor and return stack are not by the array of stack pointer visit, but by the rigid line of special-purpose shift register access (hardwire) independently in the storer.
Another object of the present invention is to reduce or eliminate the overflow and the underflow of data stack or return stack.
A further object of the present invention is to minimize the electrical connection length between a stack register of two-way stack register, thereby minimizes required driver size and minimize buffering.
These and other objects are realized that by invention as described herein wherein traditional storehouse is replaced by the register array with the work of circulation repeat pattern.This circulation repeat pattern is realized with the bidirectional shift register of a plurality of single place shift registers of alternate mode electrical interconnection comprising of being associated by use.This configuration prevents to read from the outside of storehouse, and prevents to read dummy register value unintentionally.
The processor that above-described dual stack processor can be used as independent operating comes work, also can use together with some other the similar or different processors in the interconnected computer array.
Description of drawings
Fig. 1 is a block diagram of describing the general layout of storehouse computing machine;
Fig. 2 is according to data stack of the present invention;
Fig. 3 is the more detailed view of the single register of storehouse;
Fig. 4 is according to return stack of the present invention;
Fig. 5 is the skeleton diagram according to array of computers of the present invention; With
Fig. 6 is the more detailed view that the interconnect data bus of the details drawing of subclass of computing machine of Fig. 5 and Fig. 5 is shown.
Embodiment
The present invention is described with reference to the drawings, and in the accompanying drawings, identical Reference numeral is represented identical or similar element.Though invention has been described according to the pattern that is used to realize the object of the invention, those skilled in the art arrive cognition, under the situation that breaks away from the spirit or scope of the present invention, can realize variant in view of these enlighten.
As described herein and/or in the accompanying drawings shown in embodiments of the invention and variant thereof only provide by way of example, not delimit the scope of the invention.Owing to the invention is intended to adapt to multiple variant, unless therefore otherwise specify, independent aspects of the present invention and parts can be within remaining on the spirit and scope of desired invention in, be omitted or revise at various application.
Fig. 1 is the block diagram of the general layout of the dual stack computing machine 12 describing to use among the present invention.Computing machine 12 is generally has its oneself RAM 24 and the self contained computer of ROM 26.
Other basic elements of character of computing machine 12 are the decode logic section 36 that return stack 28, instruction area 30, ALU (ALU or processor) 32, the data stack 34 that comprises R register 29 and being used for decoded to instruction.Computing machine 12 is the dual stack computing machines with data stack 34 and the return stack 28 that separates.Those skilled in the art usually should be very familiar operation such as the computing machine in this example 12 based on the computing machine of storehouse.
In the embodiment of current description, instruction area 30 comprises several registers 40, and in the present example, register 40 comprises A-register 40a, B-register 40b and P register 40c.In the present example, A-register 40a is complete 18 bit registers, and B-register 40b and P register 40c are 9 bit registers.
The invention discloses a kind of storehouse computer processor, in this storehouse computer processor, data stack and return stack comprise register array, and this register array carries out work with cycle (cyclical), repetition or circulation (circular) pattern.As in the computing machine of numerous prior aries, data stack and return stack are not the array by the stack pointer visit in the storer.
Fig. 2 discloses the embodiment according to 18 bit data storehouses of the present invention.Two of the top registers are 18 T registers and 18 source registers in the data stack.The remainder of data stack comprises eight 18 additional hardware registers, and these hardware register numbering are S in this example
2To S
9Circular register arrays S
2-S
9Can under T register and the non-existent situation of source register, operate.Yet, the existence of source register and S at least
2-S
9The combination of register provides access circuit and optimum sequential faster, thereby the higher operating speed of circular register arrays is provided.In addition, source register serves as S
2-S
9Impact damper between the other parts of addressable register and processor system, this provides S
2-S
9Sequential independence between the other parts of register and processor system.
This embodiment also comprises bidirectional shift register, and this bidirectional shift register comprises a plurality of single place shift registers.The number of single place shift register equals to be positioned at the bottom stack register S under the source register
2To S
9Number.Each single place shift register is connected to its corresponding S
2To S
9Stack register, as shown in Figure 2.The single place shift register is with the alternate mode electrical interconnection, thereby makes the S of storehouse
2To S
9Register with as shown in Figure 2 by S
2→ S
4→ S
6→ S
8→ S
9→ S
7→ S
5→ S
3→ S
2Given sequential loop interconnection pattern comes work.The select progressively of bottom stack register is operated with the pattern that circulation repeats.The interconnection line of single place shift register is never crossed over more than three adjacent shift registers, and this has been avoided the bottom shift register is connected to the needs of the long line of top shift register.These short lines need less driver, and buffering has also obtained minimizing.Given embodiment uses eight additional stacks registers as circular register arrays.Yet, also can adopt other combination of the bottom register of using with the individual form of four multiple.
Fig. 2 also discloses and has made register S
2-S
9And the read bus and the write bus of T register and source register interconnection.Each single place shift register in the bidirectional shift register is connected to S
2-S
9Corresponding bottom stack register in the array wherein only has one to be high (read is one) in a period of time internal shift register, read all other positions is zero.When powering on, must carry out initialization to shift register, be set to one one and be set to all other positions of zero so that just comprise.In given example, shift register top bit points S
2Reading, and point to the adjunct register S of interconnection
4To write, write shown in the line as the void among Fig. 2.Although in order not cause the unnecessary of accompanying drawing obscured, other is write line and is not illustrated, and the remaining bit of single bit shift register similarly is connected to register S
2To S
4In corresponding register.
By register T, S and S
2To S
9Forming the degree of depth is the last-in first-out stack (ten cell deeppush down stack) of Unit ten.Because eight register-bit in bottom are in cyclic buffer, so hardware coiling (wrap), can overflow or underflow.Can not be desirably in to put in the last-in first-out stack that this degree of depth is Unit ten and all take out, but can extract forever always from more copies of last eight projects of storehouse bottom extraction more than ten projects and with them.As on the meaning of makeing mistakes, there is not underflow from it.If because program extraction value from storehouse always, eight meetings of bottom are read again and again, so this is the quickest way of duplicating the pattern of eight words (or four or two or).
Similarly, allow not have stack overflow on the meaning of storehouse with other anything stepping from stack pointer.Storehouse is limited, if the project more than ten is placed in the storehouse, then only has last ten meetings to be retained; Preceding ten later each storages all can rewrite S
2To S
9A register in the register.Do not need storehouse " initialization " to preset position, but only can state that by bringing into use this storehouse is empty from this storehouse position.
Fig. 3 is the extended view of each register in data stack or the return stack.Each 18 bit register comprises and is numbered 18 latchs of 0 to 17.The set of 18 input storbing gates (pass gate) (being numbered 0 to 17) is arranged, and each input storbing gate optionally is connected to write bus with corresponding latch in 18 latchs.Also have the set of 18 output storbing gates (being numbered 0 to 17), each output storbing gate optionally is connected to read bus with corresponding latch in 18 latchs.The input storbing gate is controlled by the inverting amplifier that is connected to input control line by the write control signal of asserting on input control line (Fig. 2 write line), and the output storbing gate is controlled by the inverting amplifier that is connected to output control line by the read control signal of asserting on output control line (Fig. 2 read line).
Fig. 4 discloses according to 18 return stacks of the present invention.Top register in the return stack is 18 R registers, eight additional 18 hardware registers be positioned at the R register below, and be numbered as R at this
1-R
8Eight register R of bottom
1-R
8Come work with alternate mode as the repetitive cycling array, be similar to above disclosed data stack.
Circular register arrays R
1-R
8Can under the non-existent situation of R register, operate.Yet, the existence of R register and R
1-R
8The combination of register provides access circuit and optimum sequential faster, thereby the higher operating speed of circular register arrays is provided.In addition, the R register serves as R
1-R
8Impact damper between the other parts of addressable register and processor system, this provides R
1-R
8Sequential independence between the other parts of register and processor system.
This embodiment also comprises bidirectional shift register, and this bidirectional shift register comprises a plurality of single place shift registers.The number of single place shift register equals to be positioned at the additional bottom register R under the R register
1To R
8Number.Each single place shift register is connected to its corresponding R
1To R
8Bottom stack register, as shown in Figure 4.The single place shift register of bidirectional shift register is with the alternate mode electrical interconnection, thereby makes the R of storehouse
1To R
8Register is with by R
1→ R
3→ R
5→ R
7→ R
8→ R
6→ R
4→ R
2→ R
1Given sequential loop interconnection pattern work, as shown in Figure 4.The select progressively of register is operated with the circulation repeat pattern.The interconnection line of register is never crossed over more than three adjacent single place shift registers, and this has been avoided the single place shift register with the bottom is connected to the needs of long line of the single place shift register at top.These short lines need less driver, and buffering has also obtained minimizing.Although in given embodiment, disclose eight additional return registers, also can in circular register arrays, adopt the combination of four multiple other bottom register.Read bus and write bus make register R
1-R
8Interconnection.Each of shift register bit register is connected to R
1-R
8The stack register of correspondence in the array.Only have one to be high (read is one) in each shift register, and to read be zero in all other positions.When powering on, must carry out initialization to shift register, be set to one one and be set to all other positions of zero so that just comprise.In given example, shift register top bit points or read R
1, and to the adjunct register R that interconnects
3Write.
In present invention, there is not hardware detection to stack overflow or underflow case.In general, the processor of prior art uses stack pointer and memory management etc., thereby when stack pointer exceeds the memory range that distributes for this storehouse erroneous condition is carried out mark.When storehouse is arranged in storer, perhaps in storer during by management, overflow or underflow may rewrite stack item or with stack item with the things outside making a plan.Yet, because bottom register of the present invention comes work as circular array, thus storehouse can overflow or under overflow stack region.On the contrary, circulating register will only be reeled around register array.Because storehouse has the limited degree of depth, the top that therefore anything is pressed into storehouse means that some things of bottom can be rewritten.In given embodiment, will be pressed into data stack more than ten project or will be pressed into return stack and must carry out having under the situation of following understanding: do like this and can cause the project of storehouse bottom to be rewritten more than nine project.
The responsibility of software is to follow the tracks of the number of the project on the storehouse, and does not attempt placing the more project of the project that can hold than corresponding storehouse.When makeing mistakes, hardware can not detect the rewriting of the project bottom the storehouse or carry out mark.Should be noted that software can some kinds modes utilize the advantage of the circular array of storehouse bottom.As an example, software can suppose simply that storehouse all is ' empty ' at any time.Because old project is when being pressed downward into the bottom, they can be dropped when storehouse is filled, therefore do not need from storehouse, to remove old project, and be empty so there is not things to need program to carry out initialization with the hypothesis storehouse.
Another available advantage is, reuses register items and need not to be written into again the project that these are used to reuse.Eight projects in bottom in these storehouses also can be read in the loop that utilizes storehouse coiling advantage, perhaps are read and write.After twice data stack reads, T and S will have the copy from two projects of the circular array of following eight stack registers.Reading after eight times, T and S can use storehouse to reel to be written into again with from the following identical value that reads once more again.Needn't duplicate these eight projects or number of times that these projects under the situation of storehouse that these projects are write back can order read from storehouse without limits.Because bottom register is just reeled, and if original intention be not the storehouse mistake, the round-robin algorithm can repeatedly be read from storehouse by the one group of parameter that can be on data stack or return stack repeats with eight, four or two unit.
Although described present invention at the data stack and the return stack of dual stack 18 bit processors in an embodiment, the processor of other figure place also can use with the present invention.
At single dual stack processor above-described circular register arrays has been described.Yet above-described circular register arrays also can use in the array of several self contained computer, for example uses in array of computers shown in Figure 5 10.Array of computers 10 has a plurality of (being 24 in the example that illustrates) computing machine 12 (in the example of array, being also referred to as " nuclear " or " node " sometimes).In the example that illustrates, all computing machines 12 all are positioned on the single circuit small pieces 14.According to one embodiment of present invention, each computing machine 12 computing machine of independent operating normally.Computing machine 12 is interconnected by many interconnective data buss 16.In this example, data bus 16 is two-way asynchronous high-speed parallel data bus lines, although the interconnection means that adopt other for this purpose also within the scope of the invention.
Computing machine 12e is the example that is not in a computing machine 12 on array 10 borders.That is to say that computing machine 12e has four mutually perpendicular adjacent computers 12a, 12b, 12c and 12d.To use a computer hereinafter this grouping of 12a-12e more goes through the communication of 12 in the computing machine of array 10.As the view finding of Fig. 5, such as the such inner computer 12 of computing machine 12e have four other can be by bus 16 computing machine 12 of direct communication with it.In the following discussion, the principle of being discussed will be applied to except only with the computing machine 12 that is positioned at array 10 borders of three other computing machine 12 direct communications, and only with the turning computing machine 12 of two other computing machine 12 direct communications outside all computing machines 12.
Fig. 6 is the more detailed view of the part among Fig. 5, and some computing machines 12 only are shown, and particularly particularly, comprises computing machine 12a-12e.The view of Fig. 6 also discloses every data bus 16 and all has the line of reading 18, writes line 20 and many (being 18 in the present example) data lines 22.Data line 22 is all positions of one 18 bit instruction word of while parallel transmission usually.
According to this creative method, computing machine 12 such as computing machine 12e can be read its one, two, three or whole four line 18 and be set to height, thereby prepares to receive data from corresponding one, two, three or whole four adjacent computers 12.Similarly, computing machine 12 also can be write its one, two, three or whole four line 20 and be set to height.
When one among adjacent computers 12a, 12b, 12c or the 12d line 20 of writing between himself and the computing machine 12e is set to when high, if computing machine 12e has read correspondence line 18 and has been set to height, word transfers to computing machine 12e from that computing machine 12a, 12b, 12c or 12d on the data line 22 that is associated so.Then, sending computer 12 is write line 20 with release, and receiving computer (being 12e in this example) will be write line 20 and read line 18 and all drag down.The action in back is to confirm to have received data to sending computer 12.
As shown in Figure 1, in this embodiment of the present invention, computing machine 12 has four communication port 38 that communicate with adjacent computers 12, as mentioned above.Communication port 38 is a three-state driver, has closed condition, accepting state (be used for drive signal and enter computing machine 12) and transmit status (drive signal is left computing machine 12).If in array (Fig. 5) inside such as the example of computing machine 12e, so at least for above-mentioned purpose, the one or more communication port in the communication port 38 can not be used at that certain computer certain computer 12.Yet, those communication port 38 of adjoining the circuit small pieces border can have additional circuit, these circuit or be designed in this computing machine 12 inside, perhaps design the outside of computing machine 12 but be associated, thereby make this class communication port 38 serve as exterior I/O port 39 (Fig. 5) with this computing machine.The example of this class exterior I/O port 39 includes but not limited to USB (USB (universal serial bus)) port, RS232 serial bus port, parallel communications port, modulus and/or digital-to-analog conversion port and a lot of other possible variants.In Fig. 5, described " border " computing machine 12f and the interface circuit 80 that is associated, wherein interface circuit 80 is used for communicating with external unit 82 by exterior I/O port 39.
Under the situation that does not change value of the present invention or scope, can carry out various modifications to the present invention.For example, although use specific computing machine 12 to describe the present invention here, many or all creative aspects are easy to adapt to other Computer Design, other array of computers etc.
Although mainly described the present invention here at the communication between the computing machine 12 in the array 10 on the single circuit small pieces 14, but identical principle can be used for method or is modified to be used to finish between other device communicating by letter, communicating by letter between for example communicating by letter between computing machine 12 and its private memory, or the computing machine in the array 10 12 and the external devices
Similarly, although disclose aspect of the present invention at dual stack processor here, also can or comprise and implement the present invention by single stack processor more than the processor of two storehouses.
Top all only are some examples of available embodiment of the present invention.Those skilled in the art will find out easily can be under the situation that does not break away from the spirit or scope of the present invention, carries out a large amount of other modification and changes.Correspondingly, disclosure herein content purpose is not intended to qualification, and appended claim should be interpreted as comprising four corner of the present invention.
Claims (42)
1, a kind of storehouse computing machine comprises:
Be used to store the storer of data and code;
The processor that is used for processing said data and code; With
Can be by a plurality of hardware registers of described processor as storehouse.
2, computing machine according to claim 1, wherein:
Register root in described a plurality of register is accessed with positive sequence or backward according to predetermined repetitive sequence.
3, computing machine according to claim 2, wherein:
When described register is accessed with described positive sequence, accessed after the last register of the first register described in the described sequence in the register in register described in the described sequence; And when described register is accessed with described backward, accessed after the first register of the last register in the described register in described register.
4, computing machine according to claim 1 further comprises:
Bidirectional shift register, comprise a plurality of single bit registers, the output of each single bit register is connected, so that small part is controlled the visit to the register that is associated in the described register, thereby make described bidirectional shift register by along described single bit register displacement, come work as stack pointer.
5, computing machine according to claim 1, wherein
Last single bit register in the described single bit register is connected to the first single bit register in the described single bit register, makes described single bit register provide circulating path for the position along described single bit register displacement.
6, a kind of storehouse computer processor comprises:
Data stack comprises at least one data register; With
Return stack comprises at least one return register; Wherein:
In described data stack and the described return stack each all can be held 18 bit instruction words.
7, processor according to claim 6, wherein said at least one data register comprise storehouse top (T) register.
8, processor according to claim 7, wherein said at least one data register further comprise the storehouse second place (S) register.
9, processor according to claim 6, wherein said at least one return stack comprises top register (R).
10, processor according to claim 6, wherein said data stack further comprises the hardware register array.
11, processor according to claim 6, wherein said return stack further comprises the hardware register array.
12, processor according to claim 10, wherein said array is with circulation pattern work.
13, processor according to claim 11, wherein said array is with circulation pattern work.
14, a kind of method of operating computer processor comprises:
A plurality of instruction words are inputed to corresponding a plurality of command units of described processor; With
Handle described a plurality of instruction word, wherein:
Instruction can be owing to described input and described processing and overflow or underflow.
15, method according to claim 14, wherein said input comprise fills all available command units.
16, method according to claim 15, wherein said input further are included in all available command units and import the extra-instruction word after being filled.
17, method according to claim 16, wherein said input and described processing take place under the situation of not using the pointer of being realized by software.
18, method according to claim 14, wherein said processing are included in and repeatedly re-use described a plurality of instruction word under the situation that is not written into described a plurality of instruction words again.
19, a kind of computer processor comprises:
Register array; With
Shift register, wherein:
Described shift register comprises a plurality of single place shift registers by electric wire interconnection, and the number of the register in the number of wherein said a plurality of single place shift registers and the described register array equates.
20, processor according to claim 19 further comprises at least one register that is positioned on the described register array.
21, processor according to claim 19, wherein said register array further comprise read bus and the write bus that makes described array interconnect.
22, processor according to claim 19, wherein said register array is with circulation pattern work.
23, processor according to claim 20, wherein said register array piles up.
24, processor according to claim 23, wherein said single place shift register interconnects by described electric wire with alternate mode.
25, processor according to claim 19, wherein said processor is a data stack.
26, processor according to claim 25, wherein said register array comprise eight data registers.
27, processor according to claim 25, wherein said register array comprise a multiple data register of four.
28, processor according to claim 14, wherein said processor is a return stack.
29, processor according to claim 28, wherein said register array comprise eight return registers.
30, processor according to claim 28, wherein said register array comprise a multiple return register of four.
31, a kind of computer processor comprises:
Register array; With
Be hard wired to the bidirectional shift register of described register array, further comprise a plurality of single place shift registers, and the number of the register in the number of wherein said a plurality of single place shift registers and the described register array equates by electric wire interconnection.
32, processor according to claim 31 further comprises at least one register that is positioned on the described register array.
33, processor according to claim 31, described shift register comes work as the hardware pointer that points to described register array.
34, processor according to claim 31 further comprises read bus and write bus.
35, processor according to claim 31, the register that each the single place shift register correspondence in described a plurality of single place shift registers is associated in described register array.
36, processor according to claim 35 wherein only has a single place shift register to be activated in described a plurality of single place shift registers of a period of time.
37, processor according to claim 31, wherein said register array further comprise read bus and the write bus that makes described array interconnect.
38, processor according to claim 31, wherein said a plurality of single place shift registers interconnect by electric wire, thereby minimize the size and the buffering of driver.
39, processor according to claim 31, wherein said electric wire all prolong between the maximal value of three adjacent single place shift registers.
40, according to the described processor of claim 39, wherein said register array comprises eight registers.
41, processor according to claim 31, wherein said processor is a data stack.
42, processor according to claim 31, wherein said processor is a return stack.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/441,784 | 2005-05-26 | ||
| US11/441,812 | 2006-05-26 | ||
| US11/441,818 US7934075B2 (en) | 2006-02-16 | 2006-05-26 | Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array |
| US11/441,818 | 2006-05-26 | ||
| US60/818,084 | 2006-06-30 | ||
| US11/503,372 | 2006-08-11 |
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|---|---|
| CN101443731A true CN101443731A (en) | 2009-05-27 |
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|---|---|---|---|
| CNA2007800171060A Pending CN101443731A (en) | 2006-05-26 | 2007-05-25 | Circular register arrays of a computer |
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| CN (1) | CN101443731A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112631510A (en) * | 2020-12-02 | 2021-04-09 | 海光信息技术股份有限公司 | Method and device for expanding stack area and hardware platform |
| WO2022111013A1 (en) * | 2020-11-27 | 2022-06-02 | 安徽寒武纪信息科技有限公司 | Device supporting multiple access modes, method and readable storage medium |
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2007
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022111013A1 (en) * | 2020-11-27 | 2022-06-02 | 安徽寒武纪信息科技有限公司 | Device supporting multiple access modes, method and readable storage medium |
| CN112631510A (en) * | 2020-12-02 | 2021-04-09 | 海光信息技术股份有限公司 | Method and device for expanding stack area and hardware platform |
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