CN101442050B - Integrated circuits for multiple packaging modes - Google Patents

Abstract

An integrated circuit adapted for multiple packaging modes comprising: the circuit comprises a core circuit, a plurality of bonding pads and a selection module. The selection module is coupled between the core circuit and the bonding pads, and comprises a plurality of selection circuits for determining the conduction state of the core circuit between the selection module and the bonding pads according to a control signal. When the control signal is a first value, the core circuit and the bonding pads are in a first conduction state, the integrated circuit is used in the single microchip package, and when the control signal is a second value, the core circuit and the bonding pads are in a second conduction state, the integrated circuit is used in the multi-microchip package.

Description

Integrated circuits for multiple packaging modes

technical field

The present invention relates to an integrated circuit, especially an integrated circuit suitable for multiple packaging modes. the

Background technique

In recent years, integrated circuits (integrated circuits; ICs) are constantly moving towards the direction of miniaturization and integration. It is one of the goals of IC development to integrate multiple functions in a single IC so that it has the ability to be systematized. However, integrating multiple functions of an IC may result in complex manufacturing steps and an excessively large die area, which in turn leads to a lower product yield. Therefore, the two functions with large manufacturing differences or difficult to integrate are divided into different microchips, and then multi-die packaging technology is used to package a variety of microchips with different functions in one package to achieve Systematic purpose. the

Please refer to FIG. 1 , which shows a known single-die package structure. The logic microchip 110 is provided with bonding pads (pads) 120, which can be connected to pins (leads) 130 of the package body (not shown in the figure) through bonding wires (bonding wires) to serve as the output/input of the entire package body Pin (I/O pin). the

Please refer to FIG. 2 , which shows a known multi-microchip packaging structure. In FIG. 2 , a logic microchip 110 and a storage microchip 150 are included, wherein the storage microchip 150 is arranged above the logic microchip 110 in the packaging structure. A group of bonding pads 120 are disposed on the logic microchip 110 for connecting to pins 130 of a package (not shown). Furthermore, another group of bonding pads 122 is provided on the logic microchip 110 for connecting the bonding pads 160 of the storage microchip 150 located above it in the same package, so that the logic microchip 110 can access the storage microchip 150 on the data. In addition, the memory microchip 150 may also have another set of bonding pads 162 for connecting to the pins 130 of the package (not shown). the

As manufacturing evolves, mask and wafer prices run high, and often enough sales are needed to keep R&D and microchip production costs low enough. However, today's market, especially consumer electronics products, often has many small differences in detail specifications, resulting in a limited market size for any one product. When choosing different packages for traditional microchips, there are usually several modes: 1. Different numbers of pins, but the same package type; 2. The same number of pins, but different functions are provided by selecting different bonding pads, such as: output 32-bits (32 bits) DRAM (Dynamic Random Access Memory; Dynamic Random Access Memory) data pin (Data Pin), support external 32-Bits SDRM; and only connect 16Bits SDRAM (Synchronous Dynamic Random Access Memory; synchronous dynamic Random access memory), only supports external 16-Bits SDRAM; 3. The number of pins is the same, but through the internal bonding pad connection method, different internal circuit functions can be selected. For example, when a bond pad is connected to the voltage source pin (VDD Pin), it supports 32-Bits SDRAM; when it is connected to the ground pin (GND Pin), it supports 16-Bits SDRAM, which is the so-called bonding wire selection mechanism ( bonding option). However, the current microchip design can only provide one packaging mode: single microchip package or multi-microchip package, so logic microchip manufacturers must design different circuit layouts and the number of bonding pads to meet the needs of downstream manufacturers. As a result, the development and production costs of microchips cannot be effectively saved. the

Contents of the invention

In view of the above problems, one of the objectives of the present invention is to provide an integrated circuit suitable for various packaging modes, so as to solve the problem disclosed in the prior art that the development and production costs of microchips cannot be effectively saved. the

One of the objectives of the present invention is to provide an integrated circuit applicable to multiple packaging modes, and different signals can be selected according to different packaging modes, so that one chip can support different product applications. the

One of the objectives of the present invention is to provide an integrated circuit suitable for various packaging modes, which can increase the application flexibility of the chip. the

One of the objectives of the present invention is to provide an integrated circuit applicable to multiple packaging modes, which can share bonding pads. the

One of the objectives of the present invention is to provide an integrated circuit suitable for various packaging modes, which can reduce the number of bonding pads. the

One of the objectives of the present invention is to provide an integrated circuit suitable for various packaging modes, which can reduce the chip area. the

The present invention proposes an integrated circuit suitable for a single microchip and a multi-microchip packaging mode, including: a core circuit, a plurality of bonding pads and a selection module. Wherein, the selection module is coupled between the core circuit and the plurality of bonding pads, and the selection module includes a plurality of selection circuits for determining the conduction state of the core circuit through the selection module and the plurality of bonding pads according to the control signal. When the control signal is the first value, the core circuit and the multiple bonding pads are in the first conduction state, and the integrated circuit is used in a single microchip package, and when the control signal is the second value, the core circuit and the multiple bonding pads are in the first conduction state. The bonding pads are in a second conduction state, and the integrated circuit is used in a multi-microchip package. Wherein the bonding pads include: a plurality of first bonding pads for coupling an external circuit and coupling the core circuit when the integrated circuit is used in the single microchip package; and a plurality of second bonding pads for coupling to the core circuit; coupled to a microchip and to the core circuit when the integrated circuit is used in the multi-microchip package; wherein the core circuit is coupled to one of the first bonding pads and one of the second bonding pads ; and the selection circuit is coupled to one of the first bonding pads and one of the second bonding pads. the

Regarding the features and implementation of the present invention, the best embodiments are described in detail as follows in conjunction with the accompanying drawings. the

Description of drawings

Fig. 1 is the schematic diagram of known single microchip (single-die) packaging structure;

Fig. 2 is the schematic diagram of known multi-microchip (multi-die) packaging structure;

3 is a schematic diagram of an integrated circuit according to a first embodiment of the present invention;

Fig. 4 is the structural representation of the integrated circuit of Fig. 3 under single microchip package;

Fig. 5 is the structural representation of the integrated circuit of Fig. 3 under the multi-microchip package;

6 is a schematic diagram of an integrated circuit according to a second embodiment of the present invention;

7 is a schematic diagram of an integrated circuit according to a third embodiment of the present invention;

8 is a schematic diagram of an integrated circuit according to a fourth embodiment of the present invention;

Fig. 9 is a schematic structural view of the integrated circuit of Fig. 8 under a single microchip package;

Figure 10 is a schematic structural view of the integrated circuit of Figure 8 under multi-microchip packaging; and

FIG. 11 is a schematic diagram of an integrated circuit according to a fifth embodiment of the present invention. the

Description of main component symbols

110 logic microchip

120 splicing pad

122 Bonding Pad

130 pins

150 memory microchips

160 Bonding Pads

162 Bonding Pad

200 integrated circuits

210 core circuit

212 The first core circuit

214 Second core circuit

220a Joint pad group

220b Joint pad group

220c joint pad group

220d joint pad group

220e joint pad group

220f joint pad group

230 joint pad

230a splicing pad

230b Bonding Pad

230c joint pad

230e Bonding Pad

232a Bonding Pad

232b Bonding Pad

232c Bonding Pad

232d bonding pad

234a bonding pad

234b bonding pad

234c bonding pad

234d bonding pad

236a bonding pad

236b bonding pad

236c bonding pad

236d joint pad

236e Bonding Pad

236f bonding pad

236g joint pad

236h bonding pad

236i Bonding Pad

236j Bonding Pad

250 joint pads

250a splicing pad

250b splicing pad

250c joint pad

270 selection circuit

272a selection circuit

272b selection circuit

272c selection circuit

272d selection circuit

274a selection circuit

274b selection circuit

274c selection circuit

274d selection circuit

280 buffer

290 control circuit

292 registers

300 first package body

302 substrate

310 pins

310a pin

310b pin

310c pin

310d pin

310e pin

312a pin

312b pin

312c pin

312d pin

312e pin

312f pin

312g pin

312h pin

312i pin

314a pin

314b pin

314c pin

314d pin

314e pin

400 integrated circuits

410 joint pad

410a bonding pad

410b Bonding Pad

410c Splice Pad

410d joint pad

410e Bonding Pad

412a Bonding Pad

412b Bonding Pad

412c Bonding Pad

412d Bonding Pad

412e Bonding Pad

500 second package body

510a pin

510b pin

510c pin

510d pin

510e pin

512a pin

512b pin

512c pin

512d pin

512e pin

600 third package body

610a pin

610b pin

610c pin

610d pin

610e pin

Detailed ways

Specific embodiments are given below to describe the content of the present invention in detail, and the accompanying drawings are used as auxiliary descriptions. The symbols mentioned in the description are reference figures. the

Referring to FIG. 3 , it is an integrated circuit 200 according to an embodiment of the present invention, which is applicable to various types of packaging, such as single microchip packaging, multi-microchip packaging, and the like. The integrated circuit 200 includes: a core circuit 210 , a plurality of bonding pads 230 , 250 , a selection circuit 270 and a control circuit 290 . the

Here, the core circuit 210 refers to the circuit part used to provide the main core functions of the integrated circuit. Generally speaking, the core circuit 210 will have one or more signal input/output signals. In this embodiment, in order to be applicable to various packaging modes, the signal input terminal is coupled to the selection circuit 270, and the selection circuit 270 is coupled between the two bonding pads 230a, 250a and the signal input terminal of the core circuit 210 Between; the signal output terminal is coupled to the two bonding pads 230c, 250c. The control circuit 290 outputs a control signal to the selection circuit 270 according to the packaging mode of the integrated circuit 200, so that the selection circuit 270 electrically connects the signal input end of the core circuit 210 to one of the bonding pads 230a, 250a according to the control signal. . Here, the control circuit 290 may have a register 292, which is used to store the parameter value required to determine which packaging mode the integrated circuit 200 is used in, so as to output the control signal required to control the selection circuit 270, and the value stored in the register 292 Values can be changed via firmware or software program code. Moreover, although in the present embodiment, the above-mentioned control signal is determined by the control circuit 290 according to the parameter value of the register 292, the present invention is not limited thereto, other common options such as bonding option (bonding option) The mode selection mechanism can also be used here. the

In this way, the integrated circuit 200 can be applied to various packaging modes. For example, when this integrated circuit 200 (hereinafter referred to as the first integrated circuit 200 for convenience of description) is applied to a single microchip package (please refer to FIGS. On the substrate 302, the bonding pad 230 of the first integrated circuit 200 is connected to another package (for For convenience of description, the second package body 500) is referred to as the electrical connection hereinafter. Wherein, the first package body 300 and the second package body 500 are generally disposed on a printed circuit board (printed circuit board), and are connected to their respective pins 310a, 310b, 310c, 310d, 310e/510a, 510b, 510c, 510d, and 510e are connected to each other by wiring on the circuit boards. Here, the second package body 500 can be SDRAM (Synchronous Dynamic Random Access Memory; Synchronous Dynamic Random Access Memory), on which there is another integrated circuit (hereinafter referred to as the second integrated circuit 400 for convenience of description), in other words, The bonding pads 230 of the first integrated circuit 200 pass through the pins 310a/310b/310c/310d/310e of the first package 300, the pins 510a/510b/510c/510d/510e of the second package 500, and the circuits therebetween Board wires, connected to the bonding pads 410a/410b/410c/410d/410e on the second integrated circuit 400, for example, the bonding pad 230a is connected to the bonding pads on the second integrated circuit 400 through the pin 310a and the pin 510a 410a, and the bonding pad 230c is connected to the bonding pad 410c on the second integrated circuit 400 through the pin 310c and the pin 510c. At this time, the selection circuit 270 electrically connects the signal input end of the core circuit 210 to the bonding pad 230 . the

And when this integrated circuit 200 (hereinafter referred to as the first integrated circuit 200 for convenience of description) is applied to multi-microchip packaging (please refer to FIGS. 3 and 5), another integrated circuit (for convenience) is provided on the first integrated circuit 200. The second integrated circuit 400 (hereinafter referred to as the second integrated circuit 400 ), such as a memory microchip, is electrically connected to each other through the bonding pad 250 and the bonding pad 410 . Wherein, the bonding pad 230 of the first integrated circuit 200 corresponds to the bonding pad 250 , that is, is coupled to the same selection circuit 270 or the same signal output terminal. The first integrated circuit 200 is disposed on the substrate 302 of the first package body 300 , and is electrically connected to the pins 310 on the substrate 302 by the bonding pads 230 not corresponding to the bonding pads 250 . For example, the bonding pad 250a is coupled to the bonding pad 410a on the second integrated circuit 400, while the bonding pad 230a corresponding to the bonding pad 250a is not electrically connected to the pin 310a; similarly, the bonding pad 250c is coupled to the second For the bonding pad 410c on the integrated circuit 400, the bonding pad 230c corresponding to the bonding pad 250c is not electrically connected to the pin 310c; and the bonding pad 230e not corresponding to the bonding pad 250 is electrically connected to the pin 310e. At this time, the selection circuit 270 electrically connects the signal input end of the core circuit 210 to the bonding pad 250 . the

Expressed in another way, the bonding pads 230, 250 can be divided into a first bonding pad (ie, bonding pad 230 ) for coupling to an external circuit, and a second bonding pad (ie, bonding pad 230 ) for coupling to another integrated circuit. 250). In other words, when applied to a single microchip package, the selection circuit 270 electrically conducts the signal input terminal of the core circuit 210 with the first bonding pad (ie, the bonding pad 230a) according to the received control signal; When the microchip is packaged, the selection circuit 270 electrically conducts the signal input end of the core circuit 210 with the second bonding pad (ie, the bonding pad 250 a ) according to the received control signal. the

Moreover, a buffer 280 can be coupled between the signal output terminal of the core circuit 210 and the bonding pads 230c, 250c for buffering, or in other words, strengthening driving, the signal to be output by the core circuit 210 . the

Wherein, the selection circuit 270 can be realized by using a multiplexer, the input terminal of this multiplexer is connected to the bonding pads 230a, 250a, the output terminal is connected to the signal input terminal of the core circuit 210, and its control terminal is connected to the control Circuit 290 to receive the control signal. For example, when the integrated circuit 200 is applied to a single microchip package, the control circuit 290 will output a control signal 1 to the selection circuit 270, thus causing the selection circuit 270 to electrically connect the signal input terminal of the core circuit 210 to the bonding pad 230a Conversely, when applied to multi-microchip packaging, the control circuit 290 will output a control signal 0 to the selection circuit 270, thus causing the selection circuit 270 to electrically conduct the signal input terminal of the core circuit 210 with the bonding pad 250a. the

Here, the bonding pads 230 and 250 can be unidirectional (as shown in FIG. 3 ) or bidirectional (as shown in FIG. 6 ). When unidirectional transmission pads 230 , 250 are used, the signal output end of the core circuit 210 and the selection circuit 270 are coupled to different pads 230 c , 250 c / 230 a , 250 a , as shown in FIG. 3 . When using the bonding pads 230 , 250 for bidirectional transmission, the signal output end of the core circuit 210 and the selection circuit 270 are coupled to the same bonding pads 230 b , 250 b , as shown in FIG. 6 . the

Referring to FIG. 7 , an integrated circuit 200 according to another embodiment of the present invention is suitable for a first mode and a second mode of packaging, such as single microchip packaging and multi-microchip packaging. The integrated circuit 200 includes: a plurality of core circuits (for convenience of description, the first core circuit 212 and the second core circuit 214 are used as examples below), a plurality of bonding pads 230 and selection circuits 272a, 272b, 272c, 272d, 274a, 274b , 274c, 274d. the

Sequentially adjacent bond pads 232a, 232b/232c, 232d/234a, 234b/234c, 234d can be classified as bond pad groups 220a/220b/220c/220d, respectively, and bond pad groups 220a, 220b/220c, 220d will Corresponding to the first core circuit 212 and the second core circuit 214 respectively. the

The selection circuits 272 a , 272 b , 272 c , 272 d , 274 a , 274 b , 274 c , 274 d are coupled between the bonding pad 230 and the first core circuit 212 or the second core circuit 214 . the

When the integrated circuit 200 is packaged in the first mode, the selection circuits 272a, 272b, 274a, 274b electrically conduct the first core circuit 212 with the bonding pads 232a, 232b, 234a, 234b in the corresponding bonding pad groups 220a, 220c , and the selection circuits 272c, 272d, 274c, 274d electrically conduct the second core circuit 214 with the bonding pads 232c, 232d, 234c, 234d in the corresponding bonding pad groups 220b, 220d. And when the integrated circuit 200 is packaged in the second mode, the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d electrically connect the same core circuit with the bonding pads 230 at least a predetermined distance from each other, that is, select Circuits 272a, 272b, 274b, 274d electrically conduct first core circuit 212 with bond pads 232b, 232d, 234b, 234d, and selection circuits 272c, 272d, 274a, 274c connect second core circuit 214 with bond pads 232a, 232c, 234a, 234c are electrically connected. Wherein, the predetermined distance is a distance determined according to bonding rules. the

Here, a control circuit 290 may be used to output control signals according to the packaging of the first mode or the second mode (ie according to the packaging mode to be applied by the integrated circuit 200) to control the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d switching, that is, the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d connect the bonding pad 230 with the core circuit (for example: the first core circuit 212 and the second core circuit 214) according to the control signal ) electrical conduction. Wherein, the control circuit 290 may have a register 292, which is used to store the parameter values required to determine which packaging mode the integrated circuit 200 is used in, to output and control the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d required control signal. the

For example, here the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d can be realized by using multiplexers, and these multiplexers are coupled between the core circuit and the bonding pads; when integrated When the circuit 200 is applied to the package of the first mode, the control circuit 290 will output a control signal 1 to the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d, thus causing the selection circuits 272a, 272b, 274a, 274b The first core circuit 212 is electrically connected to the bond pads 232a, 232b, 234a, 234b within the bond pad groups 220a, 220c, and the selection circuit 272c, 272d, 274c, 274d is used to connect the second core circuit 214 to the bond pad groups 220b, 220d. The bonding pads 232c, 232d, 234c, 234d inside are electrically connected; otherwise, when applied to the package of the second mode, the control circuit 290 will output a control signal 0 to the selection circuits 272a, 272b, 272c, 272d, 274a, 274b , 274c, 274d, thus causing the selection circuits 272a, 272b, 274b, 274d to electrically conduct the first core circuit 212 with the bonding pads 232b, 232d, 234b, 234d, and the selection circuits 272c, 272d, 274a, 274c to connect the second core circuit 214 is in electrical communication with bond pads 232a, 232c, 234a, 234c. the

Each core circuit (the first core circuit 212 and the second core circuit 214) has one or more signal input/output terminal signals, respectively coupled to the output and input of the selection circuit, and the signal input terminal and the signal output terminal can be respectively correspond to each other. For example, referring to FIG. 7, the signal input terminals of the first core circuit 212 are coupled to the selection circuits 272a, 272b, and the corresponding signal output terminals are coupled to the selection circuits 274a, 274b, 274d; and the second The signal input terminals of the core circuit 214 are coupled to the selection circuits 272c, 272d, and the corresponding signal output terminals are coupled to the selection circuits 274a, 274c, 274d. the

Moreover, the selection circuits 274a, 274b, 274c, 274d coupled to the signal output ends of the core circuits (the first core circuit 212 and/or the second core circuit 214) can be coupled to the bonding pads 234a, 234b, 234c, 234d. The buffer 280 is used to buffer the signal to be output by the core circuit (the first core circuit 212 / the second core circuit 214 ). the

Here, the bonding pad 230 can be unidirectional (as shown in FIG. 7 ) or bidirectional (as shown in FIG. 8 ). When the bonding pad 230 of unidirectional transmission is adopted, the signal input terminal and the signal output terminal of the same core circuit (first core circuit 212/second core circuit 214) pass through selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d, and coupled to different bonding pads 232a, 232b, 232c, 232d/234a, 234b, 234c, 234d, as shown in FIG. the

And when using the bonding pads 236a, 236b, 236c, 236d for bidirectional transmission, the signal input end and signal output end of the same core circuit (first core circuit 212/second core circuit 214) pass through the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d, and are coupled to the same bond pads 236a, 236b, 236c, 236d, as shown in FIG. And, when the integrated circuit 200 is applied to the package of the first mode, the first core circuit 212 is electrically connected to the bonding pad group 220e, and the second core circuit 214 is electrically connected to the bonding pad group 220f, and when the integrated circuit 200 is applied to the second When packaged in the same mode, the first core circuit 212 and the second core circuit 214 are sequentially alternately electrically connected to the bonding pads 236a, 236b, 236c, and 236d. Here, although sequential interleaving is taken as an example, in fact, as long as the bond pads coupled to the same core circuit are separated from each other by a predetermined distance in accordance with the bonding rule. the

Therefore, the integrated circuit 200 can be applied to various packaging modes. For example, when the integrated circuit 200 (hereinafter referred to as the first integrated circuit 200 for convenience of description) is applied to a single microchip package (please refer to FIGS. 8 and 9), the integrated circuit 200 is disposed on the substrate of the first package 300 302 , the bonding pads 230 on the first integrated circuit 200 are electrically connected to pins 312 a , 312 b , 312 c , 312 d , 312 e , 312 f , 312 g , 312 h , 312 i disposed on the substrate 302 . Wherein, the bonding pads of the bonding pad group 220f are electrically connected to the pins 512a, 512b, 512c, 512d, 512e of the second package body 500 via the pins 312e, 312f, 312g, 312h, 312i, and the bonding pads of the bonding pad group 220e are electrically connected to the pins 610a, 610b, 610c, 610d of the third package 600 via the pins 312a, 312b, 312c, 312d, and in general, the first, second, and third packages 300, 500, 600 are all arranged on a printed circuit board. At this time, the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, 274d electrically connect the first core circuit 212 to the bonding pad group 220e, and electrically connect the second core circuit 214 to the bonding pad group 220f. Wherein, the second package body 500 can be SDRAM, has another integrated circuit on it (hereinafter referred to as the second integrated circuit 400 for convenience of description), here the first integrated circuit 200 can be connected via its bonding pad group 220f, pin 312e, 312f, 312g, 312h, 312i and pins 510a/510b/510c/510d/510e are connected to bonding pads on the second integrated circuit 400 so that the second core circuit 214 can access the data stored on the second integrated circuit 400. data; and the third package body 600 can be a functional circuit, where the first integrated circuit 200 can be connected to the pins 610a, 312d, 312a, 312b, 312c, 312d of the third package body 600 via its bonding pad group 220e 610b, 610c, 610d to control the operation of the third package 600. the

And when the integrated circuit 200 (hereinafter referred to as the first integrated circuit 200 for convenience of description) is applied to a multi-microchip package (please refer to FIGS. 7, 8 and 10), the first integrated circuit 200 is arranged on the substrate of the first package 300 302 , and another integrated circuit (hereinafter referred to as the second integrated circuit 400 for convenience of description), such as a memory microchip, is disposed on the first integrated circuit 200 . Here, the first integrated circuit 200 is electrically connected to the bonding pads 412a, 412b, 412c, 412d, 412e of the second integrated circuit 400 through the bonding pads 236b, 236d, 236f, 236h, 236j respectively, and the first integrated circuit 200 The non-adjacent bonding pads 236a, 236c, 236e, 236g, 236i are electrically connected to the third package body 600 through the pins 314a, 314b, 314c, 314d, 314e provided on the substrate 302 of the first package body 300 The pins 610 a , 610 b , 610 c , 610 d , 610 e are used to control the operation of the third package 600 . At this time, the selection circuits 272a, 272b, 272c, 272d, 274a, 274b, 274c, and 274d electrically conduct the same core circuit with non-adjacent bonding pads 230, for example: the selection circuits 272a, 272b, 274b, 274d connect the first The core circuit 212 is electrically connected to the bonding pads 232b, 232d, 234b, 234d, and the selection circuits 272c, 272d, 274a, 274c are electrically connected to the second core circuit 214 and the bonding pads 232a, 232c, 234a, 234c. the

By switching the bonding pads to be connected to the same integrated circuit with a predetermined distance as described above, or having other bonding pads spaced therebetween, the integrated circuit (or microchip) of this embodiment is used for multi-microchip When packaged, it can meet the requirements of the bonding wire rule that there must be a certain distance between the bonding wires. At the same time, when switching to a single microchip packaging mode, multiple bonding pads connected to the same external package can be switched to be concentrated in a continuous position, which facilitates the wiring layout on the printed circuit board. the

Furthermore, in another embodiment, the bonding pad 230 may belong to an input pad (input pad) in a certain mode, and belong to an output pad (output pad) in another mode as shown in FIG. 11 . In this embodiment, when the control circuit 290 outputs the control signal 1 to the selection circuits 274a, 274b, 274c, 274d, thus causing the selection circuits 274a, 274b to conduct the signal output terminal of the first core circuit 212 to the bonding pads 236a, 236b. Pass. Similarly, the selection circuits 274c and 274d also electrically connect the signal output terminals of the second core circuit 214 to the bonding pads 236c and 236d. Therefore, in this embodiment, when the control signal is 1, the pad 230 belongs to the output pad. Here, when the integrated circuit 200 is applied in a mode package with the control signal being 1, the first core circuit 212 is electrically connected to the bonding pad group 220e, and the second core circuit 214 is electrically connected to the bonding pad group 220f. the

Conversely, when the control circuit 290 outputs the control signal 0 to the selection circuits 272a, 272b, 272c, and 272d, the selection circuits 272a, 272b are caused to electrically connect the signal input terminal of the first core circuit 212 to the bonding pads 236b, 236d. Similarly, the selection circuits 272c, 272d also electrically connect the signal input end of the second core circuit 214 to the bonding pads 236a, 236c. Therefore, in the mode in which the control signal is 0 in this embodiment, the pad 230 belongs to the input pad. Here, when the integrated circuit 200 is applied in a mode package with the control signal being 0, the first core circuit 212 and the second core circuit 214 are sequentially electrically connected to the bonding pads 236 a , 236 b , 236 c , and 236 d. the

Therefore, the application example in FIG. 11 can be applied to a single microchip package by adjusting the control signal to 1, and reference can be made to the detailed description of FIG. 9 above. On the contrary, when the control signal is 0, multi-microchip packaging can be applied, and the detailed description of the above-mentioned FIG. 10 can be referred to. the

As mentioned above, the difference between the embodiments in Figures 3-6 and the embodiments in Figures 7-11 is that in the former, some bonding pads are located in the inner side of the integrated circuit to facilitate multiple When the microchip is packaged, it is connected to other microchips in the same package; while the latter places all the bonding pads on the edge of the integrated circuit, and then uses the sequentially staggered bonding pad configuration to meet the requirements for multi-microchip packaging. Requirements for seam wire rules. But no matter what kind of implementation, the present invention can select different signals according to different packages through circuit design, so that one chip can support different product applications, thereby increasing the application flexibility of the chip, and effectively reducing the number of bonding pads and chip area . For example, if an application has 208 pins in a single chip package, 80 pins are the docking signals to another specific chip, so in the old way, there must be at least 208 external bond pads and 80 internal bond pads , a total of 288. But according to the chip of the present invention, 208 bonding pads can be kept without increasing 80 bonding pads, and a package body with 128 pins can be used instead; 80 pins of bonding pads can output other application signals to add more product functions. the

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the protection scope of the present invention shall be determined by the scope of the appended claims. the

Claims (12)

1. integrated circuit that is applicable to the encapsulation mode of a single microchip and microchip more than comprises:

One core circuit;

A plurality of joint sheets; And

One selects module, is coupled between this core circuit and these a plurality of joint sheets, and this selection module comprises a plurality of selection circuit, in order to decide this core circuit by the conducting state between this selection module and this a plurality of joint sheets according to a control signal;

Wherein when this control signal is one first numerical value, be in one first conducting state between this core circuit and this a plurality of joint sheets, this integrated circuit is used for a single microchip encapsulation, and when this control signal is a second value, be in one second conducting state between this core circuit and this a plurality of joint sheets, this integrated circuit is used for the encapsulation of microchip more than

Wherein this joint sheet comprises:

A plurality of first joint sheets in order to coupling an external circuit, and couple this core circuit when this integrated circuit is used for this list microchip encapsulation; And

A plurality of second joint sheets in order to coupling a microchip, and couple this core circuit when this integrated circuit is used for this many microchips encapsulation;

Wherein, this core circuit one of be coupled in this first joint sheet with this second joint sheet in one of; And this selection circuit one of be coupled in this first joint sheet with this second joint sheet in one of.

2. integrated circuit as claimed in claim 1, when wherein this integrated circuit was used for this list microchip encapsulation, this selection circuit conducted this core circuit and this first joint sheet.

3. integrated circuit as claimed in claim 1, when wherein this integrated circuit was used for this many microchips encapsulation, this selection circuit conducted this core circuit and this second joint sheet.

4. integrated circuit that is applicable to the encapsulation mode of a single microchip and microchip more than comprises:

A plurality of joint sheets;

One core circuit comprises:

One signal input part; And

One signal output part is coupled to two in this joint sheet;

One control circuit is in order to export a control signal according to the encapsulation mode of this list microchip and these many microchips; And

One selects circuit, be coupled between in this joint sheet two and this signal input part, in order to according to this control signal with two in this signal input part and this joint sheet one of them conduct,

Wherein this joint sheet comprises:

A plurality of first joint sheets in order to coupling an external circuit, and couple this core circuit when this integrated circuit is used for this list microchip encapsulation; And

A plurality of second joint sheets in order to coupling a microchip, and couple this core circuit when this integrated circuit is used for this many microchips encapsulation;

Wherein, this signal output part one of be coupled in this first joint sheet with this second joint sheet in one of; And this selection circuit one of be coupled in this first joint sheet with this second joint sheet in one of.

5. integrated circuit as claimed in claim 4, wherein when this pattern of using was the encapsulation of microchip more than, this selection circuit conducted this signal input part and this second joint sheet.

6. integrated circuit as claimed in claim 4, wherein when this pattern of using was a single microchip encapsulation, this selection circuit conducted this signal input part and this first joint sheet.

7. integrated circuit as claimed in claim 4, wherein this selection circuit is a multiplexer, has a plurality of inputs that connect this joint sheet, a control end that connects an output of this signal input part and connect this control circuit.

8. an integrated circuit is applicable to the encapsulation of a single microchip and microchip more than, comprising:

A plurality of joint sheet groups, each joint sheet group has adjacent in regular turn a plurality of joint sheets;

A plurality of core circuits are corresponding to this joint sheet group; And

A plurality of selection circuit are coupled between this joint sheet and this core circuit, when this microchip is the encapsulation of this list microchip, this selection circuit with this core circuit respectively with pairing this joint sheet group in this joint sheet conduct; And when this microchip is the encapsulation of these many microchips, this selection circuit with same this core circuit with conduct at a distance of this joint sheet of a preset distance each other.

9. integrated circuit as claimed in claim 8 also comprises:

One control circuit is exported a control signal in order to selectivity according to the encapsulation of this list microchip and these many microchips;

Wherein, this selection circuit conducts this joint sheet and this core circuit according to this control signal.

10. integrated circuit as claimed in claim 8, wherein each this core circuit comprises:

At least one signal input part is coupled to this selection circuit; And

At least one signal output part corresponding to this signal input part, is coupled to this selection circuit, and when this joint sheet was one-way transmission, corresponding this signal input part conducted to this different joint sheets via this selection circuit with this signal output part.

11. integrated circuit as claimed in claim 8, wherein each this core circuit comprises:

At least one signal input part is coupled to this selection circuit; And

At least one signal output part corresponding to this signal input part, is coupled to this selection circuit, and when this joint sheet was transmitted in both directions, corresponding this signal input part conducted to this identical joint sheet via this selection circuit with this signal output part.

12. integrated circuit as claimed in claim 8 also comprises:

A plurality of buffers are electrically connected this selection circuit and this joint sheet.

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