CN101436567B - Method for preparing contact hole of plow groove type MOS transistor - Google Patents
Method for preparing contact hole of plow groove type MOS transistor Download PDFInfo
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- CN101436567B CN101436567B CN2007100942351A CN200710094235A CN101436567B CN 101436567 B CN101436567 B CN 101436567B CN 2007100942351 A CN2007100942351 A CN 2007100942351A CN 200710094235 A CN200710094235 A CN 200710094235A CN 101436567 B CN101436567 B CN 101436567B
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- contact hole
- etching
- contact holes
- boron
- mos transistor
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000002360 preparation method Methods 0.000 claims abstract description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010936 titanium Substances 0.000 claims abstract description 7
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 5
- 239000010937 tungsten Substances 0.000 claims abstract description 5
- 239000011521 glass Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000001965 increasing effect Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 abstract 3
- 239000005360 phosphosilicate glass Substances 0.000 abstract 3
- 238000000137 annealing Methods 0.000 abstract 1
- -1 titanium nitride ions Chemical class 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for preparing contact holes of a groove type MOS transistor, which comprises the following steps: (1) photoetching the contact holes after being coated with photosensitive resist, etching boron-phosphosilicate glass and an oxidation film to the silicon surface by a dry method; (2) further etching the contact holes into a groove shape to deepen across a source area; (3) peeling off the photosensitive resist; (4) transversely etching the boron-phosphosilicate glass and the oxidation film by a wet method; (5) treating the groove-shaped contact holes into circular holes by the dry method, and carrying out isotropic etching; (6) etching the boron-phosphosilicate glass and the oxidation film again by the wet method to make side walls of the contact holes form smooth curved surfaces; (7) injecting ions into the contact holes; (8) sputtering the contact holes by titanium and titanium nitride ions, and thermally annealing the contact holes quickly; and (9) depositing a tungsten plug. Through increasing a wet etching process and an isotropic etching process in the prior preparation method, the preparation method changes 90-dgree bottom corners of the prior contact holes, and solves the problems of poor metallic step coverage property caused by blockage of vertical side walls and possible electric leakage.
Description
Technical field
The present invention relates to a kind of manufacturing process of groove type MOS transistor, be specifically related to a kind of preparation method of contact hole of groove type MOS transistor.
Background technology
In groove type MOS transistor,, reduce current loss in order to reduce the on-resistance per unit of MOSFET (mos field effect transistor).It is more and more higher that the channel density of MOSFET is done.The critical size of single MOS transistor is also done littler and littler.Therefore lost efficacy in order to prevent UIS (not clamper inductive switch) at power MOS transistor, be to inject by do a step ion when doing contact hole in the past, forms a passage, makes source region and channel region be in that same potential realizes.Under the ever-reduced situation of critical size, change has taken place in the mode that the source region is injected, so this method can not be suitable for.So must reach same purpose by doing channel shaped contact hole (Contact Trench).
As Fig. 1, the basic structure of groove type MOS transistor comprises: drain region 7 is arranged at the silicon substrate bottom, channel region 6 and source region 4 are arranged on it successively, the groove 3 that has polysilicon to fill in channel region 6 and 4 both sides, source region has the oxide-film 2 (LTO) and the boron-phosphorosilicate glass 1 (BPSG) of low-temperature epitaxy in addition successively in surface of silicon.General channel shaped contact hole etching technology comprises: contact hole photoetching behind (1) resist coating, dry method are etched to silicon face with BPSG and LTO; (2) etching groove is crossed the source region junction depth; (3) the contact hole ion injects; (4) photoresist lift off; (5) titanium and titanium nitride ion sputtering, rapid thermal annealing; (6) tungsten plug deposit.Its cross section of structure and morphology that has channel shaped contact hole 1 in the technology shown in Fig. 1 now is a rectangle, and the considerable defective that the contact hole device of this structure and technology exist mainly contains following problem:
(1) channel shaped contact hole side wall angle angle is near 90 degree, and depth-to-width ratio is very big, in the time of can causing in the step process of back the barrier metal sputter, and sputter very thin or almost do not have on sidewall.What so contact hole resistance will become is very big, has a strong impact on that one of most important parameter is a conducting resistance in the power device.
(2), and bring the problem of leak electricity excessive or device reliability because on two angles of groove-shaped contact hole bottom, shape may cause these two local electric field strength excessive near the right angle when device is worked.
Therefore this patent has proposed a kind of shape that changes the channel shaped contact hole at above-mentioned defective, reaches the method for optimizing this technology.
Summary of the invention
Technical problem to be solved by this invention provides a kind of preparation method of contact hole of groove type MOS transistor, and it can solve the MOS critical size and constantly dwindle the bad and electric leakage problem that may bring of barrier metal step coverage in the contact hole of back.
In order to solve above technical problem, the invention provides a kind of preparation method of contact hole of groove type MOS transistor, wherein the structure of groove type MOS transistor is: the drain region is arranged at the silicon substrate bottom, channel region and source region are arranged on it successively, the groove that has polysilicon to fill in described channel region and both sides, source region has the oxide-film and the boron-phosphorosilicate glass of low-temperature epitaxy in addition successively in described surface of silicon; This method comprises the steps: behind (1) resist coating that to the contact hole photoetching, dry method is etched to silicon face with boron-phosphorosilicate glass and oxide-film; (2) the further etching groove of contact hole is crossed the source region junction depth; (3) photoresist lift off; (4) wet method is to boron-phosphorosilicate glass and oxide-film lateral etching; (5) dry method is done circular hole to the channel shaped contact hole and is handled isotropic etching; (6) wet method makes the sidewall of contact hole form level and smooth curved surface to boron-phosphorosilicate glass and oxide-film etching once more; (7) the contact hole ion injects; (8) titanium and titanium nitride ion sputtering, rapid thermal annealing; (9) tungsten plug deposit.
Because the present invention has increased the step of wet etching in the preparation technology of the contact hole of original groove type MOS transistor, and then changed the pattern of contact hole, overcome the electric leakage problem that barrier metal step coverage that corner, former contact hole bottom becomes 90 degree and sidewall vertically to cause is bad and may bring.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is existing channel shaped contact hole structure chart;
Fig. 2 is the structural representation after the enforcement step of the present invention (1);
Fig. 3 is the structural representation after the enforcement step of the present invention (2);
Fig. 4 is the structural representation after the enforcement step of the present invention (4);
Fig. 5 is the structural representation after the enforcement step of the present invention (5);
Fig. 6 is the structural representation after the enforcement step of the present invention (6);
Fig. 7 is the structural representation after the enforcement step of the present invention (8);
Fig. 8 is the structural representation after the enforcement step of the present invention (9).
Reference numeral is among the figure, 1, boron-phosphorosilicate glass; 2, oxide-film; 3, the groove of polysilicon filling; 4, source region; 5, channel shaped contact hole; 6, channel body; 7, drain region; 8, titanium and titanium nitride.
Embodiment
The present invention is the method for a kind of channel shaped contact hole of preparation on groove type MOS transistor, and to change corner, original contact hole bottom be the electric leakage problem that the barrier metal step coverage that vertically causes of 90 degree and sidewall is bad and may bring by increasing wet corrosion technique.The structure of the groove type MOS transistor that the present invention utilized is: drain region 7 is arranged at the silicon substrate bottom, channel region 6 and source region 4 are arranged on it successively, the groove 3 that has polysilicon to fill in described channel region 6 and 4 both sides, source region has the oxide-film 2 and the boron-phosphorosilicate glass 1 of low-temperature epitaxy in addition successively in described surface of silicon.The present invention at first behind the resist coating to the contact hole photoetching, (thickness is approximately with boron-phosphorosilicate glass 1 for dry method
) and oxide-film 2 (thickness pact
) be etched to silicon face, implement after this step technological effect as shown in Figure 2.Secondly contact hole further carries out etching groove and crosses source region 4 junction depths, and the about 4 μ m of etching depth form channel shaped contact hole 5 after the etching, implement after this step technological effect as shown in Figure 3.Then carry out photoresist lift off and wet method to boron-phosphorosilicate glass 1 and oxide-film 2 lateral etchings, etching depth
(be about in the present embodiment
), implement after this step technological effect as shown in Figure 4.Carry out dry method again channel shaped contact hole 5 is done the circular hole processing, isotropic etching, etch silicon is approximately
(be about in the present embodiment
), implement after this step technological effect as shown in Figure 5.And then wet method is to boron-phosphorosilicate glass 1 and oxide-film 2 etchings, and etching depth approximately
Make the sidewall of contact hole form level and smooth curved surface, implement after this step technological effect as shown in Figure 6.Carry out injection of contact hole ion and titanium and titanium nitride 8 ion sputterings again, rapid thermal annealing, the thickness that injects titanium and titanium nitride 8 is respectively
With
About, implement after this step technological effect as shown in Figure 7.Carry out the deposit of tungsten plug at last, deposition thickness approximately
Implement after this step technological effect as shown in Figure 8.
The channel shaped contact hole for preparing behind the above-mentioned processing step of the present invention bottom is fillet and sidewall is level and smooth curved surface, has solved the electric leakage problem that the barrier metal step coverage is bad and may bring.
Claims (3)
1. the preparation method of the contact hole of a groove type MOS transistor, the structure of described groove type MOS transistor is: the drain region is arranged at the silicon substrate bottom, channel region and source region are arranged on it successively, the groove that has polysilicon to fill in described channel region and both sides, source region, oxide-film and boron-phosphorosilicate glass that low-temperature epitaxy is arranged successively in described surface of silicon in addition; It is characterized in that, comprise the steps:
(1) behind the resist coating to the contact hole photoetching, dry method is etched to silicon face with boron-phosphorosilicate glass and oxide-film;
(2) contact hole further carries out etching groove and crosses the source region junction depth;
(3) photoresist lift off;
(4) wet method is to boron-phosphorosilicate glass and oxide-film lateral etching;
(5) dry method is done the circular hole processing to the channel shaped contact hole, and isotropic etching makes the contact hole bottom be fillet;
(6) wet method makes the sidewall of contact hole form level and smooth curved surface to boron-phosphorosilicate glass and oxide-film etching once more;
(7) the contact hole ion injects;
(8) titanium and titanium nitride ion sputtering, rapid thermal annealing;
(9) tungsten plug deposit.
2. the preparation method of the contact hole of groove type MOS transistor as claimed in claim 1 is characterized in that, the described wet method of step (4) is to boron-phosphorosilicate glass and oxide-film etching, and its depth bounds is
3. the preparation method of the contact hole of groove type MOS transistor as claimed in claim 1 is characterized in that, the described dry method of step (5) is done circular hole to the channel shaped contact hole and handled, isotropic etching, and its depth bounds is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942351A CN101436567B (en) | 2007-11-15 | 2007-11-15 | Method for preparing contact hole of plow groove type MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100942351A CN101436567B (en) | 2007-11-15 | 2007-11-15 | Method for preparing contact hole of plow groove type MOS transistor |
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| Publication Number | Publication Date |
|---|---|
| CN101436567A CN101436567A (en) | 2009-05-20 |
| CN101436567B true CN101436567B (en) | 2010-09-29 |
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|---|---|---|---|
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901767B (en) * | 2009-05-26 | 2011-12-14 | 上海华虹Nec电子有限公司 | Method for obtaining vertical channel high-voltage super junction-semiconductor device |
| CN101930977B (en) * | 2009-06-19 | 2012-07-04 | 万国半导体股份有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) device with tungsten spacing layer in contact hole and preparation method thereof |
| CN102064130B (en) * | 2009-11-12 | 2013-03-13 | 上海华虹Nec电子有限公司 | Method for forming SDMOS contact hole shape beneficial for filling metal |
| CN102103997B (en) * | 2009-12-18 | 2012-10-03 | 上海华虹Nec电子有限公司 | Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof |
| CN104952722A (en) * | 2014-03-28 | 2015-09-30 | 中芯国际集成电路制造（天津）有限公司 | Metal deposition method and method for removing sharp corner of groove |
| CN106816365B (en) * | 2016-12-23 | 2019-05-07 | 信利（惠州）智能显示有限公司 | A method of increasing the via hole angle of gradient of via layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
| US6482701B1 (en) * | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| CN1929149A (en) * | 2005-06-06 | 2007-03-14 | 谢福渊 | Source contact and metal scheme for high density trench MOSFET |
-
2007
- 2007-11-15 CN CN2007100942351A patent/CN101436567B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
| US6482701B1 (en) * | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
| CN1929149A (en) * | 2005-06-06 | 2007-03-14 | 谢福渊 | Source contact and metal scheme for high density trench MOSFET |
Non-Patent Citations (1)
| Title |
|---|
| JP平5-90218A 1993.04.09 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206 Jinqiao Road, Pudong New Area Jinqiao Export Processing Zone, Shanghai, 1188 Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |