CN101425339B

CN101425339B - Reading circuit for large capacity EEPROM memory

Info

Publication number: CN101425339B
Application number: CN2008102041208A
Authority: CN
Inventors: 王光春
Original assignee: Shanghai Beiling Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2008-12-05
Filing date: 2008-12-05
Publication date: 2010-12-29
Anticipated expiration: 2028-12-05
Also published as: CN101425339A

Abstract

The invention discloses a sense amplifying circuit for a high-capacity EEPROM memory, which comprises a first current source ISO and an EEMOS tube that are connected in series. The source terminal of the EEMOS tube is connected with the ground, the grid electrode of the EEMOS tube is provided with a fixed voltage, the drain terminal of the EEMOS tube outputs electric potential through an output circuit, and the drain terminal of the EEMOS tube is also connected with the ground through a parasitic capacitance Cp. The invention also comprises a lead-out circuit and a comparison circuit that areconnected in series. The lead-out circuit is arranged between the EEMOS tube and the first current source ISO. The input end of the comparison circuit is connected with the output end of the lead-outcircuit, and the output end of the comparison circuit is connected with the input end of the output circuit. The invention can detect whether the EEMOS is conducted or cut off by leading out and comparing the current flowing through the EEMOS, thereby the stored data is read out and the sense amplifying speed of the high-capacity EEPROM memory is significantly improved without being limited by the maximum allowable current of a memory module.

Description

A kind of reading circuit for large capacity EEPROM memory

Technical field

The present invention relates to a kind of sense amplifier circuit of memorizer, relate in particular to a kind of reading circuit for large capacity EEPROM memory.

Technical background

EEPROM is a kind of memory circuit, and it is by making (under the certain grid voltage) conducting of EE metal-oxide-semiconductor or ending and store digital signal " 1 " or " 0 ".See also Fig. 1, the schematic diagram of the eeprom memory sense amplifier circuit of prior art, when reading storage, the most frequently used method is suitable constant current source of design, is added in the drain terminal of EE MOS, adds fixedly voltage on the grid of EE MOS, when pipe ends, do not have electric current to flow through from pipe, all electric current is used for the stray capacitance Cp of EE array is charged, and output potential is finally near VDD; When the pipe conducting, because the saturation current of pipe is greater than the electric current of reading to put constant current source, output potential is a lower current potential, less than 1/2nd of VDD.The output level of sense amplifier circuit just converts digital signal " 0 " and " 1 " to through after the anti-phase shaping.

The problem of above sense amplifier circuit is: owing to require to read to put the saturation current of constant current source electric current less than EE MOS, otherwise the part that is higher than EE MOS saturation current can be charged to stray capacitance Cp, make and read to put output level near VDD, data " 1 " can be mistaken for " 0 ", so when memory size becomes big, when thereby stray capacitance became big, the required duration of charging of sense amplifier circuit was elongated, also was that read frequency can reduce.

Summary of the invention

The objective of the invention is to overcome the defective of prior art, and a kind of reading circuit for large capacity EEPROM memory is provided, it can realize increasing substantially the reading the speed of putting of high capacity eeprom memory and the restriction that is not subjected to the storage unit maximum allowed current.

The technical scheme that realizes above-mentioned purpose is: a kind of reading circuit for large capacity EEPROM memory, the first current source ISO that comprises series connection, the EEMOS pipe, the source end ground connection of described EEMOS pipe, add fixedly voltage on the grid, drain terminal is by an output circuit output potential, the drain terminal of this EEMOS pipe is also by a stray capacitance Cp ground connection, wherein, what comprise also that a series connection connects draws circuit and comparator circuit, the described circuit of drawing is arranged between the described EEMOS pipe and the first current source ISO, the input end of described comparator circuit links to each other with described output terminal of drawing circuit, and output terminal links to each other with the input end of described output circuit.

Above-mentioned reading circuit for large capacity EEPROM memory, wherein, the described circuit of drawing comprises PMOS pipe P1, the 2nd PMOS pipe P2 and NMOS pipe N1, the described first current source ISO links to each other with the drain terminal of the 2nd PMOS pipe P2 with PMOS pipe P1 respectively, the source end of described PMOS pipe P1 links to each other with the drain terminal of EEMOS pipe and the grid of PMOS pipe P1 respectively, the grid of the one PMOS pipe P1 links to each other with the grid of described the 2nd PMOS pipe P2, the source end of the 2nd PMOS pipe P2 links to each other with the drain terminal of described NMOS pipe N1, the source end ground connection of NMOS pipe N1, grid with output signal to described comparator circuit after its drain terminal links to each other.

Above-mentioned reading circuit for large capacity EEPROM memory, wherein, described comparator circuit comprises the second current source IS1 and the 2nd NMOS pipe N2 that is connected in series, the source end ground connection of described the 2nd NMOS pipe N2, grid links to each other with described output terminal of drawing circuit, and drain terminal links to each other with output circuit with the described second current source IS1 respectively.

The invention has the beneficial effects as follows: sense amplifier circuit of the present invention changes traditional sense amplifier circuit and directly detects EE MOS drain terminal voltage method, to detect EE MOS be conducting or end by the method for drawing and relatively flow through the electric current of EE MOS, and then read the data of storage, can increase substantially the reading the speed of putting of high capacity eeprom memory and be not subjected to the restriction of storage element maximum allowed current; And the electric current of current source can be greater than the maximum saturation electric current of storage unit.

Description of drawings

Fig. 1 is the schematic diagram of the eeprom memory sense amplifier circuit of prior art;

Fig. 2 is the circuit theory diagrams of reading circuit for large capacity EEPROM memory of the present invention.

Embodiment

The invention will be further described below in conjunction with accompanying drawing.

See also Fig. 2, there is shown a kind of reading circuit for large capacity EEPROM memory of the present invention, the first current source ISO and the EEMOS pipe that comprise output circuit 3, series connection, adding fixedly on the source end ground connection of EEMOS pipe, the grid, voltage, drain terminal pass through a stray capacitance Cp ground connection, what comprise also that a series connection connects draws circuit 1 and comparator circuit 2, drawing circuit 1 is arranged between the EEMOS pipe and the first current source ISO, the input end of comparator circuit 2 links to each other with the output terminal of drawing circuit 1, and output terminal links to each other with the input end of output circuit 3.

Draw circuit 1 and comprise PMOS pipe P1, the 2nd PMOS pipe P2 and NMOS pipe N1, the first current source ISO links to each other with the drain terminal of the 2nd PMOS pipe P2 with PMOS pipe P1 respectively, the source end of the one PMOS pipe P1 links to each other with the drain terminal of EEMOS pipe and the grid of PMOS pipe P1 respectively, the grid of the one PMOS pipe P1 links to each other with the grid of the 2nd PMOS pipe P2, the source end of the 2nd PMOS pipe P2 links to each other with the drain terminal of NMOS pipe N1, and a NMOS manages source end ground connection, the grid of N1 and outputs signal to comparator circuit 2 after its drain terminal links to each other.

Comparator circuit 2 comprises the second current source IS1 and the 2nd NMOS pipe N2 that is connected in series, the source end ground connection of the 2nd NMOS pipe N2, and grid links to each other with the output terminal of drawing circuit 1, and drain terminal links to each other with output circuit 3 with the second current source IS1 respectively.

Output circuit 3 comprises continuous the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3, the 3rd PMOS pipe P3 all links to each other with the output of comparator circuit 2 with the grid of the 3rd NMOS pipe N3, the source end ground connection of the 3rd NMOS pipe N3, the drain terminal of the source end of the 3rd PMOS pipe P3 and the 3rd NMOS pipe N3 all meets output Dout, and the drain terminal of the first current source ISO, the second current source IS1 and the 3rd PMOS pipe P3 all meets voltage VDD.

Principle of work of the present invention is: reading the discharge stream source still is the first current source ISO, but in the solution of the present invention, the size of reading the discharge stream source is not guaranteed adequate food by EEMOS and the restriction of electric current, so when thereby the big stray capacitance Cp of memory capacity change is big, can improve the electric current of the first current source ISO according to the requirement of read-out speed to arbitrary value.Can charge to stray capacitance Cp with bigger electric current like this, but after the electric capacity charging was finished, the steady-state current that finally flows through PMOS pipe P1 then equaled the saturation current of EEMOS pipe.Then the electric current of PMOS pipe P1 is mirrored onto the 2nd PMOS pipe P2 in succession, the one NMOS manages N1, the 2nd NMOS manages N2, (supposing three's breadth length ratio), and and the second current source IS1 compare, the second current source IS1 electric current is the constant current source of the suitable size of a setting, requirement is less than the maximum saturation electric current of the EEMOS pipe maximum leakage current greater than the EEMOS that ends, so when the EEMOS pipe is opened, the saturation current of EE metal-oxide-semiconductor is mirrored onto the 2nd NMOS pipe N2, because this electric current is greater than the second current source IS1, thus Vout be pulled down near 0V, so Dout output " 1 ".And when the EE metal-oxide-semiconductor ends, manage the electric current of P1 near 0 by a PMOS, the electric current of the 2nd NMOS pipe N2 is also near 0, Vout voltage can be drawn high VDD so, so Dout is output as " 0 ", among the present invention, the first current source ISO promptly reads the discharge stream source can make constant current source, it also can be non-constant current source, and the electric current of current source can be greater than the maximum saturation electric current of storage unit, and the present invention flows through the electric current of storage unit by detection but not the storage unit output end voltage is read the data of storage.

Among the present invention, to compare in order in the ratio of 1:1 electric current being drawn with the second current source IS1, need to make that the 2nd PMOS pipe P2 and PMOS pipe P1 are measure-alike, the 2nd NMOS pipe N2 and NMOS pipe N1's is measure-alike.

When implementing, in order to reduce to draw current drain or other purposes with comparator circuit, the 2nd PMOS manages P2, the one NMOS manages N1, the size of the 2nd NMOS pipe N2 can be adjusted as required, the electric current of adjusting back the 2nd NMOS pipe N2 equals the electric current of PMOS pipe P1 * (the 2nd PMOS pipe P2 breadth length ratio/PMOS pipe P1 breadth length ratio) * (the 2nd NMOS pipe N2 breadth length ratio/NMOS pipe N1 breadth length ratio), and this moment, the electric current of the second current source IS1 also will be by same proportional zoom.

In sum, the sense amplifier circuit scheme that the present invention proposes changes traditional sense amplifier circuit and directly detects EE MOS drain terminal voltage method, to detect EE MOS be conducting or end by the method for drawing and relatively flow through the electric current of EE MOS, and then read the data of storage, can increase substantially the reading the speed of putting of high capacity eeprom memory and be not subjected to the restriction of storage element maximum allowed current.

Though through the present invention is described in conjunction with specific embodiments, for the skilled personage in present technique field, according to substituting of making of narration above, revise with variation will be conspicuous.Therefore, such substituting, in the spirit and scope that modifications and variations fall into attached claim the time, should be included among the present invention.

Claims

1. reading circuit for large capacity EEPROM memory, the first current source IS0 that comprises series connection, the EEMOS pipe, the source end ground connection of described EEMOS pipe, add fixedly voltage on the grid, drain terminal is by an output circuit output potential, the drain terminal of this EEMOS pipe is also by a stray capacitance Cp ground connection, it is characterized in that, what comprise also that a series connection connects draws circuit and comparator circuit, the described circuit of drawing is arranged between the described EEMOS pipe and the first current source IS0, the input end of described comparator circuit links to each other with described output terminal of drawing circuit, and output terminal links to each other with the input end of described output circuit;

The described circuit of drawing comprises PMOS pipe P1, the 2nd PMOS pipe P2 and NMOS pipe N1, the described first current source IS0 links to each other with the drain terminal of the 2nd PMOS pipe P2 with PMOS pipe P1 respectively, the source end of described PMOS pipe P1 links to each other with the drain terminal of EEMOS pipe and the grid of PMOS pipe P1 respectively, the grid of the one PMOS pipe P1 links to each other with the grid of described the 2nd PMOS pipe P2, the source end of the 2nd PMOS pipe P2 links to each other with the drain terminal of described NMOS pipe N1, the source end ground connection of NMOS pipe N1, grid with output signal to described comparator circuit after its drain terminal links to each other;

Described comparator circuit comprises the second current source IS1 and the 2nd NMOS pipe N2 that is connected in series, the source end ground connection of described the 2nd NMOS pipe N2, grid links to each other with described output terminal of drawing circuit, and drain terminal links to each other with output circuit with the described second current source IS1 respectively.