CN101425329B - Semiconductor storage device - Google Patents

Abstract

The invention discloses a semiconductor memory device. It is provided with: a sense amplifier/write buffer (6) for data lines connected to the data lines DL and XDL of the memory array (1), and a dummy data line DDL and XDDL connected to the dummy memory array (2). A sense amplifier control signal generation logic circuit is used for the data line. The sense amplifier (6) is activated by the output signal of the logic circuit (7). Therefore, in a semiconductor memory device such as a dynamic random access memory (DRAM), which amplifies and reads dynamic data using bit lines, high-speed access can be realized, and various memory specifications can be easily realized.

Description

semiconductor storage device

technical field

The present invention relates to a semiconductor memory device including a dynamic random access memory (DRAM) or the like.

Background technique

In recent years, increasing the speed of semiconductor memory devices has become an important issue, and especially increasing the speed of a mixed memory used in a system LSI has become an important issue. A technique for theoretically determining the timing of amplifying data on a bit line read from a memory cell in a sense amplifier by using a replica circuit is one means for solving this technical problem. With the help of this technology, the time tolerance can be optimized, and at the same time, it can cope with the influence of external conditions, process deviation, etc.

FIG. 15 shows a circuit configuration including a replica circuit of a conventional DRAM. The circuit structure includes: a memory cell MC composed of a transistor and a capacitor, word lines WL0, WL1, bit line pairs BL0~BLn/XBL0~XBLn, the bit line pair BL0~BLn/XBL0~XBLn Sense amplifiers SA0-SAn for amplifying data, dummy memory cells DMC, dummy word line DWL, dummy bit line pair DBL/XDBL, data detection circuit 201 for detecting data of the dummy bit line pair DBL/XDBL and generating a signal, The signal generation circuit 202 is controlled by SA which activates the sense amplifiers SA0-SAn (see, for example, Patent Document 1).

The core operation of the conventional semiconductor memory device configured as above will be described using the timing chart of FIG. 16 . First, when there is an access request to the DRAM, the selected word line WLO is activated, and charges from the memory cells are transferred to the bit lines BL0-BLn. Since the dummy word line DWL is also activated at this time, charges are also transferred to the dummy bit line DBL. The charge transfer operation will cause the potential level of the dummy bit line DBL to change. If the change value exceeds the threshold of the data detection circuit 201, the SA control signal generating circuit 202 is activated to generate the SA control signal SEN. The sense amplifier SA is activated by this signal and can amplify the bit line pair BL/XBL to a desired potential.

By theoretically determining the timing until bit line data is amplified by using the dummy memory cells in this way, circuit malfunction can be eliminated and timing can be optimized, so that the timing operation can be accelerated.

Patent Document 1: Japanese Laid-Open Patent Publication JP-A-6-176568

Contents of the invention

However, a problem with the conventional configuration is that, when the electric charge is used to detect the level, the correct circuit operation cannot be performed unless the potential change amount exceeds the threshold value. In particular, in the case of a very small capacity such as a memory cell, the above-mentioned problems cannot be ignored due to the influence of process variation, leakage current, and the like.

When the set threshold exceeds, for example, the threshold of a transistor, it generally becomes a very large potential compared with the potential change from the memory cell to the bit line. For example, in order to reduce the amount of charge in dummy memory cells, reduce the parasitic capacitance of bit lines, etc., it is necessary to make a layout structure that is very different from that of a normal memory cell array. If so, it is difficult to generate the correct timing to activate the sense amplifier as a replica circuit. This is also the problem.

In the case of reading a small potential difference using a reference potential, etc., it is necessary to ensure that the design can cope with the reference potential of the process variation and external conditions when designing the circuit. An additional amount of area is reserved for laying out the reference circuitry. This is also the problem.

In a circuit structure such as DRAM that requires three types of memory cell operations: 1) charge readout operation, 2) sensing, re-storage operation, and 3) precharge operation, even if only the charge readout operation is increased in speed, the It does not have any great effect on speeding up the operation of the memory cell as a whole, nor does it have any big effect on speeding up access.

For example, in a static random access memory (SRAM) circuit structure, data is read by transferring current to a bit line. However, DRAM is different from SRAM. DRAM uses electric charges to store data in capacitors. The number of memory cells connected to a bit line is limited by the capacitance ratio of the capacitance of the memory cells to the parasitic capacitance of the bit line and the sensitivity of the sense amplifier. Therefore, when the memory capacity is lined up by freely changing the number of memory cells connected to the bit lines, that is, the number of word lines (for example, the number of word lines is 16 to 512, When the number of bit lines is 512, the memory capacity can be expanded in a variety of ways between 8KB and 256KB), even if a trade-off is considered between using a replica circuit to generate the optimal sense amplifier activation timing corresponding to the memory capacity and The extra amount of area for duplicating the circuit is not expected to have much effect.

Moreover, in the case of a hybrid memory, especially a hybrid DRAM, which has a large memory capacity and needs to be developed in various specifications, whether it is from the stability of the circuit operation or the reduction of the circuit area, it is not easy. It is more efficient to change the number of memory cells connected to a bit line by changing the number of memory arrays containing a bit line than to change the number of memory cells connected to a bit line. Therefore, compared with theoretically determining the activation timing of a sense amplifier that amplifies a bit line, the activation timing of a sense amplifier that amplifies a data line whose wiring length or charge greatly varies with the memory capacity is determined theoretically. , is not only an important issue to achieve high speed, but also an important issue that can easily realize various memory specifications.

The present invention has been researched and developed to solve the above-mentioned problems, and its purpose is to provide a readout method for amplifying the data line that changes according to the memory capacity and has the heaviest load from the point of view of the access time in theory. The start-up timing of the amplifier realizes high-speed access, shortens the access time, and can easily realize semiconductor storage devices of various memory specifications.

In order to solve the above problems, the semiconductor storage device of the present invention includes: a memory cell, a word line and a bit line connected to the memory cell, a first sense amplifier connected to the bit line, a dummy memory cell, and the a dummy bit line connected to the dummy memory cell, a second sense amplifier connected to the dummy bit line, a data line connected to the first sense amplifier, a third sense amplifier connected to the data line, A dummy data line connected to the second sense amplifier, and a logic circuit connected to the dummy data line. The output signal of the logic circuit is the input signal to activate the third sense amplifier.

The logic circuit detects that the static data generated in the second sense amplifier that amplifies the dynamic data read to the dummy bit line exceeds the conductance of the transistor by using the potential on the dummy data line. The on/off potential and the output signal are used as the input signal for starting the third sense amplifier.

In this way, with a replica circuit configuration at the timing of generating the third sense amplifier that amplifies the data line by using the potential level on the dummy data line that is amplified and transferred by the second sense amplifier, it is possible to generate The optimal transfer time for a data line that varies greatly in memory capacity and load.

In the structure in which the second sense amplifier causes a current to flow into the dummy data line, and the logic circuit detects the current, there is no possibility of malfunctioning of the circuit that exceeds the threshold value of the detection circuit, and the layout structure of the dummy circuit portion does not There is a large variation, therefore, it will not be affected by deviations in the process, external conditions, etc.

Because the word line connected to the dummy memory cell and the word line connected to the memory cell are the same wiring, there is no need to set an additional area of a replica circuit. Since the time is generated by starting at a place close to the storage unit, the time error can be made small.

The dummy memory cell is provided adjacent to the row decoder including the word line driver, and has a delay circuit that adjusts the output timing of the logic circuit. In this way, access can be realized by generating the activation timing of the third sense amplifier at the earliest. At the same time, since the delay circuit can be used to finely adjust the start-up timing of the third sense amplifier, malfunctions caused by premature timing can be prevented.

In the structure in which two or more second sense amplifiers are connected to dummy data lines by switches, when the threshold magnitude of the logic circuit and the threshold magnitude of the third sense amplifier are, for example, 4:1, the four first sense amplifiers By connecting the two sense amplifiers together, the optimum start-up moment of the third sense amplifier can be realized.

A logic circuit having a function of taking a logical sum of two or more dummy data lines whose data is the same logical value is included. In this way, by using the logical sum of the dummy data lines to generate the start-up timing of the third sense amplifier, even if an error signal is transferred to the dummy data line, there is no possibility that the start-up timing signal of the third sense amplifier is not generated. unpleasant sight.

By adopting a redundant structure, when a word line, a memory cell connected to the word line, or a dummy memory cell is defective, it is also possible to save the memory by replacing it with a redundant word line.

There is a device for reading the data of dummy memory cells to the outside, so that it can be judged whether the replica circuit used for the data line is good or not.

As described above, according to the present invention, it is possible to provide a high-speed circuit by theoretically determining the start-up timing of the sense amplifier which amplifies the data line which varies with the memory capacity and has the heaviest load from the point of view of the access time. access, shorten the access time, and can easily realize semiconductor memory devices of various memory specifications.

A brief description of the drawings

FIG. 1 is a block diagram showing the main configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing specific circuit structures of the memory array, the dummy memory array and the row decoder in FIG. 1 .

FIG. 3 is a circuit diagram showing a specific circuit configuration of a data line sense amplifier/write buffer in FIG. 1. FIG.

FIG. 4 is a circuit diagram showing a specific circuit configuration of a data line sense amplifier control signal generation logic circuit in FIG. 1 .

FIG. 5 is a timing chart showing a data read operation of the semiconductor memory device in FIG. 1. Referring to FIG.

6 is a circuit diagram showing a modified example of the data line sense amplifier control signal generation logic circuit of FIG. 4 .

FIG. 7 is a block diagram showing a modified example of the dummy memory array in FIG. 2. Referring to FIG.

FIG. 8 is a block diagram showing another modification of the dummy memory array in FIG. 2 .

9 is a block diagram showing a main configuration of a semiconductor memory device in a modified example of the first embodiment of the present invention.

FIG. 10 is a circuit diagram showing a specific circuit configuration of the sense amplifier control generation logic circuit for data lines in FIG. 9 .

11 is a block diagram showing a specific circuit configuration of a memory array, a dummy memory array, and a row decoder of a semiconductor memory device in a second embodiment of the present invention.

12 is a timing chart showing a data write operation of the semiconductor memory device in the third embodiment of the present invention.

13 is a block diagram showing the main configuration of a semiconductor memory device in a modification of the third embodiment of the present invention.

14 is a block diagram showing the main configuration of a semiconductor memory device in a fourth embodiment of the present invention.

FIG. 15 is a block diagram showing the main structure of a conventional semiconductor memory device.

FIG. 16 is a timing chart showing the circuit operation of the semiconductor memory device of FIG. 15 .

Detailed ways

Preferred embodiments of the present invention will be described with reference to the drawings.

(first embodiment)

FIG. 1 is a block diagram showing the main configuration of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 1 is a memory array including: a memory cell composed of a transistor and a capacitor, a word line and a bit line connected to the memory cell, and a sense amplifier connected to the bit line. 2 is a dummy memory array, including: a dummy storage unit made of a transistor and a capacitor (it can be the same circuit structure as the above storage unit made of a transistor and a capacitor, or it can be a circuit different from the above storage unit structure), a word line and a dummy bit line connected to the dummy memory cell, and a sense amplifier connected to the dummy bit line. 3 is a row decoder for selecting and activating word lines connected to memory cells and dummy memory cells. 4 is a precharge circuit, which precharges the data line pair DL<m:0>/XDL<m:0> for data access to the memory cell 1 . 5 is a precharge circuit, which precharges the DDL/XDDL of the dummy data line used for data access to the dummy memory cell 2 . 6 is a circuit block including a write buffer for writing data into the data line pair DL<m:0>/XDL<m:0> and a data line sense amplifier for amplifying when reading data (data line with sense amplifier/write buffer). 7 is a data line sense amplifier control signal generation logic circuit, which generates a signal for activating the data line sense amplifier 61 when the potential of the dummy data line DDL exceeds a certain threshold. 8 is a control circuit for controlling the operation of the memory.

FIG. 2 shows the specific circuit structure of the memory array 1 , the dummy memory array 2 and the row decoder 3 in FIG. 1 . Here, the number of memory cells connected to the bit line of the memory array 1 and the number of dummy memory cells connected to the dummy bit line of the dummy memory array 2 is determined by the capacitance between the cell capacitance and the parasitic capacitance of the bit line or the dummy bit line. The ratio, the sensitivity of the sense amplifier, and the speed required by the memory determine the number.

FIG. 3 shows a specific circuit configuration of the sense amplifier/write buffer 6 for data lines. In FIG. 3, 61 is a sense amplifier for data lines, and 62 is a write buffer.

FIG. 4 shows a logic circuit 7 for generating a data sense amplifier control signal. In FIG. 4, 71 is a NOR circuit, and 72 is a dummy write buffer.

Using the timing chart of FIG. 5, the operation of the duplication circuit of the dummy memory cell in the semiconductor memory device constructed as above will be described. First, when there is a read request for the memory, the read operation reference signal REA is generated in the control circuit 8 to transmit the input address signal to the row decoder 3, and the selected word line WL0 is activated by the decode signal. In this way, data is transferred from the memory cell MC to the bit line BL. At the same time, data is transferred from the dummy memory cell DMC to the dummy bit line DBL. Thus, the potential of the dummy bit line DBL precharged to 1/2 of the power supply voltage VDD (or high level) rises toward the low level. The ratio of the parasitic capacitance of the dummy bit line BL to the cell capacitance of the dummy memory cell DMC is then big. At the same time, the peripheral circuit read operation reference signal RE is also generated.

Next, after a predetermined time delay in order to transfer the charge from the memory cell MC and the dummy memory cell DMC, the sense amplifiers SA0-SAn connected to the bit lines BL/XBL and the dummy bit lines DBL/XDBL and The signal SEN for activating DSA0 and DSA1 becomes high level and is activated. In this way, the bit lines BL/XBL are respectively amplified to a high level or a low level. At the same time, the dummy bit line DBL is amplified to a low level. In addition, since the sense amplifiers SA0-SAn and DSA0 and DSA1 eliminate the equalization of the process pattern and the deviation of the sensing operation timing of the bit line and the dummy bit line, the sense amplifiers of the same circuit can be used. Sense amplifiers SA0 to SAn and DSA0 and DSA1 may use sense amplifiers having different circuit structures, but this is needless to be discussed.

The column switch signal CS0 for transferring the data of the bit line BL/XBL and the dummy bit line DBL/XDBL to the data line DL/XDL precharged to the power supply voltage VDD, and the dummy data line DDL/XDDL becomes high level. is activated, therefore, the desired data from the bit line BL/XBL is transferred to the data line DL/XDL, and the low-level data of the dummy bit line DBL is transferred to the dummy data line DDL, which is amplified by the sense amplifier DSA0 The low-level data makes the potential of the dummy data line DDL 1/2VDD after a predetermined time elapses. Because the dummy data line DDL is connected to one input of the "NOR" circuit 71 of the sense amplifier control signal generation logic circuit 7 for data, the on/off level of the CMOS transistor connected to the input signal is 1/2VDD (In other words, the output logic of the CMOS transistor is inverted), and the other input of the "NOR" circuit 71 becomes an inversion signal of the high-level signal of the peripheral circuit read operation reference signal RE. Therefore, the output signal DACNT of the data sense amplifier control signal generating logic circuit 7 changes to a high level, and the duplication circuit operation ends.

Next, since the signal DACNT becomes high level, the data line sense amplifier 61 is activated, the data on the data lines DL/XDL are amplified, and as a result, they become high level and low level, respectively. The data of the amplified data line DL is transferred to the output DO through the buffer circuit for read operation.

Finally, the read operation reference signal REA and the peripheral circuit read operation reference signal RE become low level after a certain period of time, thereby becoming a standby state in which the internal circuit of the memory is ready for the next operation.

As mentioned above, in the case where the potential change caused by the charge transfer does not exceed the threshold value, the desired operation will not be performed a second time, and the data used to amplify the bit line whose load capacitance has been fixed At the activation timing of the sense amplifier, for example, a predetermined delay time such as a transistor delay circuit is used, and the sense amplifier is used to transfer data through a current, so that the desired potential can be obtained after a certain period of time. In the case where the load capacitance varies greatly due to the memory capacity, by using dummy bit lines, sense amplifiers, column switches, dummy The output signal of a replica circuit composed of a data line and a simple level detection circuit such as a "NOR" circuit, for example, when the memory capacity becomes smaller, that is, the data line becomes shorter and the circuit load becomes lighter. Since the time for the dummy data line to reach the potential of 1/2VDD is shortened, the start-up of the sense amplifier for the data line is shortened, so that data can be output at high speed, that is, high-speed access can be realized. For example, when the memory capacity becomes larger, that is, when the load on the data line becomes heavier, the specified time becomes longer in order to enlarge the data line. It is an effective means to realize stable and high-speed start-up of the data line sense amplifier by using the timing generating circuit of the circuit.

In addition, in FIG. 4, the NOR circuit 71 is used, but any circuit configuration that can be realized by simple circuit operations such as on/off functions of CMOS transistors can be used. This is a matter of course. In contrast to this, it is very important to optimize the timing by adding a dummy data line with a load transistor similar to that of the data line sense amplifier 61 .

By configuring the memory cell and the dummy memory cell with one transistor and one capacitor, it is effective for speeding up when the accumulated data is dynamic data. However, any memory cell may be configured as long as dynamic data is accumulated therein, and may include, for example, two transistors and two capacitors.

By using the same word line as the word line connected to the memory cell and the dummy memory cell, it is not necessary to reconfigure the dummy word line for the replica circuit. Therefore, the circuit area can be reduced, and at the same time, because it is the same word line, the gates of the access transistors of the memory cell and the dummy memory cell can be activated at the same timing, so that the data is transferred to the bit line and the dummy bit. The moment of the line is the same moment. That is to say, the operation timing as the replica circuit becomes the optimum timing. As for the refresh required for the capacitor cell, since it is connected to the same word line, it is possible to refresh the dummy memory cell at the same time as the memory cell is refreshed. As a result, since the dummy memory cell does not require a special refresh operation just for it, only the dummy memory cell does not require special refresh, so it is a problem to have the word lines connected to the memory cell and the dummy memory cell share the same word line. effective measures. In addition, a structure in which memory cells and dummy memory cells are connected to different word lines is also possible, of course.

The bit line and the dummy bit line, and the data line and the dummy data line are respectively arranged in parallel, so compared with the case where the bit line and the dummy bit line, the data line and the dummy data line are vertically arranged, the load and data Line loads are equal. Therefore, since the generation timing of the replica circuit including the dummy data line can optimize the amplification timing of the data line, it is effective to separately arrange the bit line and the dummy bit line, and the data line and the dummy data line in parallel. In addition, in this specification, the relationship between the bit line and the data line is mentioned, but as long as it is a replica circuit structure after becoming static data, even the data line connected to the bit line through the switch, the data line connected to the data line through the switch The replica circuit structure of is also possible.

As shown in FIG. 1, when the dummy memory array 2 is provided adjacent to the row decoder 3, by including a delay for adjusting the output timing of the output signal DACNT of the data sense amplifier control signal generation logic circuit 7 circuit, compared with dummy memory cells other than here, for example, compared with the situation where the dummy memory cells are farthest away from the row decoder 3, the circuit operation becomes the fastest operation, so it is possible to make the output the fastest time. Therefore, it is effective for speeding up the memory. Furthermore, as a countermeasure to prevent malfunction when the output timing is too early, it is most effective to arrange a delay circuit that finely adjusts the timing. In addition, since the delay circuit can be adjusted using a fuse, a nonvolatile memory, or the like without exchanging a mask, etc., it is also an effective means from this point of view.

By connecting adjacent capacitors of dummy memory cells together, the amount of charge sensed onto the bit line is increased. Therefore, stable sense amplifier operation can be realized. Therefore, it is effective as an operation guarantee of a replica circuit. In addition, of course, any configuration may be used as long as the capacitor of the dummy memory cell is larger than the capacitor of the memory cell. In the case of short-circuiting the electrodes of a capacitor, it is also possible to form a new capacitor.

As shown in FIG. 1, by arranging the same number of memory arrays 1 and dummy memory arrays 2, it is possible to start the copy circuit from a place that conforms to the position of each physical array with the selected word line, so it is the best way to generate effective means of time. Furthermore, by sharing a word line between the memory array 1 and the dummy memory array 2, the dummy memory cell and memory cell data are read from the selected word line, and an optimal timing can be generated. Furthermore, if it is made into a structure in which the dummy memory array 2 is arranged only at one place, for example, the obstacle of timing optimization can be eliminated, and the process deviation caused by the uneven pattern of the memory cells can also be eliminated, and there is no dummy memory array 2. The area of the memory array is voided, which eliminates the extra amount of area.

Make the dummy memory cell consist of a transistor, and connect the source node of the transistor to the power supply. In this way, there is no need to consider the defect of the capacitor in the dummy memory cell, and there is no need to write and read the dummy memory cell. The data needed at the time, so it is an effective means. In addition, the dummy storage unit is formed by one transistor here, but it is also possible to form the dummy storage unit by two or more transistors, so there is no further discussion.

As shown in FIG. 6, the output side of the logic circuit 7 includes a latch circuit 73. Therefore, even if the column switch connected to the dummy sense amplifier is turned off, during the high level period, the peripheral circuit reads the operation reference signal RE at The output data can also be latched during the high level period, so it is an effective means.

Next, a configuration in which two or more sense amplifiers are connected to dummy data lines by switches will be described with reference to FIG. 7 . As shown in FIG. 7, the two sense amplifiers DSA0 and DSA1 connected to the dummy data line DDL/XDDL are connected through N-channel transistors 20, 21, 22, and 23 whose gates are respectively controlled by the control signal DCS. Structure. Therefore, the dummy data line DDL/XDDL of the dummy memory cell can read data twice as fast as the data line DL/XDLX of the memory cell. As a result, when the potential difference required for amplifying the data line DL/XDL by the data line sense amplifier 61 and the ON/OFF required for the ON/OFF of the NOR circuit 71 of the data sense amplifier control signal generation logic circuit 7 When the potential difference is 1:2, it is effective to make the generation timing of the data line sense amplifier activation signal of the replica circuit equivalent to the amplification timing of the data line sense amplifier 61 .

Since the control signal of the column switch of the sense amplifier is different from the control signal of the column switch of the dummy sense amplifier, the column switch of the sense amplifier can be controlled independently of the column decoding input, so it is easy Connect multiple dummy sense amplifiers to one dummy data line. Even if the number of dummy sense amplifiers is changed, it is effective because it does not affect the driving timing, driving capability, etc. of the column switches of the sense amplifiers.

Next, a structure in which the dummy data line is not a complementary line and the wiring arranged adjacent to the dummy data line is a power supply line will be described using FIG. 8 . As shown in FIG. 8, the dummy data line DDL is connected to sense amplifiers DSA0 and DSA1 through N-channel transistors 20 and 21 whose gates are driven by column switching signals CS0 and CS1. N-channel transistors 22 and 23 connected to one sense amplifier DSA0 and DSA1 have their gates VSS and their sources open (not connected). In this structure, since the complementary side of the dummy data line is the VSS power supply line, it not only has a shielding effect on the read operation of the dummy data line required for the operation of the replica circuit, but also has a dummy data line with a heavy load. It is hoped that the current consumed will be reduced. In addition, the description is the VSS power line, of course, the VDD power line is also possible. In the case of using the VDD line, it is possible to take measures such as connecting the source node of the transistor and connecting the gate node to the VSS power supply.

In addition, after combining the above various methods, further good effects can be received. This is a matter of course.

(Modification of the first embodiment)

9 is a block diagram showing a main configuration of a semiconductor memory device in a modified example of the first embodiment of the present invention. In particular, the data sense amplifier control signal generation logic circuit 9 is different from that of the first embodiment, and a specific circuit configuration is shown in FIG. 10 . In FIG. 10, 91 is a "NOR" circuit group, 92 is a dummy write buffer group, and 93 is an "OR" circuit, and the logical sum of a plurality of dummy data lines DDL<0> to DDL<n> is used as The control signal DACNT of the sense amplifier 61 is used for the data line.

According to this modified example, by taking the logical sum of a plurality of dummy data lines, even if one of the dummy memory cells fails, the data from the remaining dummy data lines can be transferred to the data sense amplifier control signal generating logic. The circuit 9 is therefore an effective means for realizing the desired operation of the replica circuit. Usually, the number of dummy data lines can be determined in consideration of the relationship between the occurrence rate of defects in the process and the additional amount of circuit area. Moreover, it is a matter of course that the data of two or more dummy data lines have exactly the same logical value.

In addition, a further favorable effect can be obtained by combining this embodiment with the first embodiment. This is a matter of course.

(second embodiment)

FIG. 11 is a block diagram showing the main configuration of a semiconductor memory device in a second embodiment of the present invention. In FIG. 11, 10 and 11 denote a memory array including a redundant word line RWL0, and a dummy memory array, respectively. 12 is a row decoder including a redundant decoding circuit capable of switching to a redundant word line when the memory array 10 and the dummy memory array 11 are defective.

In the semiconductor storage device configured as above, when a memory cell connected to WL0 of the memory array 10 has a defect, for example, specifying the address of a redundant word line using a fuse function, etc., if the access just hits the defect The word line WL0 is controlled by the redundant decoding circuit to switch to access the dummy redundant word line RWL0 to transfer data from the redundant memory cells to the bit line BL. In this way, defective cells can be rescued.

Similarly, when the dummy memory cell connected to WL0 of the dummy memory array 11 has a defect, the redundant decoding circuit performs control to switch to accessing the dummy redundant word line RWL0, so the dummy can also be saved. Storage unit 11.

In this way, by applying the currently existing redundant circuits including redundant memory cells and redundant word lines to the dummy memory array, even if the dummy memory cell has a defect, it can be rescued, so not only the duplication circuit can be realized In addition, it is also possible to effectively utilize the useless space in the dummy memory array by means of setting redundant memory cells. Therefore, it is an effective means.

In addition, when this embodiment is combined with the first embodiment and the modified example of the first embodiment, further favorable effects can be obtained. This is a matter of course.

(third embodiment)

Next, a third embodiment of the present invention will be described. The main structure of the semiconductor memory device according to this embodiment is shown in FIGS. 1 to 4 , and the data writing operation to the dummy memory array will be described with reference to the timing chart of FIG. 12 .

First, when there is a write request to the memory, the write operation reference signal WEA is generated in the control circuit 8, and the peripheral circuit write operation reference signal WE is generated. In this way, the data input signal DI is driven by the write buffer 6, and the data is transferred to the data line DL/XDL. Simultaneously, the dummy input signal DDI is transferred from the write buffer 72 of the data sense amplifier control signal generation logic circuit 7 to the dummy data lines DDL/XDDL. The input address signal is transmitted to the row decoder 3 by the write operation reference signal WEA, and the selected word line WL0 is activated by the decoding signal. Thereafter, the data read from the memory cell and dummy memory cell connected to the selected word line WL0 to the bit line pair BL/XBL and dummy bit line DBL/XDBL is amplified by the sense amplifier activation signal SEN. Next, the column switch signal CS0 that drives the gate of the N-channel transistor that connects the data line to the sense amplifier and the dummy data line to the sense amplifier is activated to pass the data on the data line DL/XDL through the read out of the amplifier to write to the memory cell. Similarly, data on dummy data lines DDL/XDDL is also written into dummy memory cells through sense amplifiers.

Finally, the write operation reference signal WEA and the peripheral circuit write operation reference signal WE become low level after a certain period of time, so that the internal circuit of the memory becomes ready for the next operation.

As described above, it has the following function, that is, when a write request comes, write the desired data into the memory cell, and at the same time, write the desired data into the dummy memory cell. In this way, it is possible to The data from the dummy memory cell to the dummy bit line, the sense amplifier, and the dummy data line is made into a desired data value. Therefore, it is an effective means. Since the dummy memory cell is initialized or the desired data is written simultaneously with writing to the memory cell, it is an effective means to eliminate excessive operation of the circuit.

The input signal DDI of the write buffer 72 connected to the dummy data line DDL/XDDL is connected to the VDD power supply or the ground potential. After doing so, it can be visually written without adding a new input signal to the memory. Since it is required to write fixed data into a dummy memory cell connected to a desired address, it is also effective from the viewpoint of reducing the number of memory pins.

The logic value of the input signal DDI of the write buffer 72 connected to the dummy data line DDL/XDDL can be changed from the outside, and even if the logic level of the input signal DDI is changed, the data can be generated using the sense amplifier control signal. The logic level of the output signal DACNT of the logic circuit 7 does not change when it is activated. Although not shown, it has, for example, the function of making two signal paths to one inverter by the selection circuit and switching the potential level of the input signal DDI, so it is possible to eliminate dummy memory cells caused by process conditions, external conditions, etc. Unbalanced read operation (for example, low level is easier to read than high level, etc.); the stable operation of the replica circuit including the dummy memory cell can be realized by unifying the data value, for example, which is easy to read.

Make it have the function of activating all the word lines, the sense amplifiers connected to all the dummy memory cells, the sense amplifiers connected to all the dummy memory cells, and the switches connected to the dummy data lines, and the copy circuit operates The desired data is written into the dummy memory cells at the same time. Therefore, for example, it can be efficiently performed during the initial sorting of the memory, during spare time in standby mode, and the like. By setting this function as the mode setting function, in the time other than the batch write operation that has been set by the mode, for example, if the write buffer that writes to the dummy data line is used to stop working, the When a normal write request is performed, the write operation to the dummy memory cells including the dummy data lines is restricted, thereby achieving the effect of reducing current consumption. Since it is not necessary to perform the operation simultaneously with the normal operation, for example, the operation frequency is sufficiently slowed, and the write operation to the dummy memory cell is performed with a certain margin, so that a highly stable operation of the replica circuit can be realized.

In addition, when this embodiment is combined with the above-mentioned respective embodiments, further favorable effects can be obtained. This is a matter of course.

(Modification of the third embodiment)

13 is a block diagram showing the main configuration of a semiconductor memory device in a modification of the third embodiment of the present invention. Next, the data writing operation for writing data into the dummy memory array 102 provided in the memory array 101 of the semiconductor memory device configured as shown in FIG. 13 will be described.

The flag INT that specifies the data write operation to the dummy memory cell array 102 in the mode register 111 is activated by the external control signal CNT. After the write buffer 110 is activated, it transfers the dummy data line input signal DDI to the dummy data line DDL. In the selection circuit 112, because the flag INT is at a high level, the input signal DCLK that repeats high and low levels in a certain period is selected, so that the count of the refresh counter 113 gradually increases. The address signal selected by the increment operation of the refresh count 113 is decoded in the row decoder 103, so that all the word lines are sequentially selected in the same manner as in the refresh. Like this word line action, the sense amplifier connected to the selected word line is also activated. Although not shown, the switch connecting the sense amplifier connected to the dummy memory array 102 and the dummy data line DDL is connected to the The switches on the selected sense amplifiers are also activated so that the desired data can be written into the dummy memory array 102 . This operation continues until the refresh counter 113 returns to the original value, and all data writing to the dummy memory array 102 can be completed.

For a normal refresh request, since the flag INT is in an inactive state, the refresh counter 113 operates upon receiving the refresh command signal REF.

As described above, the use of an existing memory circuit eliminates the need for a momentary large current flow operation such as a collective write operation to the dummy memory array 102, and the initialization of the dummy memory array 102 can be performed at a timing different from the normal operation. , and at the same time, the refresh operation of the memory array 101 and the dummy memory array 102 can be realized at the same time, so a very suitable circuit can be realized in terms of circuit operation, current consumption and circuit area.

In addition, as an example, the case where the write operation to the dummy memory array 102 is determined by using the mode setting of the mode register 111 is described, but as long as the write operation to the dummy memory array 102 using the refresh counter 113 can be realized, Any circuit configuration may be used as the circuit configuration for operation.

(fourth embodiment)

FIG. 14 is a block diagram showing a main configuration of a semiconductor memory device in a modified example of the fourth embodiment of the present invention. In FIG. 14, 13 is an output selection circuit. Under this circuit configuration, the output signal PDO during testing can be switched to the test output of the data output DO from the memory cell and the sense amplifier for data by using the mode selection signal MODE. The control signal generates output signals DDO of the logic circuit 7 and outputs them.

The data reading operation of the dummy memory cells of the semiconductor memory device constructed as above will be described.

When the signal DANCT becomes high level during the operation of the replica circuit shown in FIG. 5 , another output signal DDO of the data sense amplifier control signal generation logic circuit 7 also becomes high level as shown in FIG. 4 . If the mode selection signal MODE is at a high level at this time, the high level data is output to the output signal PDO.

When the mode selection signal MODE is at a low level, the output signal DO from the memory cell is output to the test output signal PDO. In this manner, it is possible to switch whether or not to output the output DDO of the data sense amplifier control signal generating logic circuit 7 .

As described above, by using the mode to select the test result of the memory, there is a means of outputting the data of the dummy memory cell to the outside, so that the defect of the replica circuit including the dummy memory cell can be inspected. As a result, it is possible to specify not only the defect of the memory cell but also the defect of the dummy memory cell, and perform memory relief measures such as redundancy relief.

In addition, the description is the case where the output DDO of the data sense amplifier control signal generation logic circuit 7 is output as it is via the selection signal, but any circuit configuration can be obtained as long as a stable external output result can be obtained by the configuration of the latch output DDO. .

When the output DDO of the data sense amplifier control signal generation logic circuit 7 is plural, by using a part or all of the data output paths, it is not necessary to use the normal output terminal during testing to confirm the data of the dummy memory cell. In particular, by adding an output terminal, data from a dummy memory cell can be read. Therefore, it is effective in terms of reducing the number of terminals of the memory and reducing the circuit area.

The data line and the dummy data line have precharge circuits respectively, and the precharge potential of the data line is different from the precharge potential of the dummy data line. An example is as follows. Assume that the precharge potential of the dummy data line is the VDD potential, and use the on/off characteristics of the transistor to generate the start-up timing of the sense amplifier that amplifies the data line, so that the precharge potential of the data line is 1. /2VDD potential, in this way, compared with the VDD precharge potential, the power consumed by many data lines in the memory can be suppressed to 1/2. The result is an effective means for low power consumption of memory.

In addition, by combining this embodiment with each of the above-described embodiments, further favorable effects can be obtained. This is a matter of course.

The semiconductor memory device according to the present invention has the ability to achieve high-speed access by theoretically determining the start-up timing of the sense amplifier that amplifies the data line that changes according to the memory capacity and that has the heaviest load from the point of view of the access time. , and can easily realize the effects of various memory specifications, and is very useful for system LSIs and the like that will mount a large number of memories with many specifications.

Claims (27)

1. A semiconductor storage device, characterized in that: include: storage unit, word lines and bit lines connected to the memory cells, a first sense amplifier connected to the bit line, dummy storage unit, a dummy bit line connected to the dummy memory cell, a second sense amplifier connected to the dummy bit line, a data line connected to the first sense amplifier, a first pre-charging circuit connected to the data line, a third sense amplifier connected to the first precharge circuit, a dummy data line connected to the second sense amplifier, a second precharge circuit connected to the dummy data line, and a logic circuit connected to the second pre-charging circuit, The output signal of the logic circuit is the input signal to activate the third sense amplifier. 2. The semiconductor storage device according to claim 1, characterized in that: The logic circuit detects that the static data generated in the second sense amplifier that amplifies the dynamic data read to the dummy bit line exceeds the conductance of the transistor by using the potential on the dummy data line. The on/off potential and the output signal are used as the input signal for starting the third sense amplifier. 3. The semiconductor storage device according to claim 1, characterized in that: A latch circuit is included on the output side of the logic circuit. 4. The semiconductor storage device according to claim 1, characterized in that: A device for latching a signal of a dummy data line which is an input of the logic circuit according to a logic value of an output signal of the logic circuit is included. 5. The semiconductor storage device according to claim 1, characterized in that: The memory cell is composed of a transistor and a capacitor, and the dummy memory cell is composed of a transistor and a capacitor. 6. The semiconductor storage device according to claim 1, characterized in that: The word line connected to the dummy memory cell is the same wiring as the word line connected to the memory cell. 7. The semiconductor storage device according to claim 1, characterized in that: The bit lines and the dummy bit lines are arranged parallel to each other, and the data lines and the dummy data lines are arranged parallel to each other. 8. The semiconductor storage device according to claim 1, characterized in that: The dummy memory cell is provided adjacent to a row decoder including a word driver, and the semiconductor memory device has a delay circuit for adjusting an output timing of the logic circuit. 9. The semiconductor storage device according to claim 1, characterized in that: Adjacent capacitors of the dummy memory cells are connected together. 10. The semiconductor storage device according to claim 1, characterized in that: For each memory array including the memory cell, the word line, the bit line, and the first sense amplifier, a memory array including the dummy memory cell, the dummy bit line, and the second sense amplifier is provided. Sense amplifiers for the dummy memory array. 11. The semiconductor storage device according to claim 1, characterized in that: The dummy storage unit is formed by a transistor, and the source node of the transistor is connected to the power supply. 12. The semiconductor storage device according to claim 1, characterized in that: It has a structure in which two or more of the second sense amplifiers are connected to the dummy data lines through switches. 13. The semiconductor storage device according to claim 12, characterized in that: A control signal of a switch connecting the data line and the first sense amplifier is different from a control signal of a switch connecting the dummy data line and the second sense amplifier. 14. The semiconductor storage device according to claim 1, characterized in that: The dummy data line is not a complementary line, and the wiring adjacent to the dummy data line is a power supply line. 15. The semiconductor storage device according to claim 1, characterized in that: The logic circuit has a function of taking a logical sum of two or more dummy data lines. 16. The semiconductor storage device according to claim 15, characterized in that: The data of the two or more dummy data lines have the same logic value. 17. The semiconductor storage device according to claim 1, characterized in that: Further includes: redundant storage unit, redundant word lines connected to the redundant memory cells, a bit line connected to the redundant storage unit, redundant dummy memory units, and A dummy bit line connected to the redundant dummy storage unit. 18. The semiconductor storage device according to claim 17, characterized in that: The logic circuit detects that the static data generated in the second sense amplifier that amplifies the dynamic data of the redundant dummy memory cell exceeds the on/off of the transistor by using the potential on the dummy data line. Cut off the potential and output the signal as the input signal to start the third sense amplifier. 19. The semiconductor storage device according to claim 1, characterized in that: Further includes: a first write buffer connected to the first precharge circuit, a second write buffer connected to the second precharge circuit, and When performing a write operation to the storage unit, data is also written into the device of the dummy storage unit. 20. The semiconductor memory device according to claim 19, wherein: The input terminal of the second write buffer is connected to a power supply or a ground potential. 21. The semiconductor storage device according to claim 19, characterized in that: The semiconductor memory device has a function that the logic value of the input data of the second write buffer can be changed from the outside, and the output logic of the logic circuit remains unchanged. 22. The semiconductor storage device according to claim 19, characterized in that: It further includes: a write-in-a-batch device for writing in all dummy memory cells together. 23. The semiconductor memory device according to claim 19, wherein: Further includes: Refresh counters to control the refresh, and A write device writes data into the dummy memory cells connected to the word line selected by the refresh counter. 24. The semiconductor storage device according to claim 1, characterized in that: It further includes reading out the output of the logic circuit to an external device. 25. The semiconductor storage device according to claim 24, characterized in that: It has a function of switching the output/non-output of the external output of the logic circuit. 26. The semiconductor memory device according to claim 24, characterized in that: When outputting from the logic circuit to the outside, part or all of the data output paths of the memory cells are used. 27. The semiconductor storage device according to claim 1, characterized in that: The precharge potential of the data line is different from the precharge potential of the dummy data line.

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