CN101420417B - Scanning circuit for data content and its scanning method - Google Patents

Abstract

The invention relates to a scanning circuit and method of a data content, store a plurality of label data by a memory circuit, and each label data corresponds to a sub rule, the memory circuit is used for receiving a first input data and outputting a first part bit in a first label data to an arithmetic circuit and receiving a second input data and outputting a second part bit of a second label data to the arithmetic circuit; the arithmetic circuit performs logic operation on the first part of bits and the second part of bits to output an operation result; a judgment circuit receives the operation result and judges whether the input data conforms to a predetermined rule according to the operation result, so that the complexity of the circuit can be saved, the cost can be saved, and the scanning efficiency can be improved.

Description

Scanning circuit for data content and its scanning method

technical field

The present invention relates to a data content scanning circuit, in particular to a network data content scanning circuit and scanning method.

Background technique

Nowadays, computer technology is more and more developed, and the transmission rate and transmission bandwidth are also improved with the advancement of technology, so the data flow that can be transmitted is also greater. Due to various factors, the data in transmission may contain viruses or advertising webpages, etc., which will slow down the processing speed of the system or even cause the system to be poisoned and fail to operate normally. Therefore, in many applications of the current system, such as network management switch (Web Switch), load balancer (Load balancer) and virus defense, etc., the content of the data will be checked one by one to avoid the above problems, which is Content scanning (contentscanning).

Please refer to FIG. 1 , which is a scanning circuit of data content in the known technology. As shown in the figure, the scanning circuit 10' includes multiple comparators 20'. Since the multiple comparators 20' are not sure where the content of the packet data to be searched is, they must scan all the contents of the packet data one by one. To ensure that there will be no scanning omissions, as shown in Figure 1, after comparing the first byte to the fifth byte of the packet data, then the second byte to the sixth byte must be compared, Therefore, usually the second byte to the fifth byte must be registered first for the next comparison. In addition, since the scanning circuit has a wide range of applications, and the classification basis of each application is different, the length of each rule (rules) will also be different. For example, when there are 10 rules that need to be scanned, but the rules The shortest length of the rule may only be two or three bytes (Bytes), but the longest rule may have dozens of bytes. Nowadays, in order to solve the above-mentioned problem that the length of each rule is different, the size of each rule is set to be constant. If a shorter rule is to be set, a mask 22' (mask) is set, and a comparator 20' is used to Comparing to confirm whether it matches the data to be scanned, not only wastes extra storage space for comparison, but also complicates circuit implementation, and requires a larger storage space for longer rules.

Therefore, the present invention proposes a scanning circuit and method for data content, which can save circuit area, and can dynamically set the length of scanning rules to increase scanning flexibility and shorten scanning time.

Contents of the invention

One of the objectives of the present invention is to provide a data scanning circuit and method to scan whether part of the input data conforms to the scanning rules, so as to save the complexity of the circuit, save the cost and improve the scanning efficiency.

One of the objectives of the present invention is to provide a data scanning circuit and method, which can dynamically set the length of scanning rules, so as to increase the flexibility of scanning.

One of the objectives of the present invention is to provide a data scanning circuit and method, which can know the position of the data conforming to the scanning rule among the plurality of input data.

The data scanning circuit and method of the present invention include a storage circuit, an arithmetic circuit and a judgment circuit. The storage circuit stores a plurality of label data, and each label data corresponds to a sub-rule. When a first input data is transmitted A first partial bit of the plurality of tag data is output to the storage circuit, and sent to the arithmetic circuit, and a second input data is sent to the storage circuit, and a second partial bit of the plurality of tag data is output, and sent to the arithmetic circuit The operation circuit logically operates the first part of bits and the second part of bits to generate an operation result, and the judging circuit receives the operation result to judge whether the input data conforms to a predetermined rule.

Description of drawings

Fig. 1 is the data scanning circuit of known technology;

Fig. 2 is a block diagram of a preferred embodiment of the present invention;

Fig. 3 is the circuit diagram of a preferred embodiment of the present invention: and

FIG. 4 is a block diagram of another preferred embodiment of the present invention.

Description of main component symbols

10' scanning circuit

20' Comparator

22' mask

10 physical layer device

20 storage circuit

22 first storage circuit

24 Second storage circuit

26 sequence units

30 arithmetic circuit

32 triggers

34 logic units

36 isolation units

40 judgment circuit

50 processing circuits

60 counting units

70 Media Access Controller

80 data scanning circuit

Detailed ways

In order to make the structural features of the present invention and the achieved effects have a further understanding and understanding, with preferred embodiments and detailed descriptions, the descriptions are as follows:

Please refer to FIG. 2 and FIG. 3 together, which are a block diagram and a circuit diagram of a preferred embodiment of the present invention. As shown in the figure, this embodiment is applied to the Internet to scan the packet data of the network, such as a web switch (Web Switch) or a load balancer (Load balancer), but the present invention is not limited to be applied to the Internet. This embodiment includes a physical layer device 10 (Physical, PHY) and a media access controller 70 (Media Access Control, MAC); the media access controller 70 includes a data scanning circuit 80 and a processing circuit 50; The scanning circuit 80 further includes a storage circuit 20 , an arithmetic circuit 30 and a judgment circuit 40 . The physical layer device 10 receives input data, and the input data includes multiple data. Since this embodiment is applied in the Internet, the input data is a packet of Internet data.

Following the above, the storage circuit 20 stores multiple batches of tag data, each batch of tag data corresponds to a sub-rule (for example: character A, symbol, etc.), each batch of tag data includes N bits of data, and each bit of data is distributed in different The address of the storage circuit 20, and the N-1 bits of the label data correspond to the same logic value, and each label data is a programmable label data for users to set. In one embodiment of storing bit data in the storage circuit 20 , the sub-rule is corresponding to the storage address of the storage circuit 20 and a value is set.

The following example illustrates that if you want to search whether the multiple input data contains ABCDE scanning rules, that is, including five sub-rules of ABCDE, the first sub-rule A corresponds to the American Standard Code for Information Interchange Code (America Standard Code for Information Interchange Code, ASCII Code) is 65, so in the storage circuit 20, the storage address 65 for storing the first label data is set to 1, and the bits of the remaining addresses (that is, addresses 0-64 and 66-255) are all set to 0, and the first label data is set to 0. The two sub-rules B correspond to ASCII Code 66, that is, in the storage circuit 20, the storage address 66 for storing the second label data is set to 1, and the bits of the other addresses (that is, addresses 0-65 and 67-255) are all set to 0 , and so on for the rest of the scan data CDE. If the data is ignored by the scanning rule, the corresponding bits are all set to 1, as shown in Figure 3, the data X is the sixth data, so the sixth bit of all storage addresses is set to 1. Because the scanning method of this embodiment takes byte as a unit, plus a byte, there are 256 combinations, so the depth of the storage circuit 20 of this embodiment is 256, that is, there are 256 addresses, and the width depends on the requirements of the scanning rule. Setting, that is, the storage bit of each address is set according to the scanning requirements.

In addition, the plurality of input data received by the physical layer device 10 will be sent to the storage circuit 20 as a read address, so that the storage circuit 20 will read the corresponding tag data according to the plurality of input data, that is, the input data They will be respectively input to the address port (address port) of the storage circuit 20, so that the storage circuit 20 respectively outputs some bits in the tag data according to the input data. Taking FIG. 3 as an example, if the first data of the input data received by the storage circuit 20 is A, since A corresponds to the storage address 65 of the storage circuit, the storage circuit 20 will output the first data in the label data according to the first data. A part of bits, that is, the data stored in the memory address 65 of the memory circuit 20 , in this embodiment, the memory circuit 20 will output 10000. If the second data of the input data is B, the storage circuit 20 will correspondingly output the data stored in the storage address 66 to obtain 01000. Wherein, a preferred embodiment of the storage circuit 20 is a static random access memory.

An arithmetic circuit 30, which sequentially receives each batch of data output by the storage circuit 20 and shifts the received data output by the storage circuit 20 according to a clock signal (Clock, CLK) and outputs it with the next batch of received storage circuit 20 The logic operation is performed on the data to generate an operation result for the judgment circuit 40 to judge. The operation circuit 30 will be described in detail below with reference to FIG. 3 . As shown in FIG. 3 , the arithmetic circuit 30 includes a plurality of flip-flops 32 and a plurality of logic units 34 , and in this embodiment the logic units 34 are AND gates. The plurality of flip-flops 32 are respectively connected in series, and the plurality of logic units 34 are respectively coupled between the plurality of flip-flops 32 to receive the plurality of data output by the storage circuit 20 and output to the coupled The plurality of flip-flops 32 . Wherein, the plurality of flip-flops 32 output the received data outputted by the storage circuit 20 according to the clock signal CLK to the logic unit 34 connected in series at the next stage. A batch of data output by the storage circuit 20 is used to generate an operation result.

The scan data is described in detail below as ABCDE. After the storage circuit 20 receives the input data, if the input data contains ABCDE, the storage circuit 20 will sequentially output the operation data 10000, 01000, 00100, 00010, 00001. That is to say, the flip-flops 32 of the arithmetic circuit 20 will respectively receive the first batch of data 10000, and will shift and output the received data to the logic unit 34 connected in series at the next stage according to the clock signal CLK. At this time, the logic unit 34 also The next batch of data will be received, and logical operations will be performed to output to the flip-flops 32 connected in series. In this embodiment, the data received by the second flip-flop 32 is 1 at this time, and will be based on the next clock signal CLK is shifted and output to the logic unit 34 connected in series at the next stage, but if the second data of the input data is not B but C, the second batch of operation data output by the storage circuit 20 will be 00100 at this time. The data received by the second flip-flop 32 in the timing operation circuit 30 will be 0, indicating that the input data does not conform to the scanning rule. That is to say, if the operation data sequentially received by the operation circuit 30 conforms to the scanning rule, the function of the operation circuit 30 is like a shift register to shift down the 1 of the first batch of operation data.

By analogy, when the input data contains ABCDE, 1 in the first batch of operation data will be shifted by five clock signals CLK, and the operation result output by the fifth flip-flop 32 will be 1, which also means Part of this batch of input data conforms to scan rule ABCDE. It can be seen that, if the operation result output by the fifth flip-flop 32 is 0, it means that there is no data conforming to the rule of ABCDE in the input data. The above-mentioned clock signal can be provided by an external circuit or an internal circuit, which is well known to those skilled in the art, so no further description is given here.

Judging circuit 40, which receives the operation result and is used to judge the logic data to know whether part of the input data conforms to the scanning rule. For this embodiment, if the operation output by the fifth flip-flop 32 of the operation circuit 30 When the result is 1, it means that part of the input data conforms to the scanning rule. When the judging circuit 40 learns that the input data received by the physical layer device 10 includes conforming to the scanning rules, it will send a control signal to the processing circuit 50, and the processing circuit 50 will perform related actions after receiving the control signal, for example, when the judging circuit 40 When the packet data of the Internet is compared with the scanning rule, the processing unit 50 can prevent the opening of the web page or avoid the attack of the virus.

The present invention is based on the scanning rule, makes each data of the scanning rule correspond to the label data of the storage circuit 20, that is, the storage address, and stores part of the corresponding label data, and allows the storage circuit 20 to output the corresponding bit according to the input data. data, and then through the calculation circuit 30 to generate calculation results based on the data output by the storage circuit 20, and then through the judgment unit 40 to judge the calculation results, you can know whether the input data contains data that conforms to the scanning rules, and this way can save the circuit. Complexity, thereby saving costs, and can improve scanning efficiency. In addition, the judging circuit 40 can arbitrarily set which flip-flop 32 output is to be used as logic data for judging, so the present invention has great flexibility and is convenient to use.

In addition, the judging circuit 40 also includes a counting unit 60 for counting the clock signal CLK. When the judging circuit 40 learns that part of the input data conforms to the scanning rule, it can know that it complies with the scanning rule according to the counting result of the counting unit 60. The location of the data in the input data to facilitate subsequent processing. The counting unit 60 disposed in the judging circuit 40 is only an embodiment of the present invention, and it is not limited that the counting unit 60 must only be disposed in the judging circuit 40 .

Referring to Fig. 3 again, since all the flip-flops 32 of the arithmetic circuit 30 in this embodiment are connected in series, so the arithmetic circuit 30 must be separated when the logic operation is different in scanning rules, so as to avoid the influence of the result of the last scanning rule The result of the next scan rule. The present invention also includes multiple isolation units 36, and the isolation units 36 in this embodiment can be OR gates. The isolation unit 36 is located between the two flip-flops 32 and is coupled to the front-stage flip-flop 32 and the logic unit 34 between the two flip-flops 32, and is used to receive an isolation signal to isolate the next scan rule, wherein The partition signal can be sent by the judging unit 40 or by other external circuits. If the first scan rule contains five scan data, the fifth flip-flop 32 and the sixth flip-flop 32 must be isolated, and the judging circuit 40 then sends a partition signal to the fifth flip-flop 32 and the isolation unit 36 between the sixth flip-flop 32, the partition signal of this embodiment is 1, so regardless of the output 1 or 0 of the fifth flip-flop 32, the output of the isolation unit 36 is 1, the fifth The output of the logic unit 34 between the first flip-flop 32 and the sixth flip-flop 32 is determined according to the first batch of data of the next scanning rule, that is, the data received by the sixth flip-flop 32 is the data of the next scanning rule , so the fifth flip-flop 32 and the sixth flip-flop 32 can be isolated to effectively isolate the scanning rules.

Continuing from the above, the judging circuit 40 can freely set the isolation unit 36 according to the size of the scan rule, so that the length of the scan rule can be dynamically set to increase the flexibility of use. In this embodiment, cost saving can be considered. The computing circuit 30 can set the isolation units 36 at a fixed interval, such as setting the isolation units 36 in multiples of 4 or 6, so as to simplify the complexity of the circuit and save costs. Furthermore, if the multi-scanning data of the scanning rule is less than the number set at a fixed interval, the extra bits are ignored data, that is, they are set to 1, such as when the isolation unit 36 is set in a multiple of 6, if When the multi-scan data of the scan rule is less than 6 bits, the extra bits can be set to 1 (don't care).

Please also refer to FIG. 4 , which is a block diagram of another preferred embodiment of the present invention. As shown in the figure, the difference between this embodiment and the embodiment of FIG. 2 is that FIG. 2 only has a storage circuit 20, and this embodiment has a first storage circuit 22 and a second storage circuit 24, wherein the first storage circuit Both the storage capacity of the circuit 22 and the second storage circuit 24 are smaller than the storage capacity of the storage circuit 20 , through this configuration, the capacity of the storage circuit 20 can be reduced, thereby reducing the occupied area. The reason for this is that if one byte (8 bits) is divided into two 4 bits, the scanning data of one byte only needs 2^4×2=32 bits, that is to say, only two depth 16 bits are required. A storage circuit 22 and a second storage circuit 24 can replace the storage circuit 20 of the embodiment in FIG. The area occupied by the storage circuit.

Furthermore, the scanning circuit of this embodiment further includes a sequence unit 26 , the input terminals of the sequence unit 26 are respectively coupled to the first storage circuit 22 and the second storage circuit 24 . When the physical layer device 10 receives the input data, it separates the input data and transmits them to the corresponding first storage circuit 22 and the second storage circuit 24 respectively, so as to output the corresponding data respectively. Afterwards, the processing by the sequence unit 26 serializes the output data of the first storage circuit 22 and the second storage circuit 24, and then transmits them to the operation circuit 30 for subsequent processing similar to that of the embodiment in FIG. 2 .

To sum up, in the data scanning circuit and method of the present invention, the storage circuit stores a plurality of tag data, and each tag data corresponds to a sub-rule, and the storage circuit outputs each sub-rule according to the first data and the second data. A first part and a second part of a label data; an operation circuit logically operates the first part and the second part to generate an operation result; a judging circuit judges whether the input data conforms to the Scan rules. Therefore, the complexity of the circuit can be saved, thereby saving the cost, and the scanning efficiency and scanning flexibility can be improved.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, the protection scope of the present invention shall be determined by the scope of the appended claims.

Claims (13)

1. a data scanning circuit is used for scanning input data and whether meets a rule, and these input data comprise one first data and one second data, and this data scanning circuit comprises:

One memory circuit; In order to store many batches of label datas; And each batch label data corresponds to a sub-rule; Wherein, this memory circuit reads address corresponding label data as a first position to export in every batch of label data with this as reading the address with these first data, and reads address corresponding label data as a second portion position to export in every batch of label data with this as reading the address with these second data;

One computing circuit is coupled to this memory circuit, in order to logical operation is carried out in this first position and this second portion position, to produce an operation result; And

One decision circuitry is coupled to this computing circuit, in order to according to this operation result judging whether these input data meet this rule,

Wherein this computing circuit comprises:

A plurality of triggers; And

A plurality of logical blocks are respectively coupled between these a plurality of triggers;

Wherein, These a plurality of triggers are exported this first position to these a plurality of logical blocks according to clock signal displacement; These a plurality of logical blocks carried out logical operation to this first position of being exported by this a plurality of trigger with this this second portion position of being exported by this memory circuit; To produce this operation result

Wherein each in the every batch of label data is distributed in this different memory circuit addresses, and

Wherein every batch of label data is the N position; And the N-1 of every batch of label data position corresponds to same logical value, and wherein in the N bit address of every batch of label data of storage of memory circuit, the corresponding memory address of the ASCII(American Standard Code for information interchange) corresponding with sub-rule is set at 1; All the other N-1 positions are set at 0

Wherein first data and second data are 1 byte, and N is 256.

2. data scanning circuit as claimed in claim 1, wherein these first data and this second data input to the address port of this memory circuit.

3. data scanning circuit as claimed in claim 1, wherein every batch of label data is a programmable label data.

4. data scanning circuit as claimed in claim 1, wherein these a plurality of logical blocks are and door.

5. data scanning circuit as claimed in claim 1 also comprises:

One counting unit meets the position that these regular data are arranged in these input data in order to count this clock signal to learn.

6. data scanning circuit as claimed in claim 1, wherein this sub-rule is represented a character.

7. data scanning circuit as claimed in claim 1, wherein this memory circuit is a static RAM.

8. data scanning circuit as claimed in claim 1 is arranged in the medium access controller.

9. a data scanning method is used for scanning input data and whether meets a rule, and these input data comprise one first data and one second data, and this data scanning method comprises:

Store many batches of label datas in a memory circuit, each batch label data corresponds to a sub-rule;

Read address corresponding label data as a first position to export in every batch of label data with this as reading the address with these first data;

Read address corresponding label data as a second portion position to export in every batch of label data with this as reading the address with these second data;

Logical operation is carried out to produce an operation result in this first position and this second portion position; And

Whether meet this rule according to this operation result with these input data of judgement,

Wherein in the step of logical operation, also comprise:

According to this first position of clock signal displacement, and carry out logical operation with this second portion position, producing this operation result,

Wherein each in the every batch of label data is distributed in the different storage addresss, and

Wherein every batch of label data is the N position; And the N-1 of this first label data position corresponds to same logical value; Wherein in the N bit address of every batch of label data of storage of memory circuit; The corresponding memory address of the ASCII(American Standard Code for information interchange) corresponding with sub-rule is set at 1, and all the other N-1 positions are set at 0

Wherein first data and second data are 1 byte, and N is 256.

10. data scanning method as claimed in claim 9, wherein these first data and this second data input to the address port of this memory circuit.

11. data scanning method as claimed in claim 9, wherein every batch of label data is a programmable label data.

12. scan method as claimed in claim 9 also comprises:

Count this clock signal and meet the position that these regular data are arranged in these input data to learn.

13. scan method as claimed in claim 9 is applied to a network management interchanger or a load balancer.

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