CN101404639B - Method for preventing block synchronization error lock in single carrier frequency domain equalization system - Google Patents
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Abstract
The invention discloses a method for preventing block synchronous locking in a single carrier system with frequency domain equalization system, which comprises the following steps: after synchronization of a data block is completed, receive data corresponding to a unique word sequence used for channel estimate is acquired, wherein the length of the unique word sequence is the same as that of the data block transmitted by a transmitting end, and is an M code element; the receive data is subject to Fourier to calculate a result of channel estimate; the result of the channel estimate is subject to Fourier to receive h, and a searching range is intended to be last L code elements of h, wherein L is the length of the cyclic prefix of the data block transmitted by the transmitting end; a multipath component with first channel gain more than threshold of predetermined channel gain is searched in the searching range, so as to acquire the position Q of the multipath component in the searching range, and the synchronous position is deflected (M+1-Q) code elements towards the opposite direction of data transmission. The invention effectively solves the problem that when an achieved first path has deep attenuation during transmitting process, determined symbol initial position is deflected towards the direction of data transmission.
Description
Technical field
The present invention relates to SC-FDE (single carrier system with frequency domainequalization, single carrier frequency domain equalization) technology, relate in particular to the method that prevents block synchronization error lock in a kind of SC-FDE system.
Background technology
At present; Along with new communication service demand increases rapidly; Transmission rate to wireless communication system and WLAN is had higher requirement; And the raising of transmission rate has brought bigger carrier wave frequency deviation, more serious ISI problems such as (intersymbol-interference, intersymbol interference) for conventional single-carrier system.OFDM (Orthogonal Frequency Division Multiplexing; OFDM) technology can effectively overcome the intersymbol interference that the weak channel of frequency selectivity brings; Become the research focus of radio communication and moving communicating field gradually, in multiple standards, be called as support technology.But the OFDM technology is relatively more responsive to carrier synchronization, and PAPR (Peak-to-Average Power Ratio, peak-to-average power ratio) is bigger, so the SC-FDE technology is suggested.The SC-FDE technology is the method that a kind of up-and-coming anti-multipath disturbs in the broadband wireless transmission; The same piecemeal of taking with OFDM transmits; And adopt CP (Cyclic Prefix; Cyclic Prefix) mode so just can be converted into circular convolution to the linear convolution of signal and channel impulse response, and eliminated the interference of the data block that multipath causes.Adopt simple frequency-domain equalization technology just can eliminate intersymbol interference at receiving terminal.The SC-FDE system compares ofdm system and does not have the PAPR problem, thus need not use expensive linear power amplifier, simultaneously neither be responsive especially to carrier synchronization, so the SC-FDE technology receives increasing attention at present.
See also Fig. 1, this figure is the sketch map that data flow is transmitted by piecemeal in the existing SC-FDE system, by visible among the figure; In existing SC-FDE system, data flow is transmitted by piecemeal, the time domain data vector paragraph x that it is N that every blocks of data stream certain encoding process of process and constellation mapping form a length afterwards; Add that after data segment x length is the Cyclic Prefix of L---the UW sequence; Obtaining length is the vectorial s of M=L+N, is called data block, wherein s
j=s
J+N+L, j=N+1 ..., N+L.Data block obtains the signal flow r corresponding with it through after the Channel Transmission at receiving terminal.The function of UW sequence mainly contains two: the firstth, avoid the IBI (interblock-interference, inter-block-interference) between the valid data piece, and channel pulse here rings time T
hMust be less than the duration T of UW
GThe secondth, can guarantee the linear convolution of signal and channel impulse response is converted into circular convolution.
The time can cause many-sided influence to the SC-FDE system partially, specific as follows:
The first, make the planisphere of signal that rotation take place;
The second, brought inter symbol interference ISI;
The 3rd, inclined to one side correction can't be carried out accurate frequency offset estimating when not carrying out;
The 4th, the time inclined to one side existence cause obtaining the original position of Fourier transform window accurately, cause channel estimating, frequency domain equalization precise decreasing;
The 5th, big partially more when initial, the effect of channel tracking, timing tracking and carrier tracking is poor more.
The influence of above-mentioned these aspects all will cause the SC-FDE system normally to move, and the accuracy of therefore initial timing estimation will influence the performance of SC-FDE system to a great extent.In general SC-FDE system, be controlled in partially usually when initial in 5% the symbol time.In order to keep the superperformance of SC-FDE system, must accurately know the original position of data block based on the SC-FDE system of piece processing.
In that arrival detects through frame, carrier wave frequency deviation is caught, the symbol original position is estimated (piece is synchronous) afterwards, also just confirmed the original position of data block generally speaking.But because the existence of Doppler frequency deviation; Channel is changing; When article one footpath that arrives occurs dark when weak in the Channel Transmission process; The gain in the second that will occur arriving footpath or the 3rd footpath is maximum, and this moment, main footpath just was not article one footpath, because the piece synchronized algorithm is to rely on to receive to seek in the data and known lead data (preamble) point of the coupling original position of coming the specified data piece; Therefore the definite original position of piece synchronized algorithm will be to the direction skew of transfer of data, and this situation is called as the synchronous mistake lock phenomenon of piece.Under block data structure shown in Figure 1, wrong lock phenomenon not only can cause above-mentioned influence, also can weaken two functions of UW sequence, therefore must piece synchronously after judgement inclined to one side when whether existing, and then inclined to one side when correcting this.
Because in the real process, the dark weak probability of appearance is less, promptly main footpath is not that article one possibility directly that arrives is less; But in case this situation occurs; The block synchronization error lock phenomenon to occur, the operation of the various algorithms after this will have a strong impact on causes the data of this frame invalid at last.
Summary of the invention
The present invention provides the method that prevents block synchronization error lock in a kind of SC-FDE system; In order to solve in the prior art when article one footpath that arrives in the Channel Transmission process, occur dark when weak, the problem that the symbol original position of determining can squint to the direction of transfer of data.
Technical scheme according to the invention is specific as follows:
Prevent the method for block synchronization error lock in a kind of single-carrier frequency domain equalization system, comprise step:
A, single-carrier frequency domain equalization system accomplish data block synchronously after, obtain the corresponding reception data r of unique word sequence that is used for channel estimating, the length of this unique word sequence is identical with the length of the data block of transmitting terminal transmission, is the M code element;
B, said reception data r is carried out Fourier transform obtain R
Fft, calculating channel estimated result H=R
Fft/ U
Fft, U
FftBe the said Fourier transform value that is used for the unique word sequence of channel estimating;
C, said channel estimation results H is carried out inverse fourier transform obtain h, back L the code element of h confirmed as in the hunting zone, wherein L is the length of Cyclic Prefix in the transmitting terminal data block of sending;
D, in said hunting zone first channel gain of search greater than the multipath component of preset channel gain thresholding; If search; Then block synchronization error lock appears in expression, obtains the position Q of this multipath component in the hunting zone, with sync bit M+1-Q code element of opposite direction skew towards transfer of data.
Preferably, also comprise step before the said steps A:
The length of the data block that A1, the length that is used for the unique word sequence of channel estimating are set to send with transmitting terminal is identical, and its length is the M code element.
Preferably, if in said hunting zone, do not search the multipath component of channel gain greater than the preset channel gain threshold, then block synchronization error lock does not appear in expression.
Preferably, the said detailed process of obtaining the reception data r of the unique word sequence correspondence that is used for channel estimating is:
Obtain being used for the original position P of the UW sequence of channel estimating, obtain the corresponding reception data r of unique word sequence that is used for channel estimating at receiving terminal, r=[r (P) ..., r (M+P-1)].
Preferably, said preset channel gain thresholding is 0.1.
Beneficial effect of the present invention is following:
The present invention utilizes the characteristic of channel estimation results on time domain; Side-play amount when the different characteristic of channel estimation results on time domain in the time of channel estimation results when locking through mistake occurring and accurate synchronization determined whether to occur wrong lock and wrong lock occurred; Solved fast and effectively in the prior art and to have occurred in the Channel Transmission process dark when weak when article one footpath that arrives; The problem that the symbol original position of determining can squint to the direction of transfer of data, its implementation procedure is simple, convenient.
Description of drawings
Fig. 1 is for preventing the method for block synchronization error lock in the SC-FDE according to the invention system;
Fig. 2 A is the sketch map of channel estimation results when article one directly occurs block synchronization error lock not taking place under the dark weak article one situation directly that causes second gain directly to arrive greater than elder generation;
Fig. 2 B is the sketch map of channel estimation results when article one directly occurs under the dark weak article one situation directly that causes second gain directly to arrive greater than elder generation block synchronization error lock taking place.
Embodiment
Owing to after piece is synchronous, can determine the original position of Fourier transform window; Therefore can carry out channel estimating according to the lead data structure; And because the SC-FDE system is the piecemeal deal with data, the size of each data block is a M=N+L Baud Length simultaneously, and the UW sequence satisfies strong correlation and the flat characteristic on the frequency domain on the time domain; Be suitable for channel estimating; Therefore the lead data piece that is used for channel estimating among the present invention be set to the UW sequence U=of M Baud Length [u (1) ..., u (M)].Because when block synchronization error lock occurring, whole circulation skew can appear in the channel estimating that the result in time domain of channel estimating is compared under the accurate synchronization, the present invention utilizes this characteristic to correct the block synchronization error lock problem exactly.
See also Fig. 1, this figure is the method that prevents block synchronization error lock in the SC-FDE according to the invention system, and its main implementation procedure is following:
The length of the data block that step 10, the length that is used for the UW sequence of channel estimating are set to send with transmitting terminal is identical, and its length is the M code element, promptly U=[u (1) ..., u (M)].
Through an instantiation the present invention is given further detailed explanation below.
See also Fig. 2 A and Fig. 2 B; The sketch map of the sketch map of Fig. 2 A channel estimation results when directly occurring in article one block synchronization error lock not taking place under the dark weak situation of gain that causes the second footpath wherein, Fig. 2 B channel estimation results when directly occurring in article one under the dark weak situation of gain that causes the second footpath block synchronization error lock taking place greater than article one footpath that arrives earlier greater than article one footpath that arrives earlier.Visible by Fig. 2 A, when original position is correct, when promptly not having the mistake lock, channel estimation results on time domain, show as three footpaths all h (h=[and h (1) ..., h (M)]) initiating terminal.Because after the piece synchronized algorithm, can second directly be confirmed as main footpath; The synchronous estimated position of piece this moment is compared correct position and can be squinted towards data transfer direction; Side-play amount is the time-delay D between article one footpath and the main footpath, and shown in Fig. 2 B, the channel estimation results that obtain this moment shows as on time domain with the initial footpath that comprises arrival after it, main footpath all at the initiating terminal of h; And the cyclic shift of time D has directly taken place in the article one that arrives before the main footpath, appears at the end of h.Whether whether D is exactly the mistake lock side-play amount of required estimation, therefore can exist channel gain to judge to have occurred wrong lock phenomenon, general channel gain in less than 0.1, can think through search h tail position and not have multipath component.Therefore whether the tail end through search channel estimated value h occurs determining whether to occur wrong lock greater than the value of channel gain thresholding 0.1; Be the corresponding position Q in article one footpath when searching first position, with sync bit M+1-Q code element of opposite direction skew towards transfer of data greater than channel gain thresholding 0.1.Because Cyclic Prefix is taken as the L Baud Length, so the hunting zone is arranged in back L the code element of h afterbody and searches for, the hunting zone be [h (M-L+1) ..., h (M)].
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (4)
1. prevent the method for block synchronization error lock in the single-carrier frequency domain equalization system, it is characterized in that, comprise step:
A, single-carrier frequency domain equalization system accomplish data block synchronously after; Obtain being used for the original position P of the UW sequence of channel estimating at receiving terminal; Obtain the corresponding reception data r of UW sequence that is used for channel estimating, r=[r (P) ...; R (M-P-1)] length of length and the transmitting terminal of this UW sequence data block of sending is identical, is the M code element;
B, said reception data r is carried out Fourier transform obtain R
Fft, calculating channel estimated result H=R
Fft/ U
Fft, U
FftBe the said Fourier transform value that is used for the UW sequence of channel estimating;
C, said channel estimation results H is carried out inverse fourier transform obtain h, back L the code element of h confirmed as in the hunting zone, wherein L is the length of Cyclic Prefix in the transmitting terminal data block of sending;
D, in said hunting zone first channel gain of search greater than the multipath component of preset channel gain thresholding; If search; Then block synchronization error lock appears in expression, obtains the position Q of this multipath component in the hunting zone, with sync bit M+1-Q code element of opposite direction skew towards transfer of data.
2. the method for claim 1 is characterized in that, also comprises step before the said steps A:
The length of the data block that A1, the length that is used for the UW sequence of channel estimating are set to send with transmitting terminal is identical, and its length is the M code element.
3. the method for claim 1 is characterized in that, if in said hunting zone, do not search the multipath component of channel gain greater than the preset channel gain threshold, then block synchronization error lock does not appear in expression.
4. the method for claim 1 is characterized in that, said preset channel gain thresholding is 0.1.
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| CN1973505A (en) * | 2004-07-16 | 2007-05-30 | 富士通株式会社 | Frequency domain equalization method and device in single-carrier receiver |
| CN101258704A (en) * | 2005-12-20 | 2008-09-03 | 中兴通讯股份有限公司 | Transmitter, receiver and method thereof |
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| CN1973505A (en) * | 2004-07-16 | 2007-05-30 | 富士通株式会社 | Frequency domain equalization method and device in single-carrier receiver |
| CN101258704A (en) * | 2005-12-20 | 2008-09-03 | 中兴通讯股份有限公司 | Transmitter, receiver and method thereof |
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