CN101399273B - Image display system and manufacturing method thereof - Google Patents

Abstract

The invention discloses a method for manufacturing a low-temperature polycrystalline silicon driving circuit and a thin film transistor. The extension parts of the grid electrode and the dielectric layer can be formed at the same time and used as a mask, so that a lightly doped source/drain region and a source/drain region can be formed at the same time by one-time doping process, thereby reducing the number of process photomasks and further reducing the manufacturing cost.

Description

Image display system and manufacturing method thereof

technical field

The invention relates to a display device, in particular to a low-temperature polysilicon thin film transistor liquid crystal display device and a manufacturing method thereof.

Background technique

Generally speaking, thin film transistors (thin film transistors; TFTs) can be classified into amorphous silicon (amorphous) thin film transistors and polycrystalline silicon (polysilcion) thin film transistors. Polysilicon thin film transistors are manufactured using low-temperature polysilicon (LTPS) technology, and are quite different from amorphous silicon thin film transistors made by amorphous silicon (a-Si) technology. Low-temperature polysilicon (LTPS) transistors have relatively large electron mobility (>20cm ² /Vsec), therefore, LTPS transistors have relatively preferred size, large aperture ratio and low power Consumption (power rating). In addition, the low-temperature polysilicon process can manufacture the driving circuit and the thin film transistor on the same substrate at the same time, so that the reliability of the display panel can be increased and the manufacturing cost of the display panel can be reduced.

However, traditional fabrication of low temperature polysilicon driving circuits and thin film transistors requires 8 or 9 photomasks, resulting in higher fabrication costs. In addition, more photomasks also lead to longer production time and lower production yield.

Therefore, there is still a need for a low-temperature polysilicon process with fewer photomasks to reduce manufacturing costs.

Contents of the invention

In view of this, an embodiment of the present invention provides an image display system, including: a low-temperature polysilicon (LTPS) driving circuit and a thin film transistor (thin film transistor; TFT). The driving circuit and the thin film transistor include: a substrate; an active layer formed on the substrate; a gate insulating layer covering the first active layer; a dielectric layer located on the gate insulating layer, and the dielectric The layer has an extension; and a gate electrode is formed on the dielectric layer and exposes the extension; a storage capacitor including upper and lower electrodes is formed on the substrate; a contact hole is formed in the gate insulating layer, and The contact hole exposes the area where the lower electrode adjoins the active layer. The above image display system further includes a plurality of wires and pixel electrodes, wherein the wires are electrically connected to the driving circuit and the TFT, and the pixel electrodes are formed on the substrate to electrically connect the TFT. The extension of the dielectric layer can reduce the off current (Ioff) of the thin film transistor.

Another embodiment of the present invention provides a manufacturing method of an image display system, including providing a low temperature polysilicon driving circuit and a thin film transistor. The manufacturing method of the low-temperature polysilicon driving circuit and the thin film transistor includes: providing a substrate; forming a first active layer and a second active layer on the substrate; performing a P+ doping process to form a source/drain region on the first active layer Among the two active layers; forming a dielectric layer with an extension above the first active layer; forming a first gate electrode and a second gate electrode on the first active layer and the second active layer respectively layer; and performing N+ doping process to simultaneously form lightly doped source/drain regions and source/drain regions in the first active layer. The manufacturing method of the above-mentioned image display system further includes forming a plurality of wires on the substrate to electrically connect the driving circuit and the thin film transistor; and forming a pixel electrode on the substrate to electrically connect the thin film transistor. The method for forming the dielectric layer with the extension and the first and second gate electrodes includes depositing the dielectric layer and the metal layer, and then patterning the metal layer to simultaneously form the first and second gate electrodes and the first and second gate electrodes. The dielectric layer of the extension.

Since the extension part of the above-mentioned dielectric layer can be formed simultaneously with the gate electrode without using an additional photomask, the number of photomasks in the process can be reduced. Furthermore, the above-mentioned extension of the gate electrode and the dielectric layer can be used as a mask, so that the N+ doping process can be performed comprehensively without additional photomasks, and light doping can be formed simultaneously in one doping step. Impurity source/drain regions and source/drain regions. Accordingly, the manufacturing method of the image display system according to the embodiment of the present invention can reduce the number of photomasks, thereby reducing the manufacturing cost.

Yet another embodiment of the present invention provides a method for manufacturing an image display system, including providing a low-temperature polysilicon driving circuit and a thin film transistor. The manufacturing method of the low-temperature polysilicon driving circuit and the thin film transistor includes: providing a substrate; forming a first active layer and a second active layer on the substrate; forming a dielectric layer with an extension on the first active layer ; respectively forming a first gate electrode and a second gate electrode above the first active layer and the second active layer; and performing an N+ doping process to simultaneously form a lightly doped source/drain region and a source The /drain region is in the first active layer; the P+ doping process is performed to form the source/drain region in the second active layer. In addition, the method of forming the dielectric layer with the extension and the first and second gate electrodes includes depositing the dielectric layer and the metal layer, and then patterning the metal layer to simultaneously form the first and second gate electrodes and a dielectric layer having an extension. The manufacturing method of the above-mentioned image display system further includes forming a plurality of wires on the substrate to electrically connect the driving circuit and the thin film transistor; and forming a pixel electrode on the substrate to electrically connect the thin film transistor.

Description of drawings

1A-1H show the cross-sectional views of the low-temperature polysilicon drive circuit and the thin film transistor of the first embodiment of the present invention;

2A-2G show cross-sectional views of manufacturing a low-temperature polysilicon drive circuit and a thin film transistor according to a second embodiment of the present invention;

Fig. 3 shows the flow chart of making low-temperature polysilicon drive circuit and thin film transistor according to the embodiment of the present invention; And

FIG. 4 shows a schematic diagram of an image display system, wherein the image display system uses a display panel including a low temperature polysilicon driving circuit and a thin film transistor according to an embodiment of the present invention.

Description of main component symbols

100～substrate; 102～buffer layer; 104～drive region; 106～pixel region; 108～semiconductor layer; 110～doping process; 112～active layer; 112a～channel region; 114～active layer; 114a～ Channel region; 114b～source/drain region; 115～doped semiconductor layer; 115a～channel region; 116～bottom electrode; 118～patterned photoresist layer; 120～patterned photoresist 122～doping process; 124～gate insulating layer; 125～dielectric material layer; 126～dielectric layer; 126a～extended part; 127～dielectric layer; 127a～extended part; 128～dielectric layer ; 128a～extension part; 129～dielectric layer; 130～gate electrode; 132～gate electrode; 134～gate electrode; 136～upper electrode; 138～doping process; 140～lightly doped source/drain 142～source/drain region; 144～lightly doped source/drain region; 146～source/drain region; 148～interlayer dielectric layer; 150～protective layer; 152a～contact hole; 152b～contact Hole; 152c～contact hole; 154a～conducting wire; 154b～conducting wire; 154c～conducting wire; 156～planar layer; 158～opening; 160～pixel electrode; 162～N-type metal oxide semiconductor element; 164～P-type metal oxide Semiconductor element; 166～thin film transistor; 168～storage capacitor;

200～substrate; 202～buffer layer; 204～drive region; 206～pixel region; 208～active layer; 208a～channel region; 210～active layer; 210a～channel region; 210b～doped region; 212 ～doped semiconductor layer; 212a～channel region; 212b～bottom electrode; 214～gate insulating layer; 216～dielectric material; 218～gate electrode; 220～gate electrode; 222～gate electrode; 224 ～upper electrode; 226～dielectric layer; 226a～extended part; 228～dielectric layer; 228a～extended part; 230～dielectric layer; 230a～extended part; 232～doping process; 234～light doping source/ Drain region; 236～source/drain region; 238～lightly doped source/drain region; 240～source/drain region; 242～photoresist material; 243～photoresist material; 244 ~doping process; 246~source/drain region; 248~interlayer dielectric layer; 250~protective layer; 252a~contact hole; 252b~contact hole; 252c~contact hole; 254a~wire; 254b~wire; 254c ～wire; 256～flat layer; 258～opening; 260～pixel electrode; 262～N-type metal oxide semiconductor element; 264～P-type metal oxide semiconductor element; 266～thin film transistor; 268～storage capacitor; 300～image Display system; 310～display panel; 320～control unit.

Detailed ways

Next, specific embodiments of the present invention and methods for making them will be described in detail. It can be appreciated, however, that the present invention provides many inventive concepts that can be implemented in a wide variety of fields of application. The examples used for illustration are merely illustrations of specific implementations utilizing the concepts of the present invention, and do not limit the scope of the present invention.

The present invention is illustrated by an embodiment of a low temperature polysilicon (LTPS) driving circuit and a thin film transistor (TFT). However, the concept of the invention can of course also be used to fabricate other integrated circuits. 1A-1H are cross-sectional views showing fabrication of a low-temperature polysilicon driving circuit and a thin film transistor according to a first embodiment of the present invention. 2A-2G are cross-sectional views showing fabrication of a low temperature polysilicon driving circuit according to a second embodiment of the present invention.

As shown in FIG. 1A , a substrate 100 with a buffer layer 102 formed thereon is provided, and the substrate 100 can be divided into a driving area 104 and a pixel area 106 . In an embodiment, the above-mentioned substrate 100 may be glass, plastic or other suitable transparent substrates.

Next, a semiconductor layer 108 is formed on the substrate 100 . In one embodiment, the method of forming the semiconductor layer 108 may be, for example, depositing an amorphous silicon layer (amorphous silicon layer) on the above-mentioned substrate 100 by a chemical vapor deposition (chemical vapor deposition; CVD) method, and then performing an excimer laser Annealing (excimer laser annealing; ELA) treatment enables the amorphous silicon layer to be crystallized into a polysilicon layer (polysilicon layer).

As shown in FIG. 1B , the semiconductor layer 108 is patterned, and then a doping process is performed to form an active layer 112 , an active layer 114 and a doped semiconductor layer 115 (doped semiconductor layer). In addition, a portion of the doped semiconductor layer 115 located in the pixel region 106 can also be used as an active layer of a subsequent thin film transistor (TFT). In an embodiment, the above-mentioned doping process may also be performed before the step of patterning the semiconductor layer.

In addition, in one embodiment, the doping process can also be performed while depositing the amorphous silicon layer, and then laser annealing is performed on the amorphous silicon layer to convert it into polysilicon, and then the polysilicon layer is patterned. The above-mentioned doping process may also be referred to as a channel doping process (channel doping).

As shown in FIG. 1C , a P+ doping process 122 such as boron ions is performed to form source/drain regions 114 b in the active layer 114 . In one embodiment, a photoresist material is coated on the substrate 100 , and then the photoresist material is patterned to form patterned photoresist layers 118 and 120 . In the driving region 104 , the patterned photoresist layer 118 shields the active layer 112 , and the patterned photoresist layer 120 shields a portion of the active layer 114 to expose the portion to be doped. In the pixel region 106 , the patterned photoresist layer 118 shields part of the doped semiconductor layer 115 to expose the part to be doped. Next, a doping process 122 is performed to form a source/drain region 114b and a channel region 114a, and in the pixel region 106, a lower electrode 116 of a storage capacitance is formed. After the doping process 112 is completed, the patterned photoresist layers 118 and 120 are removed.

但并不以此为限。As shown in FIG. 1D , a gate insulation layer 124 and a dielectric material layer 125 are sequentially formed on the substrate 100 to cover the components fabricated on the substrate 100 . In an embodiment, the material of the dielectric material layer 125 may be silicon nitride, silicon oxynitride or other suitable nitride materials. The material of the gate insulating layer 124 may be silicon oxide. In addition, the thickness of the dielectric material layer 125 is related to the implantation energy of the subsequent N+ doping process, and the preferred thickness may be about 400 Angstroms

But not limited to this.

In another embodiment, the gate insulating layer 124 and the dielectric material layer 125 may also be formed first, and then a P+ doping process is performed to form the source/drain region 114 b in the active layer 114 .

As shown in FIG. 1E , then, gate electrodes 130 , 132 and 134 and an upper electrode 136 are formed on the dielectric layers 126 , 127 , 128 and 129 respectively. In one embodiment, a metal layer such as aluminum/molybdenum alloy is formed on the substrate 100, and then, a patterned photoresist layer (not shown) is formed on the metal layer, and The overetching process removes part of the metal layer and part of the dielectric material layer at the same time. After that, the patterned photoresist layer is removed to form the gate electrodes 130 , 132 , 234 and the upper electrode 136 , and the dielectric layers 126 , 127 , 128 and 129 .

之间。In addition, the dielectric layers 126 , 127 and 128 respectively having extending portions 126 a , 127 a and 128 a can also be formed simultaneously through the above-mentioned over-etching process on the metal layer without additional steps of forming a mask. Accordingly, process steps can also be reduced. In one embodiment, the length d of the extensions 126a, 127a and 128a of the dielectric layers 126, 127 and 128 is preferably between 3000 angstroms. ~5000 Angstroms

between.

As shown in FIG. 1F , a phosphorous ion N+ doping process 138 is performed to simultaneously form lightly doped drain/source (LDD) regions 140 , 144 and source/drain regions 142 , 146 . It should be noted that since the N+ doping process is performed after forming the gate electrodes, the gate electrodes 130 , 132 and 134 can be used as masks for the channel regions 112 a , 114 a and 115 a.

In addition, the extensions 126a and 128a of the above-mentioned dielectric layers 126 and 128 can also be used as a mask to reduce phosphorus ions passing through the extensions 126a and 128a during the N+ doping process. Therefore, the concentration of phosphorus ions in the active layers 112 and 115 covered with the extensions 126a and 128a is lower than the concentration of phosphorus ions in the active layers 112 and 115 not covered with the extensions 126a and 128a. Accordingly, according to the method of the first embodiment of the present invention, the N+ doping process can be performed comprehensively by using the extension of the gate electrode and the dielectric layer as a mask, without additional steps of forming a mask, so as to simultaneously The fabrication of lightly doped source/drain regions and source/drain regions is completed.

Since the extensions 126a and 128a can be used as masks, the sides of the lightly doped source/drain regions 140 and 144 are substantially aligned with the sides of the extensions 126a and 128a respectively. Furthermore, since the extension of the dielectric layer can be formed simultaneously with the gate electrode, no additional photomask is required, and the formed extension and the gate electrode can be used as a mask to simultaneously form the lightly doped The impurity source/drain region and the source/drain region also do not need a photomask. Therefore, according to the method described in the first embodiment of the present invention, the number of photomasks can be reduced by at least two. Therefore, the production process can be shortened and the cost can be saved.

After the above steps are completed, an N-type metal-oxide semiconductor (MOS) element 162 will be formed in the drive region 104, which consists of a channel region 112a, a lightly doped source/drain region 140, a source/drain region 142, a gate insulating layer 124, a dielectric layer 126 and a gate electrode 130, and a P-type metal oxide semiconductor element 164, which is composed of a channel region 114a, a source/drain region 114b, a gate insulating layer 124, The dielectric layer 127 and the gate electrode 132 are formed. At the same time, a thin film transistor 166 will also be formed in the pixel region 106, which consists of a channel region 115a, a lightly doped source/drain region 144, a source/drain region 146, a gate insulating layer 124, a dielectric layer 128 and a gate electrode. electrode 134 and storage capacitor 168 .

It is worth mentioning that, in the above-mentioned N+ doping process, in order to completely shield the channel region 114a, the bottom width L2 of the gate electrode 132 of the P-type metal oxide semiconductor element 164 is preferably larger than that of the channel region 114a. The length L1 is such that the gate electrode 132 can completely cover the channel region 114 a during the N+ doping process. For the above purpose, in an embodiment where the length L1' of the channel region 114a is similar to the length L1 of the channel region 112a, the bottom width L2 of the gate electrode 132 of the P-type metal oxide semiconductor element 164 can be designed to be greater than N The bottom width L2 ′ of the gate electrode 130 of the type MOS device 162 . Alternatively, in an embodiment where the bottom width L2 of the gate electrode 132 is similar to the bottom width L2' of the gate electrode 130, the length L1 of the channel region 114a of the P-type metal oxide semiconductor element 164 can also be designed to be smaller than N The length L1 ′ of the channel region 112 a of the type MOS device 162 .

As shown in FIG. 1G, an interlayer dielectric layer (interlayer dielectric) 148 and a passivation layer (passivation layer) 150 are sequentially deposited on the above-mentioned substrate 100, and then, the interlayer dielectric layer 148 and the passivation layer 150 are patterned to form The contact holes 152 a , 152 b and 152 c are in the interlayer dielectric layer 148 and the passivation layer 150 and expose the source/drain regions 142 , 114 b and 146 .

In FIG. 1G, after patterning the interlayer dielectric layer 148 and the passivation layer 150, wires 154a, 154b, and 154c are formed in the respective contact holes 152a, 152b, and 152c to electrically connect the source/drain regions 142, 114b and 146. In one embodiment, a metal stack layer such as molybdenum/aluminum/molybdenum is covered on the substrate 100, and then the metal stack layer is patterned to form wires 154a, 154b, and 154c, which are electrically connected to the thin film transistors in the pixel region 106. 166 and the driver circuit of the driver region 104 .

It is worth mentioning that in the pixel region 106, the lower electrode 116 of the storage capacitor 168 is doped with a P-type dopant, and the source/drain region 146 of the thin film transistor 166 is doped with an N-type dopant. Therefore, The phenomenon of PN junction (PN junction) will be derived. In a preferred embodiment, the contact hole 152c can be disposed adjacent to or adjacent to the lower electrode 116 and the source/drain region 146, and the wire 154c is filled in the contact hole 152c, so as to derive the emitted electrons and holes. Thus, the occurrence of PN junction phenomenon can be avoided.

As shown in FIG. 1H , a flat layer 156 is formed on the substrate 100 , and then, the flat layer 156 is patterned to form an opening 158 . Afterwards, a pixel electrode 160 is formed on the planar layer, and is electrically connected to the thin film transistor 166 through the opening 158 . In one embodiment, a transparent conductive layer such as indium tin oxide (ITO) is formed on the substrate 100 , and then the transparent conductive layer is patterned to form the pixel electrode 160 .

FIG. 1H shows a cross-sectional view of a low temperature polysilicon driving circuit and a thin film transistor according to a first embodiment of the present invention. Please refer to FIG. 1H , in the driving region 104 , a complementary metal-oxide semiconductor (CMOS) device driving circuit having N-type and P-type metal-oxide semiconductor devices 162 and 164 is shown. The above-mentioned N-type metal oxide semiconductor device 162 includes an active layer 112, a gate insulating layer 124, a dielectric layer 126 having an extension 126a, and a gate electrode 130, wherein the gate electrode 130 is located on the dielectric layer 126 and exposed extension 126a. The P-type metal oxide semiconductor element 164 includes an active layer 114 having a channel region 114, a source/drain region 114a, a gate insulating layer 124, and a gate electrode 132, wherein the width of the bottom of the gate electrode 132 is larger than that of the trench. The length of the track area 114.

Please refer to FIG. 1H again, in the pixel area 106, a thin film transistor 166 and a storage capacitor 168 are displayed. The thin film transistor 166 includes an active layer, a gate insulating layer 124 , a dielectric layer 128 having an extension 128 a , and a gate electrode 134 , wherein the gate electrode 134 is located on the dielectric layer 126 and exposes the extension 128 a. The active layer includes a channel region 115a, a lightly doped source/drain region 144 and a source/drain region 146, wherein the sides of the lightly doped source/drain region 114 are substantially aligned with the sides of the extension portion 128a respectively. side. In FIG. 1H , wires 154 a , 154 b and 154 c are formed on the substrate 100 and are electrically connected to the thin film transistor 166 and the driving circuit. The wire 154c is in contact with the lower electrode 116 and the source/drain region of the storage capacitor 168 through the contact hole. Furthermore, the pixel electrode 160 is electrically connected to the thin film transistor 166 and corresponds to the storage capacitor 168 .

It should be noted that since the extension of the dielectric layer can be used as a mask during the doping process, the extension of the dielectric layer can be formed simultaneously with the gate electrode. Therefore, according to the method of the first embodiment of the present invention, the number of photomasks in the process can be reduced, thereby reducing the manufacturing cost. In addition, the extension of the above-mentioned dielectric layer can also reduce the off current (Ioff) of the thin film transistor.

2A-2G show cross-sectional views of manufacturing a low-temperature polysilicon driving circuit and a thin film transistor according to a second embodiment of the present invention. Compared with the first embodiment, in the second embodiment, the P+ doping process is performed after forming the gate electrode and the N+ doping process. Therefore, the materials and formation methods of similar components can refer to the description of the above-mentioned first embodiment, and will not be repeated here.

As shown in FIG. 2A , a substrate 200 on which a buffer layer 202 is formed is provided, and the substrate 200 is divided into a driving region 204 and a pixel region 206 . Next, the active layers 208 and 210 and the doped semiconductor layer 212 are formed on the substrate 200 .

As shown in FIG. 2B , a gate insulating layer 214 and a dielectric material layer 216 are sequentially formed on the substrate 200 to cover the components fabricated on the substrate 200 . Next, as shown in FIG. 2C , gate electrodes 218 , 220 and 222 , and dielectric layers 226 , 228 and 230 respectively having extensions 226 a , 228 a and 230 a are formed on the substrate 200 . Similar to the first embodiment, first, a metal layer is deposited on the dielectric material layer 215, then, a patterned photoresist material (not shown) is formed, and an overetching process is performed to simultaneously form the gate electrode 218, 220 and 222, and dielectric layers 226, 228, and 230 with extensions 226a, 228a, and 230a, respectively, without additional masking steps. In one embodiment, the length d of the extension portions 226 a , 228 a and 230 a is preferably between 3000 angstroms and 5000 angstroms. In addition, through the above steps, a storage capacitor is also formed on the substrate 200, and the storage capacitor includes an upper electrode 224 and a lower electrode 212b (as shown in FIG. 2D ). Since the extension part of the dielectric layer can be formed simultaneously with the gate electrode without an additional photomask, the number of photomasks in the process can also be reduced, thereby saving manufacturing cost.

In FIG. 2D , then, through the mask formed by the above-mentioned gate electrodes 218, 222 and extensions 226a, 230a, an N+ doping process 232 is performed to simultaneously form lightly doped source/drain regions 234 and source/drain regions. electrode region 236, and lightly doped source/drain region 238 and source/drain region 240 without additional masking steps. It should be noted that, since the extensions 226a and 230a can be used as masks, the sides of the lightly doped source/drain regions 234 and 238 are substantially aligned with the sides of the extensions 226a and 230a.

As shown in FIG. 2E , a P+ doping process 244 is performed to form source/drain regions 246 . In one embodiment, a photoresist material is covered and patterned to form patterned photoresist layers 242 and 243 to expose the portion to be doped. Next, a P+ doping process 244 is performed to form source/drain regions 246 . It is worth noting that since the above-mentioned N+ doping process is comprehensive doping, therefore, in the P+ doping process, its doping concentration is preferably greater than that of the above-mentioned N+ doping process, so as to convert the original The N+ doped region 210b is transformed into a P+ source/drain region 246 .

As shown in FIG. 2F, then, an interlayer dielectric layer 248 and a protective layer 250 are sequentially formed on the substrate 200, and then, the interlayer dielectric layer 248 and the protective layer 250 are patterned to form contact holes 252a, 252b and 252c is in the interlayer dielectric layer 248 and the passivation layer 250 . Lead wires 254a, 254b, and 254c are formed on the substrate 200, and respectively extend in the above-mentioned contact holes 252a, 252b, and 252c, so as to electrically connect the thin film transistor 266 with the N-type metal oxide semiconductor element 262 and the P-type metal oxide semiconductor device. A CMOS device driving circuit for the physical semiconductor device 264 . It is worth mentioning that the above-mentioned contact hole 252c will expose the area adjacent to the source/drain region 240 and the bottom electrode 212b, so that the subsequently formed wire 254c will contact the source/drain region 240 and the bottom electrode 212b at the same time.

As shown in FIG. 2G , an overcoating layer 256 is formed on the substrate 200 , and then, the overcoating layer 256 is patterned to form an opening 258 . Afterwards, the pixel electrode 260 is formed corresponding to the storage capacitor 268 and electrically connected to the thin film transistor 266 .

FIG. 2G shows a cross-sectional view of a low temperature polysilicon driving circuit and a thin film transistor according to a second embodiment of the present invention. Please refer to FIG. 2G , in the driving area 204 , a CMOS device driving circuit having an N-type MOS device 262 and a P-type MOS device 264 is shown. The N-type metal oxide semiconductor device 262 includes an active layer 208, a gate insulating layer 214, a dielectric layer 226 with an extension 226a, and a gate electrode 218, wherein the gate electrode 218 is located on the dielectric layer 226 and exposed extension 226a. The PMOS device 264 includes an active layer 210 , a gate insulating layer 214 and a gate electrode 220 .

Please refer to FIG. 2G again, in the pixel area 206, a thin film transistor 266 and a storage capacitor 268 are displayed. The thin film transistor 266 includes an active layer with a channel region 212a, a lightly doped source/drain region 238 and a source/drain region 240, a gate insulating layer 214, a dielectric layer 230 with an extension 230a, and a gate electrode. The electrode 222, wherein the gate electrode 222 is disposed on the dielectric layer 230, exposes the extension 230a, and the side of the lightly doped source/drain region 238 is substantially aligned with the side of the extension 230a. The storage capacitor 268 is located on the substrate 200 and includes an upper electrode 224 and a lower electrode 212b. Also as shown in FIG. 2G , wires 254 a , 254 b and 254 c are formed above the substrate 100 and are electrically connected to the thin film transistor 266 and the driving circuit. The pixel electrode 260 corresponds to the storage capacitor 268 and is electrically connected to the thin film transistor 266 . It is worth mentioning that, in the pixel region 206 , the wire 254 c simultaneously contacts the lower electrode 212 b of the storage capacitor 268 and the source/drain region 240 of the thin film transistor 266 through the contact hole.

FIG. 3 shows a flow chart of fabricating a low temperature polysilicon driving circuit and a thin film transistor according to an embodiment of the present invention. In FIG. 3 , a substrate is provided, and an active layer (photomask 1 ) is formed on the substrate, as shown in steps S5 and S10 . Next, a local P+ doping process (photomask 2) is performed to form source/drain regions of the P-type metal oxide semiconductor device, as shown in step S15. A gate electrode is formed on the substrate (photomask 3), as shown in step S20. Carry out the N+ doping process comprehensively (without photomask), so as to form lightly doped source/drain regions and source/drain regions of N-type metal oxide semiconductor elements and thin film transistors at the same time, as shown in step S25 . A protection layer is deposited on the substrate, and the protection layer is patterned to form a plurality of contact holes (photomask 4), as shown in step S30. A plurality of wires are formed on the substrate (photomask 5 ) to electrically connect the driving circuit and the TFT, as shown in step S35 . A flat layer is covered on the substrate, and the flat layer (photomask 6 ) is patterned to form openings, as shown in step S40. Afterwards, a pixel electrode (photomask 7 ) is formed and electrically connected to the thin film transistor, as shown in step S45 .

Because, during the N+ doping process, the lightly doped source/drain region and the source/drain region can be fabricated at the same time, without additionally forming a mask. Therefore, the number of photomasks required for the process can be reduced, thereby reducing the cost of the process. In addition, in FIG. 3, step S15 can also be performed after steps S20 and S25, as disclosed in the second embodiment. It can be seen that, according to the methods disclosed in the embodiments of the present invention, only seven photomasks are needed to fabricate low temperature polysilicon driving circuits and thin film transistors.

4 shows a schematic diagram of an image display system 300, wherein the image display system 300 uses a display panel 310 including the low-temperature polysilicon driving circuit and thin film transistors of the present invention, and the display panel 310 may be a part of an electronic device. As shown in FIG. 4 , the image display system 300 includes a display panel 310 and a control unit 320 coupled thereto for transmitting signals to the display panel 310 to control the display panel to display images. The above-mentioned image display system 300 can be a mobile phone (mobile phone), a digital camera (digital camera), a personal digital assistant (personal digital assistant; PDA), a notebook computer (notebook computer), a desktop computer (desktopcomputer), a television, a vehicle Electronic devices such as monitors, global positioning systems (GPS), aviation monitors or portable digital versatile disc players.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any skilled person in the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as defined in the claims.

Claims (11)

1. image display system comprises:

Low temperature spathic silicon driving circuit and thin-film transistor comprise:

Substrate;

First active layer is formed on this substrate;

Gate insulator covers this first active layer;

First dielectric layer is positioned on this gate insulator, and this dielectric layer has extension; And

The first grid electrode is formed on this dielectric layer, and exposes this extension;

Storage capacitors is formed on this substrate, and this storage capacitors comprises top electrode and bottom electrode;

Contact hole is formed among this gate insulator, and this bottom electrode of this contact holes exposing is in abutting connection with the zone of this first active layer;

A plurality of leads are formed at this substrate top, and electrically connect drive circuit and this thin-film transistor; And

Pixel electrode electrically connects this thin-film transistor,

Wherein, this first active layer comprises: first channel region, corresponding to the first grid electrode; First lightly-doped source/drain region is in abutting connection with this first channel region; And first source/drain region, in abutting connection with this first lightly-doped source/drain region.

2. image display system as claimed in claim 1, this drive circuit wherein also comprises:

Second active layer is formed on this substrate, and this second active layer has second channel region and in abutting connection with the source/drain region of this second channel region;

Second dielectric layer is formed on this gate insulator; And

The second grid electrode is formed on this second dielectric layer, and to should second channel region.

3. image display system as claimed in claim 2, wherein the bottom width of this second grid electrode is greater than the length of this second channel region, and the length of this second channel region is less than the length of this first channel region.

4. image display system as claimed in claim 2, wherein the bottom width of this second grid electrode is greater than the length of this second channel region, and the bottom width of this second grid electrode is greater than the bottom width of this first grid electrode.

5. image display system as claimed in claim 1 also comprises:

Display floater comprises this low temperature spathic silicon driving circuit and thin-film transistor; And

Control unit couples this display floater, to control this display floater.

6. image display system as claimed in claim 5; Wherein this image display system comprises the electronic installation that uses this display floater, and this electronic installation comprises that mobile phone, digital camera, personal digital assistant, notebook computer, desktop computer, TV, automobile-used display, global positioning system, aviation are with display or the multi-functional laser disc player of portable digital.

7. the manufacture method of an image display system comprises:

Make the drive circuit and the thin-film transistor of low temperature polycrystalline silicon, comprising:

Substrate is provided;

Form first active layer and second active layer on this substrate;

The deposition of dielectric materials layer is in this substrate top;

Depositing metal layers is on this dielectric materials layer;

This metal level of patterning, forming first grid electrode and second grid electrode respectively in this first active layer and this second active layer top, and form simultaneously have extension dielectric layer between this first grid and this first active layer; And

Carry out first doping process, to form the lightly-doped source/drain region and first source/drain region simultaneously among this first active layer;

Form a plurality of leads on this substrate, to electrically connect this drive circuit and this thin-film transistor; And

Form pixel electrode on this substrate, and electrically connect this thin-film transistor.

8. the manufacture method of image display system as claimed in claim 7, this metal level of patterning wherein comprises:

Form patterning photoresist layer on this metal level of part; And

Carry out the over etching step, remove this metal level of part and this dielectric materials layer of part, to form this first, second gate electrode and to have this dielectric layer of this extension; And

Remove this patterning photoresist layer.

9. the manufacture method of image display system as claimed in claim 7 before forming this metal level, also comprises:

Form photo anti-corrosion agent material on this substrate;

This photo anti-corrosion agent material of patterning is with this second active layer of expose portion;

Carry out second doping process, to form channel region and second source/drain region, wherein the length of this channel region is less than the bottom width of this second grid electrode; And

Remove this photo anti-corrosion agent material.

10. the manufacture method of image display system as claimed in claim 7 also comprises forming storage capacitors on this substrate, and wherein this storage capacitors comprises top electrode and bottom electrode.

11. the manufacture method of image display system as claimed in claim 10 before forming these a plurality of leads, also comprises:

Form protective layer on this substrate, and cover this drive circuit, this thin-film transistor and this storage appearance electric capacity; And

This protective layer of patterning, forming contact hole among this protective layer, and the zone of this bottom electrode of this contact holes exposing and this first source/drain electrode adjacency.

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