CN101399019B - Source Driver and Its Noise Suppression Method - Google Patents

Abstract

The invention discloses a source driver and a noise suppression method thereof, which can suppress noise output by the source driver when a power supply is switched on/off. The source driver is powered by a first supply voltage output by a power supply and at least comprises a data bus, a plurality of channels, a multiplexer and a plurality of output ports. Each channel has a latch unit that can store data. The method at least comprises the following steps. First, it is determined whether the first supply voltage is insufficient, and if not, the following steps are performed. The data transmitted on the data bus is set as a default value, and then the latch unit is kept open, so that the data is output from the latch unit. Then, the multiplexer is kept open, so as to output a driving voltage through the output port according to the data.

Description

Source Driver and Its Noise Suppression Method

technical field

The present invention relates to a display, and in particular to a source driver of a display and a method thereof.

Background technique

In recent years, with the progress of optical technology and semiconductor technology, liquid crystal display (Liquid Crystal Display; LCD) has been widely used in electronic products. Liquid crystal displays have the advantages of high image quality, small size, light weight, low voltage drive, and low power consumption. Therefore, they have been widely used in portable computers, personal digital assistants, and color TVs, and have become the mainstream of displays.

FIG. 1 shows a schematic diagram of a conventional source driver 100 used in a liquid crystal display. The source driver 100 at least includes channels ( 108 , 110 ), a multiplexer (MUX) 112 , output ports ( 114 , 116 ), a data bus 118 and a charge sharing switch 120 . Channels 108 and 110 are respectively connected to output ports 114 and 116 via multiplexer 112 . The voltage equalizing switch 120 is electrically connected between the output terminals 114 and 116 for equalizing the voltage of the output terminals when needed. Each channel has a shift register (122 or 132), a latch unit (Latch Unit) (123 or 133), a level shifter (128 or 138), and a digital/analog converter (DAC) (130 or 140). Each latch unit at least includes a first latch (124 or 134) connected in series with a second latch (126 or 136). The data is transmitted on the data bus 118 and stored in the latch unit. What's more, the data is first stored in the first latch and then stored in the second latch. The data is then sent to a display (not shown) via the output ports 114 and 116 to display corresponding images on the display.

However, when the power supply supplied to the source driver is about to be cut off, the voltage supplied to the source driver will drop. Because the voltage is not enough, the channel may malfunction, which will cause abnormal images on the display, such as lines Defects (Line Defects) or stripes (Band Mura).

Contents of the invention

Therefore, the object of the present invention is to provide a source driver and its noise suppression method, which can reduce abnormal images displayed on the display when the power supply is turned on/off.

Another object of the present invention is to provide a source driver with a voltage drop detector for detecting whether the power supply is on/off, and if so, generating a reset signal (ResetSignal).

According to the above object of the present invention, a method for suppressing output noise of a source driver when a power supply is turned on/off is proposed. The source driver at least includes a data bus, multiple channels, a multiplexer and multiple output ports. The channels are coupled to the output port via a multiplexer, each channel has a latch unit, and data is transmitted on the data bus and stored in the latch unit. The source driver can be powered by a first supply voltage output by the power supply. The above method includes at least the following steps. Firstly, it is judged whether the first supply voltage is insufficient, and if not, the following steps are performed. First, the data transmitted on the data bus is set to a default value, and then the latch unit is kept open, so that the data is output from the latch unit. Then, keep the multiplexer turned on, so as to output a driving voltage through the output port according to the above data.

According to another object of the present invention, a source driver is provided, which can be powered by a power supply. The source driver at least includes a data bus, at least two channels, a multiplexer, at least two output ports, and a voltage drop detector. Each channel has a latch unit, and data is transmitted on the data bus and stored in the latch unit. The output port is coupled to the channels via a multiplexer. The voltage drop detector is used for detecting whether a first supply voltage output by the power supply is insufficient, and if insufficient, generates a reset signal. If this reset signal is generated, the data transmitted on the data bus is set to a default value, the latch unit is turned on, so that the data is output from the latch unit, and the multiplexer is turned on, so that according to the data, through the output The port outputs a driving voltage.

Description of drawings

In order to make the above-mentioned and other objects, features, advantages and embodiments of the present invention more comprehensible, the detailed description of the accompanying drawings is as follows:

FIG. 1 shows a schematic diagram of an existing source driver used in a liquid crystal display;

FIG. 2 shows a schematic diagram of a source driver according to a preferred embodiment of the present invention;

Fig. 3 shows a schematic diagram of another source driver according to a preferred embodiment of the present invention; and

Fig. 4 shows a schematic diagram of a pressure drop detector according to a preferred embodiment of the present invention.

Description of reference symbols

100: source driver 306: controller

108: Channel 308: Channel

110: Channel 310: Channel

112: Multiplexer 312: Multiplexer

114: output port 314: output port

116: output port 316: output port

118: Data bus 318: Data bus

120: Voltage sharing switch 320: Voltage sharing switch

122: Shift register 322: Shift register

123: Latch unit 323: Latch unit

124: The first latch 324: The first latch

126: Second latch 326: Second latch

128: Level shifter 328: Level shifter

130: Digital/Analog Converter 330: Digital/Analog Converter

132: Shift register 332: Shift register

133: Latch unit 333: Latch unit

134: The first latch 334: The first latch

136: Second latch 336: Second latch

138: Level shifter 338: Level shifter

140: Digital/Analog Converter 340: Digital/Analog Converter

200: source driver 402: first voltage divider

202: Power supply 404: Second voltage divider

204: Voltage drop detector 406: First comparator

206: Controller 408: Second comparator

208: Channel 410: The first inverter

210: channel 412: second inverter

212: multiplexer 414: third inverter

214: output terminal 416: fourth inverter

216: output port 418: level shifter

220: Voltage sharing switch 420: Fifth inverter

300: Source driver 422: NOR gate

302: Power supply 424: The sixth inverter

304: Pressure drop detector 426: OR gate.

Detailed ways

In order to make the description of the present invention more detailed and complete, reference may be made to the following description together with the illustrations in accompanying drawings 2 to 4 .

Please refer to FIG. 2 , which shows a schematic diagram of a source driver according to a preferred embodiment of the present invention. The source driver 200 in FIG. 2 is powered by a power supply 202, and the source driver 200 includes at least a plurality of channels (channel 208, channel 210...), at least one multiplexer (MUX) 212, multiple A output port (output port 214, output port 216...) is coupled to the channel via a multiplexer 212, a voltage sharing switch 220, a voltage drop detector 204 is connected to the power supply 202, and a control The detector 206 is connected to the voltage drop detector 204. The voltage equalizing switch 220 is electrically connected between the output ports 214 and 216 for equalizing the voltage of the output terminals when needed. The power supply 202 can provide a high potential first supply voltage and a low potential second supply voltage.

The voltage drop detector 204 can determine whether the power supply is on or off, and if yes, generates a reset signal RS. The determination of power on/off is by detecting whether one of the first supply voltage and the second supply voltage output from the power supply 202 is insufficient, that is, whether it is lower than a certain threshold.

The reset signal RS is sent to the controller 206 again. The controller 206 then generates a control signal CN according to the reset signal RS, and transmits the control signal CN to the voltage sharing switch 220 to turn off the voltage sharing switch 220 . This control signal CN is further transmitted to the multiplexer to disconnect the channel from the output port. Therefore, when the power supply 202 supplying power to the source driver is about to be turned on/off, abnormal data may occur. Not sent to the output port. Therefore, when the power supply is turned on/off, the display will continue to display the original image.

Please refer to FIG. 3 , which shows a schematic diagram of another source driver according to a preferred embodiment of the present invention. The source driver 300 in FIG. 3 is powered by a power supply 302, and the source driver 300 includes at least a channel 308 and a channel 310, a multiplexer (MUX) 312, an output port 314 and an output port 316, and a data bus 318 , a voltage equalizing switch 320 , a voltage drop detector 304 connected to the power supply 302 , and a controller 306 connected to the voltage drop detector 304 . Output port 314 and output port 316 are coupled to channel 308 and channel 310 via multiplexer 312 . The voltage equalizing switch 320 is electrically connected between the output port 314 and the output port 316 of the source driver 300 for equalizing the voltage of the output terminal when needed.

Each channel has a shift register (322 or 332), a latch unit (323 or 333), a level shifter (328 or 338), and a digital/analog converter (DAC) (330 or 340). Each latch unit at least includes a first latch (324 or 334) connected in series with a second latch (326 or 336). The data is transmitted on the data bus 318 and stored in the latch unit. What's more, the data is first stored in the first latch and then stored in the second latch.

When the power supply 302 normally supplies power to the source driver 300, the data in the channel will be input to the multiplexer 312, and then sent to a display (not shown in the figure) through the output port 314 and the output port 316, so as to The corresponding image is displayed on the display. However, when the power supply 302 is about to be turned on or off, the voltage delivered to the source driver 300 starts to be insufficient. If the output voltage of the power supply 302 is insufficient, the voltage drop detector 304 generates a reset signal RS, and sends the reset signal RS to the controller 306 to generate a control signal CN according to the reset signal RS. The control signal CN is sent to the voltage equalizing switch 320 to turn off the voltage equalizing switch 320 . Then, the control signal CN is also transmitted to the data bus 318 to set the data transmitted on the data bus 318 to a default value. What's more, the control signal CN is also transmitted to the latch units 323 and 333 to keep the latch units 323 and 333 turned on, so as to output data from the latch units 323 and 333 . The control signal CN is further sent to the multiplexer 312 to keep the multiplexer 312 turned on so as to output a driving voltage through the output port according to the above data. Therefore, the output port 314 and the output port 316 will output the preset voltage to a display (not shown in the figure). Therefore, when the power supply is turned on/off, the display will display a corresponding black or white picture.

It should be noted that in other embodiments of the present invention, the voltage sharing switch is optional. Therefore, in other embodiments of the present invention, when the power supply 302 is about to be turned on or off, that is, when the first supply voltage is insufficient, the step of turning off the voltage equalizing switch is also optional. What's more, in the preferred embodiment of the present invention, the step of keeping the latch unit turned on is to keep the second latch turned on.

The structure of the voltage drop detector and the generation of the reset signal RS will be described in detail below.

Please refer to FIG. 4 , which shows a schematic diagram of a pressure drop detector according to a preferred embodiment of the present invention. The voltage drop detector 304 in FIG. 4 includes at least a first voltage divider 402, a second voltage divider 404, a first comparator 406, a second comparator 408, a first inverter 410, and a second inverter 412. , a third inverter 414 , a fourth inverter 416 , a level shifter 418 , a fifth inverter 420 and an OR gate 426 . The OR gate 426 at least includes a NOR gate 422 connected in series with a sixth inverter 424 . The first voltage divider 402 includes resistors R1 to R7 connected in series, and the second voltage divider 404 includes resistors R11 to R16 connected in series.

The first voltage divider 402 generates a first divided voltage V A1 according to the first supply voltage VDDA output from the power supply, and the second voltage divider 404 generates a first divided voltage V _A1 according to the second supply voltage VDDD output from the power supply. The first comparator 406 compares the first divided voltage V _A1 with the threshold voltage V _TH , and generates a first comparison signal _RSA . If the first divided voltage V _A1 is less than the threshold voltage V _TH , the first comparison signal RSA is at a high potential, indicating that the voltage of the power supply is insufficient because the power supply is about to be turned on/off. If the first divided voltage V _A1 is greater than the threshold voltage V _TH , the first comparison signal RSA is at a low level, indicating that the power supply supplies power to the source driver normally.

Similarly, the second comparator 408 compares the second divided voltage V _D1 with the threshold voltage V _TH , and generates a second comparison signal RSD. If the second divided voltage V _D1 is smaller than the threshold voltage V _TH , the second comparison signal RSD is at a high potential, indicating that the power supply is about to be turned on/off. If the second divided voltage V _D1 is greater than the threshold voltage V _TH , the second comparison signal RSD is at a low potential, indicating that the power supply supplies power to the source driver normally. Compared with the second supply voltage VDDD, the first supply voltage VDDA is a high voltage, the first comparator is a high voltage element, and the second comparator is a low voltage element. The setting and changing of the first divided voltage V _A1 , the second divided voltage V _D1 and the threshold voltage V _TH can be determined by the user.

The threshold voltage V _TH is generated by a circuit that is not easily affected by the output voltage drop of the power supply, such as a band-gap voltage generator.

The first comparison signal RSA is transmitted to an input terminal of the OR gate 426 through the first inverter 410 and the second inverter 412 . The second comparison signal RSD is transmitted to the level shifter 418 through the third inverter 414 and the fourth inverter 416 to shift the level of the second comparison signal RSD. The level-shifted second comparison signal RSD is sent to the other input terminal of the OR gate 426 via the fifth inverter 420 . If both the first comparison signal RSA and the second comparison signal RSD are at low level, the OR gate 426 outputs a low level signal, indicating that the power supply supplies power to the source driver normally, and therefore, the reset signal will not be generated. Conversely, if the first comparison signal RSA and/or the second comparison signal RSD are at high potential, the OR gate 426 outputs a high potential signal, indicating that the power supply is about to be turned on/off, and the reset signal RS is generated.

From the above preferred embodiments of the present invention, one advantage of the present invention is that the present invention can reduce abnormal images displayed on the display when the power supply is turned on/off.

It can be seen from the above-mentioned preferred embodiments of the present invention that another advantage of the present invention is that the present invention uses a voltage drop detector to detect whether the power supply is being turned on/off, and if so, generate a reset signal.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the patent scope of the present invention.

Claims (7)

1. A method for suppressing noise output from a source driver when a power supply is turned on/off, the source driver comprising a data bus, a plurality of channels, a multiplexer, and a plurality of output ports, the channels being coupled to the output ports via the multiplexer, each of the channels having a latch unit, data being transmitted on the data bus and stored in the latch unit, the source driver being powered by a first supply voltage output from the power supply, the method comprising:

judging whether the first supply voltage is insufficient, if so, performing the following steps:

setting the data transmitted on the data bus to a default value;

maintaining the latch unit to be turned on so that the data is output from the latch unit; and

keeping the multiplexer open to output a driving voltage via the output port according to the data,

wherein,

the step of maintaining the multiplexer on is performed by transmitting the control signal to the multiplexer, the control signal being generated in response to a reset signal, and the reset signal being generated if the result of the determining step is positive,

the reset signal is generated by comparing a first divided voltage generated according to the first supply voltage with a threshold voltage, and generating the reset signal if the first divided voltage is less than the threshold voltage,

the source driver is further powered by a second supply voltage output by the power supply, and the reset signal is generated by comparing a second divided voltage with the threshold voltage, the second divided voltage being generated according to the second supply voltage, and the reset signal being generated if the second divided voltage is less than the threshold voltage.

2. The method of claim 1, wherein the first divided voltage is generated by dividing the first supply voltage using a first voltage divider.

3. The method of claim 1, wherein the second divided voltage is generated by dividing the second supply voltage using a second voltage divider.

4. A method as claimed in claim 1, wherein said latch unit comprises a first latch and a second latch connected in series, said data being stored in said first latch before being stored in said second latch, and said step of maintaining said latch unit open maintains said second latch open.

5. A source driver powered by a power supply, the source driver comprising:

a data bus;

at least two channels, each channel is provided with a latch unit, and data are transmitted on the data bus and stored in the latch unit;

a multiplexer;

at least two output ports coupled to the channels via the multiplexer; and

a voltage drop detector for detecting whether the first supply voltage and the second supply voltage outputted by the power supply are insufficient, and if not, generating a reset signal, the voltage drop detector at least comprising:

a first voltage divider for generating a first divided voltage according to the first supply voltage;

a first comparator for comparing the first divided voltage with a threshold voltage;

a second voltage divider for generating a second divided voltage according to a second supply voltage output from the power supply;

a second comparator for comparing the second divided voltage with the threshold voltage to determine whether the second supply voltage is insufficient; and

an OR gate having two input terminals respectively connected to the output terminals of the first comparator and the second comparator for outputting the reset signal,

if the reset signal is generated, setting the data transmitted on the data bus as a default value, starting the latch unit to enable the data to be output from the latch unit, and starting the multiplexer to output a driving voltage through the output port according to the data; and

every two adjacent output ports are connected through a voltage sharing switch, and the source driver further comprises a controller for turning off the voltage sharing switch and keeping the multiplexer on according to the reset signal.

6. The source driver of claim 5, wherein the first supply voltage is a high voltage compared to the second supply voltage, the first comparator is a high voltage device, and the second comparator is a low voltage device.

7. The source driver as claimed in claim 6, wherein the voltage drop detector further comprises a level shifter connected between the second comparator and the OR gate.

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