Embodiment
The technical scheme that further specifies below in conjunction with drawings and Examples.
Referring to Fig. 2.Reference signal generating circuit is made up of first reference voltage source circuit, second reference voltage source circuit, pulse-width modulation circuit and low-pass filter circuit.First reference voltage source circuit is made up of capacitor C 201 and chip IC 201, and the IC201 of present embodiment adopts MX584 reference voltage source integrated chip.6,7 pin of chip IC 201 are connected with the two ends of capacitor C 201 respectively, and 8,4 pin of chip IC 201 are connected with ground with DC power supply+5V respectively, and 1 pin of chip IC 201 is connected 20 pin of the chip IC of delivering to again in the pulse-width modulation circuit 203 with 3 pin.Second reference voltage source circuit is made up of capacitor C 202, resistance R 208, chip IC 202, and the IC202 of present embodiment adopts MX584 reference voltage source integrated chip.1,3,8 pin of chip IC 202 and an end common ground of capacitor C 202,4 pin of chip IC 202 are connected with an end of the other end of capacitor C 202, resistance R 208, deliver to 7 pin of the chip IC 203 in the pulse-width modulation circuit again, the other end of resistance R 208 is connected with DC power supply-5V.Pulse-width modulation circuit is made up of capacitor C 203, C204, chip IC 203, chip IC 204, and the IC203 in the present embodiment adopts ADG788 analog switch chip, and IC204 adopts OP-07A integrated operational amplifier chip.2 pin of chip IC 203,4 pin and 5 pin common grounds, 14 pin of chip IC 203 are connected with an end of DC power supply+2.5V, capacitor C 203,3 pin of chip IC 203 are connected with an end of DC power supply-2.5V, capacitor C 204, the other end common ground of the other end of capacitor C 203, C204,11 pin of chip IC 203,13 pin are connected with 1 pin, 6 pin of chip IC 203 respectively, 19 pin of chip IC 203,8 pin connect signal leading-in end SCLK jointly, 9 pin of chip IC 203 connect signal leading-in end SCTRL, and 12 pin of chip IC 203 connect 3 pin of chip IC204.7 pin of chip IC 204 and 4 pin be connected respectively DC power supply+15V and-15V, 2 pin of chip IC 204 are connected with 6 pin, deliver to an end of the resistance R 201 in the low-pass filter circuit again.Low-pass filter circuit is made up of resistance R 201-R206, capacitor C 205-C210, chip IC 205-IC207, and the IC205-IC207 of present embodiment adopts OP-07A integrated operational amplifier chip.7 pin of chip IC 205-IC207 and 4 pin are connected with-15V with DC power supply+15V respectively, one end of the other end of resistance R 201 and resistance R 202, one end of capacitor C 206 connects, one end of the other end of resistance R 202 and capacitor C 205,3 pin of chip IC 205 connect, the other end ground connection of capacitor C 205,6 pin of the other end of capacitor C 206 and chip IC 205, one end of 2 pin and resistance R 203 links to each other, one end of the other end of resistance R 203 and resistance R 204, one end of capacitor C 208 links to each other, one end of the other end of resistance R 204 and capacitor C 207,3 pin of chip IC 206 connect, the other end ground connection of capacitor C 207,2 pin of the other end of capacitor C 208 and chip IC 206, one end of 6 pin and resistance R 205 connects, one end of the other end of resistance R 205 and resistance R 206, one end of capacitor C 210 connects, one end of the other end of resistance R 206 and capacitor C 209,3 pin of chip IC 207 connect, the other end ground connection of capacitor C 209,2 pin of the other end of capacitor C 210 and chip IC 207,6 pin and reference signal exit Vbz connect.First reference voltage source circuit and second reference voltage source circuit take place respectively+2.5V and-the accurate reference dc voltage fixed signal of 2.5V high accuracy, low drift, this signal is delivered to pulse-width modulation circuit.Pulse-width modulation circuit is modulated into duty ratio and frequency with accurate reference dc voltage fixed signal and equals the duty ratio of rectangular modulation signal and frequency, low level and equal pulse-width modulation (PWM) ripple that 0V, high level equal reference voltage.The PWM ripple is connected to low-pass filter circuit, filters alternating component by low-pass filter circuit, produces the voltage division signal by the accurate reference dc voltage of rectangular modulation signal dutyfactor dividing potential drop.When the duty ratio from 0 to 1 of the rectangular modulation signal of pulse-width modulation circuit step by step during step change, the signal exit of reference signal generating circuit (Vbz end) will obtain from 0V to 2.5V or the serial voltage division signal of the reference dc voltage of step increments step by step from-2.5V to 0V.
Referring to Fig. 3.Signal detection and calibration circuit is made up of multiple signals selecting circuit, filter circuit, range automatic switching circuit and signal amplitude translation circuit.The multiple signals selecting circuit is made up of zero sequence current mutual inductor TAN, resistance R 301-R304, chip IC 301, chip IC 302A, and the IC301 of present embodiment adopts CD4051 multiplexer chip, and IC302 adopts TL084 integrated operational amplifier chip.Triple line A, B, C passes the iron core of zero sequence current mutual inductor TAN, one end ground connection of zero sequence current mutual inductor TAN secondary side, the other end is connected with resistance R 301,12 pin of the other end of resistance R 301 and chip IC 301, one end of resistance R 302 connects, the other end ground connection of resistance R 302,13 pin of chip IC 301 meet lead terminal VIA, 14 pin of chip IC 301 meet lead terminal VIB, 15 pin of chip IC 301 meet lead terminal VIC, lead terminal VIA, VIB, VIC is connected with current signal detection circuit, 1 pin of chip IC 301 connects by the next lead terminal Vbz of reference signal generating circuit, one end of resistance R 303 and+2.5V power supply, 5 pin of chip IC 301 connect, the other end of resistance R 303,2 pin of chip IC 301,6 pin, one end ground connection of 8 pin and resistance R 304,4 pin of the other end of resistance R 304 and IC301 are connected with-2.5V power supply, 16 pin of chip IC 301 connect+the 5V power supply, 7 pin of chip IC 301 connect-the 5V power supply, 9 pin of chip IC 301 meet lead terminal XC, 10 pin of chip IC 301 meet lead terminal XB, 11 pin of chip IC 301 meet lead terminal XA, lead terminal XA, XB is connected with association's data processing and response circuit with XC, 3 pin of chip IC 301 connect 3 pin of chip IC 302A, 4 pin of chip IC 302A connect+the 12V power supply, 11 pin of chip IC 302A connect-the 12V power supply, 2 pin of chip IC 302A with connect filter circuit after 1 pin links to each other.Filter circuit is made up of resistance R 305, R306, capacitor C 301, C302 and chip IC 302B, one end of resistance R 305 connects 1 pin of chip IC302A, the other end of resistance R 305 connects an end of resistance R 306 and an end of capacitor C 302, the other end of resistance R 306 is connected with 5 pin of chip IC 302B, an end of capacitor C 301, the other end ground connection of capacitor C 301, the other end of capacitor C 302 connects range automatic switching circuit with 6 pin, 7 pin of chip IC 302B after being connected.Range automatic switching circuit is made up of resistance R 308, R310-R312, three terminal potential device R307, R309, chip IC 303A, IC303B, chip IC 302C, IC302D and chip IC 406D, IC303 in the present embodiment adopts LM339 comparator chip, and IC406 adopts ADG788 integrated switching circuit chip.5 pin of chip IC 303A are connected with 15 pin of 6 pin of chip IC 303B, chip IC 406D, 7 pin of chip IC 302B and an end of resistance R 311, one termination of three terminal potential device R307+5V power supply, the other end ground connection of three terminal potential device R307,4 pin of the 3rd chip termination IC303A of three terminal potential device R307, one termination of three terminal potential device R309-5V power supply, the other end ground connection of three terminal potential device R309,7 pin of the 3rd chip termination IC303B of three terminal potential device R309.3 pin of chip IC 303A and an end of resistance R 308, + 5V power supply links to each other, the 12 pin ground connection of chip IC 303A, 2 pin of the other end of resistance R 308 and chip IC 303A, 1 pin of chip IC 303B, 18 pin of chip IC 406D, lead terminal HF connects, the other end of resistance R 311 is connected with 10 pin of chip IC 302C, one end ground connection of resistance R 310,9 pin of the other end and chip IC 302C, one end of resistance R 312 connects, the other end of resistance R 312 is connected with 8 pin of chip IC 302C and 17 pin of chip IC 406D, 16 pin of chip IC 406D connect 12 pin of chip IC 302D, 13 pin of chip IC 302D, 14 pin link to each other, and are connected to signal amplitude translation circuit.Signal amplitude translation circuit is by resistance R 313-R318, chip IC 407D forms, IC407D in the present embodiment adopts TL084 integrated operational amplifier chip, 14 pin of one chip termination IC302D of resistance R 316,12 pin of resistance R 316 another termination chip IC 407D and an end of resistance R 317, one end ground connection of resistance R 313, the other end of resistance R 313 is connected with 13 pin of chip IC 407D and an end of resistance R 314, the other end of resistance R 314 links to each other with 14 pin of chip IC 407D and an end of resistance R 315, another termination lead terminal CHC1+ of resistance R 315, the other end of resistance R 317 links to each other with an end of normal voltage signal terminal VREF and resistance R 318, another termination lead terminal CHC1-of resistance R 318.The output of multiple signals selecting circuit connects filter circuit, and the output of filter circuit connects range automatic switching circuit, and the output of range automatic switching circuit connects signal amplitude translation circuit.The multiple signals selecting circuit passes through XA, XB, three signal terminal gatings of XC analog signal input channel IN0~IN7 by association's data processing and response circuit, can receive threephase current transformer (CT) successively but A phase current signal VIA, B phase current signal VIB, C phase current signal VIC and the normal voltage signal Vbz, the fixed standard voltage signal+2.5V that regulate of stepping ,-2.5V and ground signalling, and the voltage signal that changes from the reflection zero-sequence current amplitude of zero sequence current mutual inductor TAN.The follow-up processing flow of multiple signals selecting circuit output signal is identical with the signal processing flow of each sense channel in the current signal detection circuit, this signal filters radio-frequency component outside the monitoring range through filter circuit, select gain amplifier by range automatic switching circuit according to the amplitude of signal again, after signal amplitude translation circuit receives this conversion of signals for suitable analog to digital converter signal.
Referring to Fig. 4.Current signal detection circuit is divided into first sense channel, second sense channel and the 3rd sense channel, detect A, B, C three-phase current signal respectively, each passage is made up of current signal acquisition cuicuit, filter circuit, range automatic switching circuit and signal amplitude translation circuit respectively.The current signal acquisition cuicuit of first sense channel is made up of current transformer TA1, resistance R 401, R402, chip IC 401A, and the IC401-IC403 of present embodiment, IC407 all adopt TL084 integrated operational amplifier chip.The A phase line is passed the iron core of current transformer TA1, one end of current transformer TA1 secondary side is connected with an end of resistance R 401, the other end of resistance R 401 is connected with an end of resistance R 402,3 pin of chip IC 401A, 3 pin of chip IC 401A connect signal lead terminal VIA, lead terminal VIA is connected with signal detection and calibration circuit, the other end ground connection of the other end of resistance R 402, current transformer TA1 secondary side, 1 pin, 2 pin of chip IC 401A connect filter circuit, 4 pin of chip IC 401A, 11 pin connect respectively power supply+12V ,-12V.The filter circuit of first sense channel is made up of resistance R 403, R404, capacitor C 401, C402, chip IC 401B, one end of resistance R 403 connects 1 pin of chip IC401A, the other end of resistance R 403 connects an end of resistance R 404 and an end of capacitor C 402, the other end of resistance R 404 connects 5 pin of chip IC401B, an end of capacitor C 401, the other end ground connection of capacitor C 401,6 pin and 7 pin of another termination chip IC 401B of capacitor C 402,7 pin of integrated operational amplifier IC401B connect range automatic switching circuit.The range automatic switching circuit of first sense channel is by resistance R 407-R410, three terminal potential device R405, R406, chip IC 404A and IC404B, chip IC 401C and IC401D, and chip IC 406A forms, IC404 in the present embodiment adopts LM339 comparator chip, and IC406 adopts ADG788 integrated switching circuit chip.2 pin of 5 pin of chip IC 404A, 6 pin of chip IC 404B, chip IC 406A and an end of resistance R 409 are connected with 7 pin of chip IC 401B, one termination of three terminal potential device R405+5V power supply, the other end ground connection of three terminal potential device R405,4 pin of the 3rd chip termination IC404A of three terminal potential device R406, one termination of three terminal potential device R406-5V power supply, the other end ground connection of three terminal potential device R406,7 pin of the 3rd chip termination IC404B of three terminal potential device R406.3 pin of chip IC 404A and an end of resistance R 407, + 5V power supply links to each other, the 12 pin ground connection of chip IC 404A, 2 pin of the other end of resistance R 407 and chip IC 404A, 1 pin of chip IC 404B, 19 pin of chip IC 406A, lead terminal HA connects, lead terminal HA handles with master data and response circuit is connected, the other end of resistance R 409 is connected with 10 pin of chip IC 401C, one end ground connection of resistance R 408,9 pin of the other end of resistance R 408 and chip IC 401C, one end of resistance R 410 connects, 8 pin of the other end of resistance R 410 and chip IC 401C, 20 pin of IC406A connect, 14 pin of chip IC 406A connect+the 2.5V power supply, 3 pin of chip IC 406A connect-the 2.5V power supply, the 4 pin ground connection of chip IC 406A, 1 pin of chip IC 406A connects 12 pin of chip IC 401D, 13 pin of chip IC 401D, 14 pin link to each other, and are connected to signal amplitude translation circuit.The signal amplitude translation circuit of first sense channel is made up of resistance R 411-R416 and chip IC 407A, 14 pin of one chip termination IC401D of resistance R 412,3 pin of another termination chip IC 407A of resistance R 412 and an end of resistance R 413, one end ground connection of resistance R 411,2 pin of the other end of resistance R 411 and chip IC 407A, one end of resistance R 415 connects, 1 pin of the other end of resistance R 415 and chip IC 407A, one end of resistance R 416 links to each other, 4 pin of chip IC 407A connect+the 12V power supply, 11 pin of chip IC 407A connect-the 12V power supply, another termination lead terminal CHA0+ of resistance R 416, the other end of resistance R 413 and normal voltage signal terminal VREF, one end of resistance R 414 links to each other, another termination lead terminal CHA0-of resistance R 414, lead terminal HA, CHA0+, CHA0-exports master data to and handles and response circuit.The composition of second sense channel and the 3rd sense channel, structure are identical with first sense channel respectively, the input signal of second sense channel comes from current transformer TA2 and master data is handled and the normal voltage signal lead terminal VREF of response circuit, and the lead terminal of output signal has VIB, HB, CHB0+, CHB0-.The input signal of the 3rd sense channel comes from current transformer TA3 and normal voltage signal terminal VREF, and the lead terminal of output signal has VIC, HC, CHC0+, CHC0-.The input of current signal acquisition cuicuit connects main circuit, and its output connects filter circuit, and the output of filter circuit connects range automatic switching circuit, and the output of range automatic switching circuit connects signal amplitude translation circuit.Main circuit A, B, C three-phase current produce the voltage signal that reflection main circuit current amplitude changes through the current signal acquisition cuicuit respectively, this signal filters radio-frequency component outside the monitoring range through filter circuit, select gain amplifier by range automatic switching circuit according to the amplitude of signal again, after signal amplitude translation circuit receives this conversion of signals for suitable analog to digital converter signal.
Referring to Fig. 5.The sampling rate control circuit is by line voltage fundamental signal acquisition cuicuit, keep square-wave signal generative circuit, the frequency multiplication of phase locked loop circuit of same frequency to form with the line voltage first-harmonic, three parts connect successively, its effect is the square-wave signal that the line voltage fundamental signal is converted to real-time tracking line voltage fundamental frequency, again this square-wave signal is carried out process of frequency multiplication, generate the synchronized sampling control wave that has integral multiple relation and tracking line voltage fundamental signal frequency change with line voltage fundamental signal frequency.Line voltage fundamental signal acquisition cuicuit is made up of voltage transformer TV, chip IC 501, resistance R 501-R506 and capacitor C 501-C506, and the IC501 of present embodiment adopts TL084 integrated operational amplifier chip.One end of voltage transformer TV primary side is connected with electrical network phase line A, and the other end of voltage transformer TV primary side is connected with network neutral line N.One end of resistance R 501 is connected with an end of voltage transformer TV secondary side, the other end of resistance R 501 is connected with an end of resistance R 502 and an end of capacitor C 501, the other end of resistance R 502 is connected with 3 pin of chip IC 501A, an end of capacitor C 502, the other end ground connection of the other end of capacitor C 502, voltage transformer TV secondary side, 4 pin of chip IC 501A, 11 pin respectively with DC power supply+12V ,-12V is connected, 1 pin of chip IC 501A, 2 pin are connected with the other end of capacitor C 501 and an end of resistance R 503.The other end of resistance R 503 is connected with an end of resistance R 504, an end of capacitor C 503, the other end of resistance R 504 is connected with 5 pin of chip IC 501B, an end of capacitor C 504, the other end ground connection of capacitor C 504,7 pin of chip IC 501B, 6 pin are connected with the other end of capacitor C 503 and an end of resistance R 505.The other end of resistance R 505 is connected with an end of resistance R 506, an end of capacitor C 505, the other end of resistance R 506 is connected with 10 pin of chip IC 501C, an end of capacitor C 506, the other end ground connection of capacitor C 506,8 pin of chip IC 501C, 9 pin are connected with the square-wave signal generative circuit with the other end of capacitor C 505.Line voltage transforms to secondary side through voltage transformer TV and obtains voltage signal, obtain the voltage fundamental signal through the filtering link that is made of chip IC 501, resistance R 501-R506 and capacitor C 501-C506, this signal is sent into the square-wave signal generative circuit that keeps same frequency with the line voltage first-harmonic.Keep the square-wave signal generative circuit of same frequency to form with the line voltage first-harmonic by voltage comparator circuit, integrated schmidt trigger, wherein voltage comparator circuit is made of integrated voltage comparator IC502 and peripheral components R507-R509, the IC502 of present embodiment adopts LM339 voltage comparator chip, and IC503 adopts CC40106 integrated schmidt trigger chip.An end of resistance R 507 is connected with 8 pin of line voltage fundamental signal acquisition cuicuit chips IC501C in the voltage comparator circuit, the other end of resistance R 507 is connected with 4 pin of chip IC 502,5 pin of chip IC 502 link to each other with an end of resistance R 508,2 pin of chip IC 502 are connected with an end of 1 pin of chip IC 503 and resistance R 509, the other end of resistance R 508,12 pin ground connection of chip IC 502, the other end of resistance R 509,3 pin of chip IC 502 connect+the 5V power supply, 7 pin ground connection of chip IC 503,14 pin of chip IC 503 connect+the 5V power supply, and 2 pin of chip IC 503 connect 14 pin of frequency multiplication of phase locked loop circuit chips IC504.Convert the square-wave signal of same frequency to through voltage comparator circuit from the voltage fundamental signal of line voltage fundamental signal acquisition cuicuit, what be shaped as rule through integrated schmidt trigger again keeps the square-wave signal of same frequency with the line voltage first-harmonic, and this signal is sent into the frequency multiplication of phase locked loop circuit.The frequency multiplication of phase locked loop circuit is made up of chip IC 504, IC505, capacitor C 507, C508 and resistance R 510-R512, and the chip IC 504 of present embodiment adopts CC4046 digital phase-locked loop integrated chip IC505 to adopt CC4040B binary counter chip.11 pin of chip IC 504 are connected with an end of resistance R 510, the other end of resistance R 510,5 pin of chip IC 504 and 8 pin ground connection, the end of 13 pin connecting resistance R511 of chip IC 504, the other end of resistance R 511, one end of resistance R 512 is connected with 9 pin of chip IC 504, the other end of resistance R 512 is connected with an end of capacitor C 507, the other end ground connection of capacitor C 507,16 pin of chip IC 504 connect+the 5V power supply, 6 pin of chip IC 504 connect an end of capacitor C 508,7 pin of chip IC 504 connect the other end of capacitor C 508,4 pin of chip IC 504,3 pin respectively with 10 pin of chip IC 505,13 pin are connected, 16 pin of chip IC 505 connect+the 5V power supply, 11 pin of chip IC 505 and 8 pin ground connection, the lead terminal fN of sampling rate control wave output connects 4 pin of chip IC504 and 10 pin of chip IC 505, and lead terminal fN handles with master data and response circuit is connected.From keeping the regular square-wave signal of the square-wave signal generative circuit of same frequency with the line voltage first-harmonic, through frequency-tracking, phase locking and the frequency division feedback effect of frequency multiplication of phase locked loop circuit, output has the integral multiple relation and follows the tracks of the synchronized sampling control wave fN of line voltage fundamental signal frequency change with line voltage fundamental signal frequency.
Referring to Fig. 6.Master data is handled and response circuit is made up of analog to digital conversion circuit, digital signal processing circuit and release control circuit, analog to digital conversion circuit is made up of chip IC 601 and chip IC 606, IC601 adopts the ADS8364 modulus conversion chip in the present embodiment, and IC606 adopts OP-07A integrated operational amplifier chip.Analog to digital conversion circuit receives the analog signal that comes from current signal detection circuit by CHA0+, CHA0-, CHB0+, CHB0-, six lead terminals of CHC0+, CHC0-, receive the analog signal that comes from signal detection and calibration circuit by two lead terminals of CHC1+, CHC1-, provide the normal voltage signal to current signal detection circuit and signal detection and calibration circuit by lead terminal VREF.Lead terminal CHA0+, CHA0-respectively with 63 pin of chip IC 601,64 pin connect, lead terminal CHB0+, CHB0-respectively with 6 pin of chip IC 601,7 pin connect, lead terminal CHC0+, CHC0-respectively with 16 pin of chip IC 601,17 pin connect, pin terminals CHC1+, CHC1-respectively with 19 pin of chip IC 601,18 pin connect, lead terminal VREF is connected with 2 pin with 6 pin of chip IC 606,4 pin of chip IC 606,7 pin respectively with-15V power supply, + 15V power supply connects, 3 pin of chip IC 606 are connected with 62 pin with 61 pin of chip IC 601,3 of chip IC 601,8,13,59 and 22 pin connect+the 5V power supply, 4 of chip IC 601,9,14,60,21,5,10,15,25,32 link to each other with ground with 49 pin, the A0-A2 port of chip IC 601, the D0-D15 port, CS, RD, EOC, CLK, HOLDA, HOLDB, HOLDC links to each other with digital signal processing circuit respectively with the RESET port, the BYTE port of chip IC 601, the ADD port is connected with ground, the BVDD port of chip IC 601 is connected, and is connected to digital signal processing circuit with+3.3V power supply.Chip IC 601 is under the coordination of CS, RD, EOC, CLK, HOLDA, HOLDB, HOLDC, RESET port and A0-A2 port, and analog to digital conversion circuit passes to digital signal processing circuit with transformation result by the D0-D15 port.Digital signal processing circuit is made up of chip IC 602, chip IC 603, capacitor C 601-C605, inductance L 601, resistance R 601 and crystal oscillator CT601, IC602 adopts the TMS320LF2407A DSP chip in the present embodiment, and IC603 adopts three-way-eight line decoder chips of 74LV138.The D0-D15 port of chip IC 602 links to each other with the D0-D15 port of IC601 in the analog to digital conversion circuit respectively, connects lead terminal D0-D15 again.The RD of chip IC 602, XINT2, T4PWM, the RS port respectively with analog to digital conversion circuit in the RD of IC601, EOC, CLK, the RESET port links to each other, 56 pin of IC601 in 81 pin of chip IC 602 and the analog to digital conversion circuit, 57 pin link to each other with 58 pin, 3 of chip IC 602,41,66,76,94,125 link to each other with ground with 140 pin, 4 of chip IC 602,42,67,77, in 95 and 141 pin and+3.3V power supply and the analog to digital conversion circuit 24 of IC601,50 pin link to each other, the IS port of chip IC 602 is connected with the E2 port with the E1 of IC603, the A0-A10 port of chip IC 602 is connected with lead terminal A0-A10, wherein A0-A2 is connected with the A0-A2 port of IC601 in the analog to digital conversion circuit simultaneously, 123 pin of chip IC 602 and an end of capacitor C 601, the end of crystal oscillator CT601 connects, 124 pin of another termination chip IC 602 of crystal oscillator CT601, one end of capacitor C 602, the other end of capacitor C 601 links to each other with ground with the other end of capacitor C 602.11 pin of chip IC 602 and an end of resistance R 601, one end of capacitor C 604 connects, the other end of resistance R 601 is connected with an end of capacitor C 603,10 pin of chip IC 602 and the other end of capacitor C 603, the other end of capacitor C 604 connects, 29 of chip IC 602,50,86 link to each other with+3.3V power supply with an end of 129 pin and inductance L 601,12 pin of chip IC 602 link to each other with an end of the other end of inductance L 601 and capacitor C 605, the other end of capacitor C 605,28 of chip IC 602,49,85,128 pin are connected with ground, 52 pin of chip IC 602 connect the release control circuit, the IOPB1 of chip IC 602, IOPB2, IOPB3, the IOPB4 port meets lead terminal HA respectively, HB, HC, HF, the IOPA4 of chip IC 602, the IOPA5 port meets lead terminal BUSYL respectively, fN, the R/W of chip IC 602, the RD port meets lead terminal R/W respectively, RD, the Y0 port of chip IC 603 connects the CS port of chip IC 601, the Y1 port of chip IC 603 meets lead terminal CE, the E3 of chip IC 603 and GND port ground connection, the VCC port of chip IC 603 connects+the 3.3V power supply.Chip IC 602 is under the coordination of the sampling rate control circuit that lead terminal fN introduces, the sample frequency of control chip IC601, judge the range of current signal detection circuit and signal detection and calibration circuit according to the state of lead terminal HA, HB, HC and HF, chip IC 602 is by the coordinated of lead terminal CE, RD, BUSYL, R/W, A0-A10, D0-D15, with association's data processing and response circuit swap data.The release control circuit is made up of chip IC 604, chip IC 605, resistance R 602-R604, diode D601, triode Q601 and magnetictrip coil C, present embodiment chips IC604 adopts 7404 inverter chips, and IC605 adopts TIL117 photoelectrical coupler chip.1 pin of chip IC 604 is connected with 52 pin of chip IC 602,14 pin of chip IC 604,7 pin connect respectively+5V power supply and ground, 2 pin of chip IC 604 are connected with 2 pin of chip IC 605, the end of 1 pin connecting resistance R602 of chip IC 605, another termination+5V power supply of resistance R 602,5 pin of chip IC 605 connect+the 12V power supply, the negative electrode of diode D601, the end of magnetictrip coil C, the end of 4 pin connecting resistance R603 of chip IC 605, the end of the other end connecting resistance R604 of resistance R 603, the base stage of triode Q601, the other end of resistance R 604, the grounded emitter of triode Q601, the anode of diode D601, the collector electrode of another termination triode Q601 of magnetictrip coil C.Analog to digital conversion circuit receives the analog signal that comes from current signal detection circuit and signal detection and calibration circuit, under the control of digital signal processing circuit, finish the conversion of analog quantity to digital quantity, and transformation result delivered to digital signal processing circuit, digital signal processing circuit is processed the digital quantity that collects and is judged, data after the processing are delivered to association's data processing and response circuit, digital signal processing circuit is then finished tripping operation action control by the release control circuit through judging as needing the control circuit breaker trip.
Referring to Fig. 7.Association's data processing and response circuit are made up of association's data processing circuit and keyboard-display circuit, association's data processing circuit is made up of chip IC 701, chip IC 702, chip IC 703, chip IC 704, resistance R 701, capacitor C 701-C703, button K and crystal oscillator CT701, IC701 in the present embodiment adopts IDT7133 double-port RAM chip, IC702, IC703 adopt the ternary homophase latch of 74LS373 chip, and IC704 adopts the N87C196KC singlechip chip.Association's data processing circuit is by lead terminal D0-D15, CE, A0-A10, RD, BUSYL, R/W, handle and the response circuit swap data with master data, the 1-16 pin of chip IC 701 connects lead terminal D0-D15 successively, 52 pin of chip IC 701 connect lead terminal CE, the 54-64 pin of chip IC 701 connects lead terminal A0-A10 successively, 65 pin of chip IC 701 connect lead terminal RD, 53 pin of chip IC 701 connect lead terminal BUSYL, 66 pin of chip IC 701 are connected lead terminal R/W with 67 pin, 17 pin and 68 pin of chip IC 701 connect+the 5V power supply, 18 pin of chip IC 701 and 35 pin ground connection, the 42-49 pin of chip IC 701 is connected with the Q7-Q0 port of IC702 successively, 41 pin of chip IC 701,40 pin, 39 pin, 51 pin respectively with 2 pin of IC703,5 pin, 6 pin, 9 pin connect, the 19-26 pin of chip IC 701 connects the D0-D7 port of chip IC702 successively, the P3.0-P3.7 port of chip IC 704, the 27-34 pin of chip IC 701 connects the P4.0-P4.7 port of chip IC704 successively, the 27-30 pin of chip IC 701 connects the D0-D3 port of chip IC703 successively, 38 pin of chip IC 701,50 pin connect the P0.0 of chip IC704 respectively, the P0.1 port, 36 pin of chip IC 701 are connected 40 pin and 61 pin of chip IC704 with 37 pin, 20 pin of chip IC 702 and 20 pin of IC703 connect+the 5V power supply, 1 pin of chip IC 702 and IC703,10 pin connect the back and link to each other with ground, and 11 pin of chip IC 702 and IC703 are connected with 62 pin of chip IC 704 after linking to each other.1 pin of chip IC 704 connects+the 5V power supply, 14 pin of chip IC 704,36 pin and 68 pin ground connection, 16 pin of chip IC 704 and an end of resistance R 701, one end of capacitor C 701, the end of button K connects, the other end of button K, another termination+5V power supply of capacitor C 701, the other end ground connection of resistance R 701,67 pin of chip IC 704 and the end of crystal oscillator CT701, one end of capacitor C 702 connects, 66 pin of chip IC 704 and the other end of crystal oscillator CT701, one end of capacitor C 703 connects, the other end of capacitor C 702, the other end of capacitor C 703 is connected with ground, the P1.0-P1.3 port of chip IC 704 connects keyboard-display circuit, the P0.0-P0.4 port of chip IC 704 respectively with the lead terminal SCTRL of reference signal generating circuit, the XA of SCLK and signal detection and calibration circuit, XB, XC connects.Keyboard-display circuit is made up of chip IC 705, chip IC 706-IC713, button S0-S15, resistance R 702-R720 and capacitor C 704.IC705 adopts the HD7279A programmable keyboard to show common interface chip in the present embodiment, and IC706-IC713 all adopts eight sections light-emitting diode display chips of LTS547GF.The CS of chip IC 705, CLK, DATA, the KEY port is connected with the P1.0-P1.3 port of IC704 in the association data processing circuit successively, the SG of chip IC 705, SF, SE, SD, SC, SB, SA, the DP port successively with the end of resistance R 703-R710, the end of resistance R 711-R718 connects, the other end ground connection of resistance R 711-R718, the resistance R 703-R710 other end successively with the end of button S8-S15, the end of button S0-S7 connects, and with chip IC 706-IC713 g separately, f, e, d, c, b, a, the DP port connects, the DIG0-DIG7 port of chip IC 705 is connected with the G port of chip IC 706-IC713 successively, DIG6 port wherein, the DIG7 port is distinguished connecting resistance R720 again, the end of R719, the other end of resistance R 720 is connected with the other end of button S0-S7, the other end of resistance R 719 is connected with the other end of button S8-S15, the vdd terminal mouth of chip IC 705,28 pin connection+5V power supplys, the VSS port ground connection of chip IC 705,27 pin of chip IC 705 and an end of resistance R 702, one end of capacitor C 704 connects, another termination+5V power supply of resistance R 702, the other end ground connection of capacitor C 704.Association's data processing circuit receives the data that master data is handled and response circuit transmits, and delivers to keyboard-display circuit after handling and shows relevant information; Receive the key value of keyboard-display circuit, handle the back according to the information of operator's input or pass to the master data treatment circuit, or change content displayed; Control reference signal generating circuit and signal detection and calibration circuit.Keyboard-display circuit is responsible for receiving the keyboard value of operator's input, passes to association's data processing circuit then, receives the data display message that association's data processing circuit transmits simultaneously.
The present invention includes reference signal generating circuit, signal detection and calibration circuit, current signal detection circuit, sampling rate control circuit, master data processing and response circuit, association's data processing and response circuit.Reference signal generating circuit is assisted the control of data processing and response circuit, in current signal detection circuit input range scope, but produces the normal voltage signal that stepping is regulated.Signal detection and calibration circuit has three kinds of mode of operations under the control of association's data processing and response circuit, first kind is used to calibrate self passage, and second kind is used for the calibration current signal deteching circuit, and the third is used for the verification threephase current transformer.When first kind of mode of operation, the signal detection and calibration circuit collection comes from the serial reference voltage signal of reference signal generating circuit, sampled signal passes to master data and handles and response circuit, and the sampled data after master data processing and response circuit will be changed passes to association's data processing and response circuit.When second kind of mode of operation, signal detection and calibration circuit and current signal detection circuit keep synchronized sampling, collection comes from the signal of threephase current transformer (TA1, TA2, TA3), sampled signal passes to master data and handles and response circuit, and the sampled data after master data processing and response circuit will be changed sends association's data processing and response circuit to.When the third mode of operation, signal detection and calibration circuit is gathered the signal of threephase current transformer (TA1, TA2, TA3) and the signal of zero sequence current mutual inductor (TAN) simultaneously, sampled signal passes to master data and handles and response circuit, and the sampled data after master data processing and response circuit will be changed sends association's data processing and response circuit to.Current signal detection circuit handled by master data and response circuit is controlled, and gathers the signal that comes from threephase current transformer (TA1, TA2, TA3), and sampled signal sends master data to and handles and response circuit.The signal that the sampling rate control circuit will come from voltage transformer (TV) carries out low-pass filtering, obtain the voltage fundamental signal, then the line voltage fundamental signal is converted to the square-wave signal of real-time tracking line voltage fundamental frequency, again this square-wave signal is carried out process of frequency multiplication, generate the synchronized sampling control wave that has integral multiple relation and tracking line voltage fundamental signal frequency change with line voltage fundamental signal frequency, this signal is given master data and is handled and response circuit.Master data processing and response circuit and association's data processing and response circuit, sampling rate control circuit, current signal detection circuit, signal detection and calibration circuit are connected.After receiving the sampling rate control signal, the three-phase current signal that master data is handled and response circuit received current signal deteching circuit is gathered, received signal detects the analog signal that is used to calibrate of calibration circuit collection, finish analog quantity to the switching foundation of digital quantity, the digital quantity that collects is processed and judged, data after the processing are delivered to association's data processing and response circuit, master data is handled and the response circuit process is judged as need the control circuit breaker trip, then finishes the action control of tripping by the release control circuit.The operating current set point and the delay time set point of long delay overcurrent protection, short time delay overcurrent protection and instant over current protection that master data processing and response circuit reception association's data processing and response circuit transmit.Association data processing and response circuit and master data processing and response circuit, signal detection and calibration circuit, reference signal generating circuit are connected, and assist data processing and response current that four kinds of mode of operations are arranged.First kind is to handle and the response circuit swap data with master data; association's data processing and response circuit receive the operating current set point and the delay time set point of overcurrent protection from keyboard; and this series of values passed to master data is handled and response circuit; three-phase electricity flow valuve after three-phase current sampled data that the reception master data is handled and response circuit transmits and the computational analysis; the former storage is used for calibration, delivers to LED after latter's conversion process and show.Second kind is that signal detection and calibration circuit is calibrated, association's data processing and response circuit control reference signal generating circuit output series standard magnitude of voltage, by the signal detection and calibration circuit image data, compare with preset value simultaneously, correction signal detects the systematic error of calibration circuit.The third is the calibration current signal deteching circuit, association's data processing and response circuit control signal detect the signal of calibration circuit and select the path, by master data handle and response circuit respectively by signal detection and calibration circuit and current signal detection circuit synchronous acquisition with three-phase current signal, under the normal operating conditions of not disturbing master data processing and response circuit by current signal detection circuit collection three-phase current signal, is benchmark by association's data processing and response circuit with the data by the signal detection and calibration circuit collection, the systematic error of correction current signal testing circuit.The 4th kind is the verification threephase current transformer, association data processing and response circuit control signal detect the calibration circuit threephase current transformer (TA1 that samples simultaneously, TA2, the signal of signal TA3) and zero sequence current mutual inductor (TAN), calculate three-phase current instantaneous value sum, compare with same zero-sequence current value constantly, equate then to illustrate that as both threephase current transformer and zero sequence current mutual inductor state are normal, reliable operation, otherwise then explanation wherein has at least a state undesired, it is unreliable to work, by association's data processing and response circuit display alarm, reminding user to replace.Association's data processing and response circuit come the calibration current testing circuit by signal detection and calibration circuit, and in the process of verification operation of current transformers state, do not influence master data processing and response circuit and normally gather current signal work, thereby realize on-line testing and calibration function by current signal detection circuit.