CN101393767A

CN101393767A - Memory device with sense amplifier

Info

Publication number: CN101393767A
Application number: CNA2007101529192A
Authority: CN
Inventors: 李文杰; 陈景文; 方宏基; 郑智元; 吴忠政
Original assignee: MemoCom Corp
Current assignee: MemoCom Corp
Priority date: 2007-09-21
Filing date: 2007-09-21
Publication date: 2009-03-25

Abstract

The invention provides a storage device which comprises a first storage unit and a second storage unit. The first memory cell includes a first transistor coupled to a bit line and the second memory cell includes a second transistor coupled to a complementary bit line. The first transistor includes a first gate terminal coupled to a first word line. The second transistor includes a second gate terminal coupled to a second word line. The first transistor and the second transistor are controlled by the first word line and the second word line, respectively. A first sense amplifier having an asymmetric configuration is coupled to the bit line and the complementary bit line and is capable of sensing a state of at least one of the bit line and the complementary bit line.

Description

The memory storage of band detecting amplifier

Related application

The application's case and the 60/846th, No. 560 U.S. Provisional Patent Application cases are relevant and advocate right of priority based on this U.S. Provisional Patent Application case, this U.S. Provisional Patent Application case is to file an application on September 21st, 2006, and it is incorporated herein with way of reference in full.

Technical field

The application relates generally to the detecting amplifier that is associated with memory storage.

Background technology

Detecting amplifier has been widely used in the various storage arrays.For example, each storage unit in the storage array can have an output that is used to indicate the state of this unit.With the random access storage device is example, and each storage unit can be connected to its output one of following two bit lines: BL (bit line) or BLB (paratope line).Carrying out this two bit lines can being precharged to a reference voltage before storer reads operation, it is usually between high voltage (for example VDD) and ground voltage.During reading operation, a bit line or paratope line are connected to a storage unit, be stored in the voltage level that electric charge in the storage unit can change bit line.After reading operation, bit line can have two kinds of different voltage levels with paratope line.

Detecting amplifier can be used for reading the result of a reading operation.For example, a detecting amplifier can be connected to described two bit lines, to detect its voltage difference and to amplify this voltage difference with the sensing element state, for example logical zero or logical one.For example, a detecting amplifier can have the phase inverter of a pair of symmetry, and this has the identical phase inverter of two cross-coupled to phase inverter.In other words, each phase inverter in the detecting amplifier has identical characteristic and both had been used for BL and detects and also to be used for BLB and to detect.For the design of this kind detecting amplifier, reference voltage is set at VDD/2 usually.

The example of Fig. 1 (a) graphic extension one prior art memory storage and testing circuit together.Referring to Fig. 1 (a), this memory storage has two

storage unit

110 and 115, pre-charge circuit 140, reaches detecting amplifier 150.Can be by enabling word line (WL) 120 selectively storage unit 110 be write and can read it by bit line (BL) 130.Similarly, can be by enabling word line (WL) 125 selectively storage unit 115 be write and can read it by paratope line (BLB) 135.

In a reading operation, a pre-charge circuit 140 will be enabled by its control signal PRCH145, and pre-charge circuit 140 can the two be precharged to a reference voltage VPR with BL130 and BLB135 thereby make, as shown in Fig. 1 (b).Voltage VPR is VDD/2, i.e. half of VDD (positive voltage level that it can be provided for the common source terminal by memory storage).After pre-charge process 176, can apply a voltage (for example VDD) to word line 120, to read corresponding storage unit.In reading cells 110 processes, it can store a charge level of representing logical one or logical zero, and this can correspond respectively to a voltage level or a ground voltage level that equals or approach VDD.Decide on stored charge, in a single day bit line 130 is coupled to storage unit 110, just can be during the electric charge shown in Fig. 1 (b) is shared process 177 charges to a voltage that raises or is discharged to the voltage of a step-down from its initial pre-charge state VDD/2.

After read operation, enable detecting amplifier 150 that line SNR 175 obtains enabling by one and will amplify signal from described two bit lines BL 130 and BLB 135.Therefore, as beginning testing process 178 as shown in Fig. 1 (b).As shown in Fig. 1 (c) and Fig. 1 (d), the example of graphic extension one detecting amplifier.Detecting amplifier 150 can comprise the phase inverter of two same types and characteristic, and this can provide a symmetry configuration.Correspondingly, the trip point 188 of the phase inverter 180 shown in Fig. 1 (c) and Fig. 1 (d) is identical with the trip point 190 of phase inverter 182, as shown in Fig. 1 (e).

Summary of the invention

In various embodiments of the present invention, a kind of memory storage comprises at least one detecting amplifier that is asymmetric configuration.

In one embodiment, a kind of memory storage comprises one first storage unit and one second storage unit, wherein this first storage unit comprises a first transistor that is coupled to a bit line, and this second storage unit comprises a transistor seconds that is coupled to a paratope line.The gate terminal of this first transistor and this transistor seconds can be coupled to and be controlled by one first word line and one second word line respectively.One first detecting amplifier can be coupled to this bit line and this paratope line, and has an asymmetric configuration.Detecting amplifier 302 can be disposed, to detect one of them state of this bit line and this paratope line.

Description of drawings

This paper only is exemplary of the invention at the embodiment shown in accompanying drawing graphic, but not is limited.

One example of the testing circuit that a memory storage and accompanies in Fig. 1 (a) graphic extension prior art;

Fig. 1 (b) is an exemplary waveform, is used for the operation of graphic extension prior art one memory storage;

An example of a detecting amplifier in Fig. 1 (c) and 1 (d) graphic extension prior art;

Two characteristics in Fig. 1 (e) graphic extension prior art with phase inverter of similar configuration;

Fig. 2 graphic extension is a calcspar of storage array device according to an embodiment of the invention;

Fig. 3 graphic extension is an exemplary memory storage according to an embodiment of the invention;

One calcspar of a kind of according to an embodiment of the invention detecting amplifier configuration of Fig. 4 (a) graphic extension;

Fig. 4 (b) graphic extension is an example of the transfer characteristics of two phase inverters in the detecting amplifier according to an embodiment of the invention;

Fig. 4 (c) graphic extension is an example of the transfer characteristics of two phase inverters in another detecting amplifier according to an embodiment of the invention;

Fig. 5 (a) graphic extension is a calcspar of another configuration of detecting amplifier according to an embodiment of the invention;

Fig. 5 (b) graphic extension is an example of the transfer characteristics of two phase inverters in the detecting amplifier according to an embodiment of the invention;

Fig. 5 (c) graphic extension is an example of the transfer characteristics of two phase inverters in another detecting amplifier according to an embodiment of the invention;

Fig. 6 graphic extension one exemplary waveform is used for the graphic extension operation of detecting amplifier according to an embodiment of the invention;

Another exemplary waveform of Fig. 7 graphic extension is used for the graphic extension operation of detecting amplifier according to an embodiment of the invention;

Fig. 8 graphic extension is according to one embodiment of the invention, the exemplary waveform of BL and BLB when storage unit 340 storages one logical zero;

Fig. 9 graphic extension is according to one embodiment of the invention, the exemplary waveform of BL and BLB when storage unit 340 storages one logical one;

Figure 10 graphic extension is according to one embodiment of the invention, and one provides the example of an asymmetric detecting amplifier by sharing some transistor;

Figure 11 graphic extension is according to one embodiment of the invention, and another provides the example of an asymmetric detecting amplifier by sharing some transistor; And

Figure 12 graphic extension is according to one embodiment of the invention, the example that enabling of detecting amplifier controlled.

Embodiment

Exemplary embodiment of the present invention can comprise that one is communicatively coupled to the storage array of detecting amplifier, and these detecting amplifiers comprise the unsymmetric circuit that is coupled to bit line and paratope line.Fig. 2 is a calcspar, an exemplary embodiment of its graphic extension one storage array device 200.Storage array device 200 comprises a row decoder 202 and a column decoder 204 that is coupled to a storage array 206.In this embodiment, each bit line 208 is coupled to a detecting amplifier 210 by column decoder 204.In one embodiment, detecting amplifier 210 can comprise unsymmetric circuit, and this unsymmetric circuit is configured to detect the variation of the voltage (corresponding to " 1 " of being stored or " 0 ") that is associated with the storage unit (not shown) of storage array 206.This and other exemplary embodiment can comprise can accurately read the ability that before is considered to the storage unit that can not read, thereby improves the yield of available memory effectively.

In each embodiment, this unsymmetric circuit can use the various semiconductor devices with different qualities to do in fact, for example uses to have the transistor of different channel width (W) to the ratio (for example (W/L)) of channel length (L).Exemplary embodiment of the present invention can be carried out precharge by pairs of bit line and paratope line makes the reference voltage of memory storage have dirigibility, and/or the reference voltage that is used in the voltage level state that detects bit line or paratope line has dirigibility.In certain embodiments, can produce the power consumption that bit-line pre-charge voltage reduces memory storage because of not needing an independent power supply or a pre-charge voltage generation circuit.In certain embodiments, can the needed electric charge of detection of stored location mode because of changing that pre-charge voltage is reduced to.Correspondingly, can prolong data hold time and can reduce memory data is frequently refreshed the power that is consumed.

Fig. 3 graphic extension one can be contained in an exemplary embodiment of the memory storage 300 in the storage array device 200.In this embodiment, memory storage 300 comprises a storage unit 340, a storage unit 345, a pre-charge circuit 360, reaches a detecting amplifier circuit 305.Can be by enabling word line (WL) 350 selectively storage unit 340 be write and can read it by bit line (BL) 330.Similarly, can be by enabling word line (WL) 355 selectively storage unit 345 be write and can read it by paratope line (BLB) 335.Pre-charge circuit 360 can be used for by the PRCH terminal being controlled the precharge to BL and BLB, and these two lines are precharged to precharge reference voltage VPR.

In an exemplary embodiment, detecting amplifier circuit 305 comprises a detecting amplifier 302 and a detecting amplifier 304.For amplifying from for the signal of BL and BLB, these two detecting

amplifiers

302 and 304 can be asymmetric.In one embodiment, detecting amplifier 302 can comprise the phase inverter 310 (INV1) and 315 (INV2) of two cross-coupled, and detecting amplifier 304 can comprise the phase inverter 320 (INV3) and 325 (INV4) of two cross-coupled in addition.In another embodiment, a phase inverter can comprise a PMOS (P type) transistor and a NMOS (N type) transistor, and this PMOS transistor AND gate nmos pass transistor is coupled to its gate terminal together.One or more asymmetric detecting amplifiers are used to provide two or more to have the phase inverter of different qualities (for example different transfer characteristics functions or different electrical characteristics).In one embodiment, phase inverter 310 can have transfer (or amplification) characteristic function that is different from phase inverter 315, and phase inverter 320 can have transfer (or amplification) characteristic function that is different from phase inverter 325.For example, phase inverter to 310 with 315 and/or phase inverter may be inequality to the different channel width of the ratio of channel length or nmos pass transistor to 320 and 325 trip point to the ratio of channel length because of the transistorized different channel width of PMOS.In another embodiment, the PMOS transistor of phase inverter 310 has the transistorized electrical characteristics of the PMOS that is different from phase inverter 315.For example, the transistorized starting voltage of the PMOS of phase inverter 310 can be greater than the transistorized starting voltage of the PMOS of phase inverter 315, and this makes the logic starting voltage of phase inverter 310 bigger.Therefore, in each embodiment, can obtain the asymmetric configuration of detecting amplifier by the entity size that changes each phase inverter respectively.

Detecting amplifier 302 can be controlled by enables line SNR 312, and detecting amplifier 304 can be controlled by and enables line SNL 322.Detecting amplifier circuit 305 can be coupled to pair of bit lines (for example a BL330 and a BLB 335), and can detect the signal on BL 330 and the BLB 335.In this example, storage unit 340 and storage unit 345 are coupled to BL 330 and BLB 335 respectively, and are controlled by a WL350 and a WL 355 respectively.BL 330 and BLB 335 are coupled to

pre-charge circuit

360, and 360 of pre-charge circuits are controlled by pre-charge enable line PRCH and are coupled to precharge reference voltage VPR.

In one example, the detecting amplifier 302 that is controlled by SNR 312 can be used for 330 reading cells 340 from BL, and the detecting amplifier 304 that is controlled by SNL 322 can be used for 335 reading cells 345 from BLB.In some instances, can enable line SNR 312 with these two respectively enables with SNL 322.Yet, also can simultaneously SNR 312 and SNL 322 be enabled, with while reading cells 340 and storage unit 345.Under this kind operational mode, storage unit 340 and storage unit 345 can be stored complementary value.

In another exemplary embodiment, detecting amplifier circuit 305 can comprise one of them detecting amplifier: detecting amplifier 302 or detecting amplifier 304.Detecting amplifier circuit 305 can thereby detect one of them state of this bit line and this paratope line at every turn.For example, as shown in FIG. 3, detecting amplifier circuit 305 comprises a detecting amplifier 302, and detecting amplifier 302 has unsymmetric circuit, and promptly the transfer characteristics function of phase inverter 310 is different from phase inverter 315.Storage unit 340 and storage unit 345 are coupled to bit line (BL) 330 and paratope line (BLB) 335 respectively.Transfer characteristics function on phase inverter 310 and phase inverter 315 is decided, and detecting amplifier 302 can pass through bit line (BL) 330 reading cells 340, perhaps by paratope line (BLB) 335 reading cells 345.For example, if the trip point of phase inverter 310 is lower than the trip point of phase inverter 315, detecting amplifier 302 accessible storage unit 340 then.Yet, if the trip point of phase inverter 310 is higher than the trip point of phase inverter 315, detecting amplifier 302 accessible storage unit 345.

Can use various configurations that one dissymmetrical structure is provided to detecting amplifier circuit 305.The logical block diagram of an embodiment of Fig. 4 (a) graphic extension detecting amplifier 302,304.Detecting amplifier 302 comprises a phase inverter 310 and a phase inverter 315 of mutual cross-coupled, and detecting amplifier 304 can have a phase inverter 320 and a phase inverter 325 of mutual cross-coupled.

One example of the transfer characteristics function of Fig. 4 (b) graphic extension phase inverter 310 and phase inverter 315.Referring to Fig. 4 (b), the left side curve is corresponding to phase inverter 310, and right side graph is corresponding to phase inverter 315.In this example, the trip point of phase inverter 310 (V saltus step 1) is lower than the trip point (V saltus step 2) of phase inverter 315.In other words, phase inverter 310 more " can drive " than phase inverter 315, and this means that phase inverter 310 comparable phase inverters 315 drive bigger load.

One example of the transfer characteristics function of Fig. 4 (c) graphic extension phase inverter 320 and phase inverter 325.Referring to Fig. 4 (c), the left side curve is corresponding to phase inverter 325, and right side graph is corresponding to phase inverter 320.In this example, the trip point of phase inverter 325 (V saltus step 4) is lower than the trip point (V saltus step 3) of phase inverter 320.In other words, phase inverter 325 more " can drive " than phase inverter 320, and this means that phase inverter 325 comparable phase inverters 320 drive bigger load.

Second of detecting amplifier circuit 305 is configured in conceptive first configuration that is similar among Fig. 3, but the asymmetry of each is all put upside down in these two detecting amplifiers, as shown in Fig. 5 (a)-(c).One exemplary calcspar of this kind of Fig. 5 (a) graphic extension configuration.Referring to Fig. 5 (a), detecting amplifier 302 can have a phase inverter 310a and a phase inverter 315a of mutual cross-coupled, and detecting amplifier 304 can have a phase inverter 320a and a phase inverter 325a of mutual cross-coupled.One example of the transfer characteristics function of Fig. 5 (b) graphic extension phase inverter 310a and phase inverter 315a.Referring to Fig. 5 (b), the left side curve is corresponding to phase inverter 315a, and right side graph is corresponding to phase inverter 310a.In this example, the trip point of phase inverter 315a (V saltus step 2) is lower than the trip point (V saltus step 1) of phase inverter 310a.In other words, phase inverter 315a more " can drive " than phase inverter 310a.

One example of the transfer characteristics function of Fig. 5 (c) graphic extension phase inverter 320a and phase inverter 325a.Referring to Fig. 5 (c), the left side curve is corresponding to phase inverter 320a, and right side graph is corresponding to phase inverter 325a.In this example, the trip point of phase inverter 320a (V saltus step 3) is lower than the trip point (V saltus step 4) of phase inverter 325a.In other words, phase inverter 320a more " can drive " than phase inverter 325a.

Decide on memory circuitry design and reference voltage level, can use the various configurations of one or more detecting amplifiers.In an exemplary embodiment, can adjust the configuration of detecting amplifier and the transfer characteristics function of phase inverter according to the various Considerations of the level that comprises VPR.In many examples, can use one or more detecting amplifiers to realize the dirigibility of the level of VPR with asymmetrical design.In some instances, VPR can depart from VDD/2 or designed precharge reference voltage under various conditions, is beneficial to the function that design or characteristic according to the detecting amplifier circuit realize circuit.For example, can adjust VPR according to the characteristic of detecting amplifier because of the variation of manufacturing process, material or service condition.In some other exemplary embodiment, can be according to designing and/or adjust detecting amplifier or other characteristics for the performance of adjusting memory storage or the VPR level that operation characteristic provides.For example, if VPR is or near VDD, then according to an example, can design or adjust detecting amplifier or its characteristic, to change the voltage level detection characteristic, shown in the transfer characteristics function among reference Fig. 4 (b), 4 (c), 5 (b) and 5 (c).

In an exemplary embodiment, can use a V increase-V to reduce relatively to select a configuration.For example, when the voltage level of logical one was represented in storage unit 340 storages one, it can produce a little voltage increase V with respect to VPR and increase on BL.Similarly, when the voltage level of logical zero was represented in storage unit 340 storages one, it can produce a little voltage decrease V with respect to VPR and reduce on BL.If V increases and reduces less than V, then the detecting amplifier of memory storage can use one to be same as or to be similar to the configuration shown in Fig. 4 (a)-4 (c).And if the V increase reduces greater than V, then the detecting amplifier of memory storage can use one to be same as or to be similar to the configuration shown in Fig. 5 (a)-5 (c).

Hereinafter with the operation of graphic extension according to detecting amplifier example of the present invention.In one example, VPR can be set at the level that is higher than VDD/2, for example certain value between VDD/2 and VDD.As an illustrative example, when V increases when reducing less than V, storage unit 340 can use one to be similar to the detecting amplifier shown in addressing with reference to Fig. 4 (a)-4 (c) and to store a voltage level of representing logical one.Fig. 6 graphic extension one exemplary waveform is used for the operation of graphic extension detecting amplifier.Referring to Fig. 6, the reading operation of memory storage can have three phases: precharge (equalization), electric charge is shared, and detection-phase.In one example, can use one between ground level and VDD level and be higher than the level of VDD/2.During pre-charging stage, the two level of BL and BLB all is precharged to VPR.During electric charge was shared, word line was activated, and shared the electric charge (influenced by a voltage level) that is stored in the corresponding stored unit to allow BL and/or BLB.After electric charge was shared, the voltage level on the BL can become a little more than VPR, in other words, produce a little voltage increase V and increase, the voltage on the BLB then near or be in the VPR level.

In one embodiment, for amplifying the poor of BL and BLB level, can use a more drivable phase inverter to BL, the phase inverter 310 shown in Fig. 4 (a) for example is to be pushed into the voltage level on the BLB downwards one lower level.Then, the voltage level of the reduction on the BLB input end can make phase inverter 315 that the voltage level on the BL is drawn on VDD.Correspondingly, when the approaching end of detection-phase, can read a logical one state from BL.In this embodiment, this asymmetric detecting amplifier can provide a kind of effective solution that is used for distinguishing the voltage difference of BL and BLB, and makes the precharge reference voltage have level flexibly.

Fig. 7 graphic extension one exemplary waveform is to be used for the operation of graphic extension detecting amplifier.In this embodiment, the voltage level of logical zero is represented in storage unit 340 storages one.Referring to Fig. 7, after electric charge was shared, the voltage level of BL can become a little less than VPR, in other words, produced a little voltage decrease V and reduced, and the voltage level of BLB then can be in or near the VPR level.Therefore, the input voltage that grid is coupled to the phase inverter 310 of BLB is lower than the phase inverter 315 that grid is coupled to BLB.Use the asymmetric configuration of above illustrated detecting amplifier 302, phase inverter 310 more " can drive " than phase inverter 315.Yet, by trip point is designed, phase inverter 315 will be not can drop-down BLB voltage level.In some instances, the asymmetric configuration of this kind can be V saltus step 1 and V saltus step 2 provides scope more flexibly.For example, V saltus step 1 and V saltus step 2 the two can all be higher than and after electric charge is shared, take a sample the BL voltage level that obtains but be lower than VPR360.In this example, phase inverter 315 can promote the BL voltage level towards ground level.And by with importing as it than low level on the BL, phase inverter 310 can draw the BLB voltage level on VDD.Correspondingly, when the approaching end of detection-phase, can read a logical zero state from BL.

When the V increase reduced greater than V, detecting amplifier also can have one and be similar to or be same as the configuration shown in Fig. 5 (a)-5 (c).Fig. 8 graphic extension exemplary BL and BLB waveform of when reducing (produce V) when storage unit 340 storage one logical zero.The exemplary BL and the BLB waveform of (when producing the V increase) when Fig. 9 graphic extension is stored a logical one when storage unit 340.The detecting amplifier operation of storage unit that although above example is graphic extension when working as VPR and being higher than VDD/2, yet when VPR is lower than VDD/2, can explain similarly that also the detecting amplifier of storage unit moves.

Figure 10 graphic extension one provides the example of an asymmetric detecting amplifier by sharing some transistor.Referring to Figure 10, a PMOS transistor 1005 and a PMOS transistor 1010 can be shared by two groups of asymmetric detecting amplifiers.In one example, a PMOS transistor 1005 and a nmos pass transistor 1015 can form one first phase inverter, and a PMOS transistor 1010 and a nmos pass transistor 1020 can form one second phase inverter.First and second phase inverter of these two cross-coupled can form one first detecting amplifier.In addition, a PMOS transistor 1005 and a nmos pass transistor 1025 can form one the 3rd phase inverter, and a PMOS transistor 1010 and a nmos pass transistor 1030 can form one the 4th phase inverter.The the 3rd and the 4th phase inverter of these two cross-coupled can form one second detecting amplifier.In some instances, the shared transistor arrangement of this kind can reduce the required number of transistors of detecting amplifier circuit, and can reduce occupied chip space of a memory storage or area.

Can be with wherein one group or these two groups of detecting amplifiers all are designed to have a dissymmetrical structure.For example, nmos pass transistor 1015 can have different characteristics with 1020, for example different transfer characteristics function (for example, the different trip points of phase inverter) or different electrical characteristics (for example different starting voltages of phase inverter).In one example, can with the drive strength (being the ratio of channel width) of transistor 1015 to channel length (W/L) 1015 and the drive strength (W/L) 1020 of transistor 1020 be designed to have a certain physical relation.For example, (W/L) ratio of 1015/ (W/L) 1020 can be in 0.25 to 4 even 0.1 to 10 scope, and this decides on for example various factorss such as component design, transistor threshold, device application.In one example, (W/L) ratio of 1015/ (W/L) 1020 can be 2/3.Similarly, nmos pass transistor 1025 can have different characteristics with 1030, for example different transfer characteristics functions.Drive strength (W/L) 1025 of transistor 1025 and the drive strength (W/L) 1030 of transistor 1030 can be designed to have a certain physical relation.In an exemplary embodiment, (W/L) ratio of 1025/ (W/L) 1030 can be in 0.25 to 4 even 0.1 to 10 scope, and this decides on for example various factorss such as component design, transistor threshold, device application.In one example, (W/L) ratio of 1025/ (W/L) 1030 can be 3/2.

In addition, in one example, can be with (W/L) 1025/ when of (W/L) 1015/ (W/L) 1020

(W/L) 1030 ratio is designed to have a certain physical relation or approximate identical.Particularly, the drive strength of NMOS 1015 can equal the drive strength of NMOS 1030 to NMOS to the ratio of the drive strength of NMOS 1020

The ratio of 1025 drive strength.For example, when the ratio of (W/L) 1015/ (W/L) 1020 was 2/3, (W/L) ratio of 1025/ (W/L) 1030 can be 3/2.Yet, above shown in the ratio of various parameters be exemplary, and also can use the combination of other ratios and various ratios according to for example various factorss such as component design, transistor threshold, device application.In addition, each transistor threshold and each W/L ratio can be designed independently of each other or in combination, to obtain similar result.In other words, can change each transistorized W/L ratio, with some characteristic of formation phase inverter and the asymmetry or the symmetry of each detecting amplifier.

Figure 11 graphic extension another use some shared transistor that the example of one asymmetric detecting amplifier is provided.Referring to Figure 11,

nmos pass transistor

1115 and 1120 can be shared by two groups of asymmetric detecting amplifiers.In one example, a nmos pass transistor 1115 and a PMOS transistor 1105 can form one first phase inverter, and a nmos pass transistor 1120 and a PMOS transistor 1110 can form one second phase inverter.First and second phase inverter of these two cross-coupled can form one first detecting amplifier.In addition, a nmos pass transistor 1115 and a PMOS transistor 1125 can form one the 3rd phase inverter, and a nmos pass transistor 1120 and a PMOS transistor 1130 can form one the 4th phase inverter.The the 3rd and the 4th phase inverter of these two cross-coupled can form one second detecting amplifier.In some instances, the shared transistor arrangement of this kind can reduce the required number of transistors of detecting amplifier circuit, and can reduce occupied chip space of a memory storage or area.For providing different characteristics to these two groups of detecting amplifiers, for example different transfer characteristics functions, first group of

PMOS transistor

1105 and 1110 can have the configuration that is different from second group of

PMOS transistor

1125 and 1130.

Can be with wherein one group or these two groups of detecting amplifiers all are designed to have a dissymmetrical structure.For example, PMOS transistor 1105 can have different characteristics with 1110, for example different transfer characteristics function (for example, the different trip points of phase inverter) or different electrical characteristics (for example different starting voltages of phase inverter).In one example, can be with drive strength (W/L) 1105 of transistor 1105 and the drive strength of transistor 1110

(W/L) 1110 be designed to have a certain physical relation.For example, (W/L) 1105/ (W/L) 1110 it

Ratio can be in 0.25 to 4 even 0.1 to 10 scope, and this looks for example component design, transistor threshold

Value, device various factors such as application and decide.In one example, (W/L) ratio of 1105/ (W/L) 1110

Can be 2/3.Similarly, PMOS transistor 1125 can have different characteristics with 1130, and is for example different

The transfer characteristics function.In an exemplary embodiment, drive strength (W/L) 1125 of transistor 1125 and the drive strength (W/L) 1130 of transistor 1130 can be designed to have a certain physical relation.For example, (W/L) ratio of 1125/ (W/L) 1130 can be in 0.25 to 4 even 0.1 to 11 scope, and this decides on for example various factorss such as component design, transistor threshold, device application.In an exemplary embodiment,

(W/L) ratio of 1125/ (W/L) 1130 can be 3/2.

In addition, in an exemplary embodiment, the ratio of (W/L) 1125/ when (W/L) 1130 of (W/L) 1105/ (W/L) 1110 can be designed to have a certain physical relation or approximate identical.Yet, above shown in the ratio of various parameters be exemplary, and also can use the combination of other ratios and various ratios according to for example various factorss such as component design, transistor threshold, device application.Correspondingly, each transistor threshold and each W/L ratio can be designed independently of each other or in combination, to obtain similar result.In other words, can change each transistorized W/L ratio, with some characteristic of formation phase inverter and the asymmetry or the symmetry of each detecting amplifier.

The a pair of detecting amplifier of Figure 12 graphic extension enable the example of controlling.Referring to Figure 12, SNR and SNL can be subjected to a control module 1210 control, to control the activation of one of them or these two detecting amplifiers by the whole bag of tricks.In an exemplary embodiment, can use a fuse block as a control module.During powering up or behind fuse failure, can enable SNR 312 and SNL 322 or one of them.In another exemplary embodiment, can use the activation of a tinsel control detection amplifier.In other exemplary embodiment, can use an automatic probe unit automatically to survey which detecting amplifier needs to activate.

According to one embodiment of the invention, these two asymmetric detecting amplifiers can use two independent lines (for example SNR and the SNL shown in Fig. 3,10 or 11) of enabling to come independent operating.In some instances, only these two of enabling in the line are put height at every turn.In other examples, can be configured storer, make with reference to described storage unit 340 of Fig. 3 and storage unit 345 to comprise complementary all the time.In one example, then can read these two unit simultaneously, and SNR and SNL can be put height simultaneously.In this example, these two unit can be coupled to two independent word lines, reach two detecting amplifiers, and one of them or these two detecting amplifiers can be asymmetric and can activate simultaneously.And the characteristic of these two detecting amplifiers can influence the combined effect of these two detecting amplifiers to BL and BLB signal.

According to explanation above as can be seen, the present invention relates to a kind of have one can asymmetric configuration or the memory storage of the detecting amplifier of asymmetric operation.Be understood by those skilled in the art that can make change to each embodiment mentioned above, this does not deviate from broad sense inventive concept of the present invention.Therefore, should be appreciated that the present invention is not limited only to the specific embodiment that disclosed, and is intended to various modification are covered by in the spirit of the present invention and scope that claims defined by enclosing.

Claims

1. A storage device comprising:

A first memory cell and a second memory cell, wherein the first memory cell includes a first transistor coupled to a bit line, and the second memory cell includes a second transistor coupled to a complementary bit line transistor;

A first word line and a second word line, wherein the first transistor and the second transistor include a first transistor coupled to and controlled by the first word line and the second word line, respectively. a gate terminal and a second gate terminal; and

a first sense amplifier coupled to the bit line and the complementary bit line, wherein the first sense amplifier has an asymmetric configuration and is configured to sense at least one of the bit line and the complementary bit line One of a state.

2. The memory device according to claim 1, wherein the first sense amplifier comprises a first inverter and a second inverter, the first inverter and the second inverter is cross-coupled, the input of the first inverter is coupled to the bit line and the output of the first inverter is coupled to the complementary bit line, and the second inverter The input of the second inverter is coupled to the complementary bit line and the output of the second inverter is coupled to the bit line.

3. The storage device according to claim 2, wherein the first inverter and the second inverter comprise a P-type transistor and an N-type transistor respectively, and according to the first inverter A different channel width to channel length ratio of one of the P-type or N-type transistors associated with the second inverter and the same P-type or N-type transistor associated with the second inverter The first inverter and the second inverter are configured to have different transfer characteristic functions.

4. The memory device according to claim 3, wherein the ratio of the channel width to the channel length of one of the P-type or N-type transistors associated with the first inverter is relatively A ratio of the channel width to channel length ratio of the same P-type or N-type transistor associated with the second inverter is between 0.1 and 10.

5. The memory device of claim 3, wherein the threshold voltage of one of the P-type or the N-type transistor associated with the first inverter is different from that of the second inverter. The threshold voltage of the same P-type or N-type transistor associated with the phase device.

6. The memory device of claim 1 , further comprising a second sense amplifier coupled to the bit line and the complementary bit line, the second sense amplifier configured to sense the bit line A state of at least one of the line and the complementary bit line.

7. The memory device of claim 6, wherein the second sense amplifier has an asymmetric configuration or a symmetrical configuration.

8. The memory device according to claim 7, wherein the second sense amplifier comprises a third inverter and a fourth inverter, the third inverter and the fourth inverter is cross-coupled, the input of the third inverter is coupled to the bit line and the output of the third inverter is coupled to the complementary bit line, and the fourth inverter The input of the fourth inverter is coupled to the complementary bit line and the output of the fourth inverter is coupled to the bit line.

9. The storage device according to claim 8, wherein the third inverter and the fourth inverter comprise a P-type transistor and an N-type transistor respectively, and according to the third inverter A different channel width to channel length ratio of one of the P-type or N-type transistors associated with the fourth inverter and the same P-type or N-type transistor associated with the fourth inverter The third inverter and the fourth inverter are configured to have different transfer characteristic functions.

10. The storage device according to claim 9, wherein the first inverter comprises a first P-type transistor and a first N-type transistor, and the third inverter comprises a second P-type transistor. transistor and the first N-type transistor, the second inverter includes a third P-type transistor and a second N-type transistor, and the fourth inverter includes a fourth P-type transistor and the first Two N-type transistors.

11. The storage device according to claim 9, wherein the first inverter comprises a first P-type transistor and a first N-type transistor, and the third inverter comprises the first P-type transistor. type transistor and a second N-type transistor, the second inverter includes a second P-type transistor and a third N-type transistor, and the fourth inverter includes the second P-type transistor and a first Four N-type transistors.

12. The memory device according to claim 9, wherein the ratio of the channel width to the channel length of one of the P-type or N-type transistors associated with the third inverter is relatively A ratio of the channel width to channel length ratio of the same P-type or N-type transistor associated with the fourth inverter is between 0.1 and 10.

13. The memory device of claim 9, wherein the second sense amplifier is symmetrical, based on the sum of one of the P-type or N-type transistors associated with the third inverter and The same P-type or N-type transistor associated with the fourth inverter has the same ratio of channel width to channel length, and the third inverter and the fourth inverter have the same The transfer characteristic function of .

14. The memory device of claim 6, wherein the first sense amplifier and the second sense amplifier are activated simultaneously to detect the first memory cell and the second memory cell respectively.

15. The memory device of claim 6, further comprising a control unit coupled to the first amplifier and the second sense amplifier, the control unit configured to control the first sense amplifier amplifier and the activation of one or both of the second sense amplifier.

16. A storage array device comprising:

a memory cell array comprising memory cells coupled to a first decoder and a second decoder, each memory cell comprising a bit line and a complementary bit line; and

a sense amplifier circuit coupled to said first decoder and said bit line and said complementary bit line, said sense amplifier circuit comprising a first sense amplifier having an asymmetric configuration for detecting a A state of at least one of the bit line and the complementary bit line of the memory cell.

17. The memory array device as claimed in claim 16, wherein the sense amplifier circuit further comprises a second sense amplifier coupled to the bit line and the complementary bit line, the second sense amplifier via configured to detect a state of at least one of the bit line and the complementary bit line.

18. The memory array device as claimed in claim 16, wherein said first sense amplifier comprises a first inverter and a second inverter, said first inverter and said second inverter Inverters are cross-coupled, each of the first inverter and the second inverter includes a P-type transistor and an N-type transistor, and according to the a different channel width to channel length ratio of one of the P-type or N-type transistors and the same P-type or N-type transistor associated with the second inverter The phaser and the second inverter are configured to have different transfer characteristic functions.

19. The memory device of claim 18, wherein the threshold voltage of one of the P-type or the N-type transistor associated with the first inverter is different from that of the second inverter. The threshold voltage of the same P-type or N-type transistor associated with the phase device.

20. The memory array device according to claim 17, wherein said second sense amplifier comprises a third inverter and a fourth inverter, said third inverter and said fourth inverter Phases are cross-coupled, each of the third inverter and the fourth inverter includes a P-type transistor and an N-type transistor, and according to the One of the P-type or N-type transistors and a channel width to channel length ratio of the same P-type or N-type transistor associated with the fourth inverter is the third inverter The fourth inverter is configured to have the same or different transfer characteristic function.

21. The memory device according to claim 20, wherein the first inverter comprises a first P-type transistor and a first N-type transistor, and the third inverter comprises a second P-type transistor transistor and the first N-type transistor, the second inverter includes a third P-type transistor and a second N-type transistor, and the fourth inverter includes a fourth P-type transistor and the first Two N-type transistors.

22. The memory device according to claim 20, wherein the first inverter comprises a first P-type transistor and a first N-type transistor, and the third inverter comprises the first P-type transistor. type transistor and a second N-type transistor, the second inverter includes a second P-type transistor and a third N-type transistor, and the fourth inverter includes the second P-type transistor and a first Four N-type transistors.

23. The memory array device of claim 17, wherein the first sense amplifier and the second sense amplifier are configured to simultaneously activate different memory cells.

24. The memory device of claim 17, further comprising a control unit coupled to the first sense amplifier and the second sense amplifier, the control unit configured to control the first sense amplifier and the second sense amplifier activation of one or both of the second sense amplifiers.