CN101377826B - Radio frequency and/or radio frequency identification electronic filemark/ apparatus with integration substrate, and manufacturing and using method thereof - Google Patents

Abstract

The invention discloses a MOS radio frequency monitoring and/or identification electronic tag and a manufacturing method thereof. Electronic tags generally include a substrate, an antenna and/or an inductor on the substrate, and an integrated circuit formed at a location on the substrate in addition to the antenna and/or the inductor. The integrated circuit has a bottommost layer in physical contact with the surface of the substrate. The manufacturing method generally includes the steps of: (1) forming a lowermost layer of an integrated circuit on a substrate; (2) forming a continuous layer of the integrated circuit on the lowermost layer of the integrated circuit; and (3) A conductive active layer is attached to the substrate.

Description

Radio frequency and/or radio frequency identification electronic tag/device with integrated substrate and method of manufacturing and using same

technical field

The present invention relates to sensors, commodity electronic anti-theft systems (electronic article surveillance, EAS), radio frequency (radio frequency, RF) and/or radio frequency identification device (RFID) electronic tags and devices, in particular to commodity electronic anti-theft systems, radio frequency and/or The structure of the radio frequency identification device and its manufacturing and/or production method. Therefore, the present invention can provide a low-cost manufacturing process for manufacturing an electronic tag for a radio frequency identification device (or an electronic anti-theft system for goods). The electronic tag includes a substrate, a radio frequency front end or a subset of a radio frequency front end, memory and logic circuits.

Background technique

Today, remotely powered electronic devices and related systems are known. For example, US Patent No. 5,099,227 to Geiszler et al. and entitled "proximity detecting apparatus" discloses a remote actuation apparatus. The remote drive device utilizes electromagnetic coupling to obtain power from a remote source, and then utilizes electromagnetic and electrostatic coupling to transmit stored data to a receiving end. The sink is usually co-located with the remote source. Such remote-actuated communication devices are known as RFID electronic tags.

Radio frequency identification device electronic tags and related systems have a variety of uses. For example, RFID electronic tags are often used in automated gate sentry applications for personal identification and protection of secured buildings or areas. These electronic tags usually take the form of access control cards. The information stored in the radio frequency identification device electronic tag is used to identify the holder of the electronic tag trying to enter the secured building or area.

Old-fashioned automated gatekeeper applications typically require persons authorized to enter a secured building to insert or swipe their identification card or electronic tag into a reader used in the system to be recognized by the identification card or electronic tag. Volume label read information. The new RFID electronic tag system uses radio frequency data transmission technology, allowing the electronic tag to be read at a short distance, thereby eliminating the need to insert or swipe the identification electronic tag through the reader.

The most distinctive feature is that the user only needs to hold the electronic tag and approach a base station or place the electronic tag near the base station. The base station is coupled to a security system for protecting the building or area. The base station transmits an excitation signal to the electronic tag to drive a circuit on the electronic tag. The circuit responds to the trigger signal, and transmits the stored information from the electronic tag to the base station. The base station receives and decodes the information. This information is then processed by the security system to determine whether the access is appropriate. Also, the identification tag can be remotely written (eg, programmed and/or deactivated) via a trigger signal. The trigger signal is appropriately modulated by a predetermined method.

Some conventional RFID electronic tags and systems mainly use electromagnetic coupling to remotely actuate the remote device. The remote device is coupled to an exciter system and a receiving system. The actuation system generates an electromagnetic trigger signal to actuate the device and cause the device to transmit a signal that may contain the stored information. The receiving system receives the signal generated by the remote device.

On a more basic level, RFID electronic tag circuits typically perform some or all of the functions listed below:

(1) RF energy is absorbed by the reader region;

(2) converting a radio frequency signal into a DC signal driving the chip;

(3) Demodulating incoming clock, timing and/or command signals in radio frequency signals sent by the reader;

(4) Generate state machine judgment and control logic to act on income or current instructions;

(5) Reading data in digital form from a memory array or other source (eg, output of a sensor). The reading of the data is equivalent to a counter or a registration machine;

(6) There is a storage component (such as a memory) for storing the identity code or other information read to the reader and/or used for security authentication. For example, EAS deactivation-type memory used to calculate the intended use of a transit ticket and/or to return information from a sensor to the reader; and

(7) Modulating the coded data, timing signals or other instructions sent back to the electronic tag antenna for transmission to the electronic tag reader.

On the other hand, the EAS electronic tag circuit may exclude some of the above-mentioned steps and/or functions. For example, the logic divider EAS drives an internal logic divider circuit (logicdivider) with basic RF energy. The logic divider circuit then modulates the antenna of the electronic tag, causing a unique sub-harmonic signal to be transmitted back to the reader (see eg UK Patent No. GB 2,017,454A). This sub-harmonic signal can be easily separated from other noise sources (such as carrier harmonics) and produce an effective EAS signal. In some instances, non-linear effects arising from semiconductor devices simplify things even further, such as disclosed in US Pat. No. 4,670,740. Non-linear effects in semiconductor devices or varactors result in sub-harmonic signals, and sub-harmonic signals can be detected by the reader without the need for relayed RF-to-DC power conversion or logic processing.

See Figure 1A. The traditional radio frequency identification device electronic tag is formed through a process. The process includes dicing a wafer 10 manufactured by a conventional wafer process into a plurality of chips 20 . Chip 20 is then placed on an antenna or inductor mount (which may include an etched, trimmed or printed metal antenna, inductor coil, or other conductive structure). Alternatively, as shown in FIG. 1B , the chip 20 can be placed on an interposer strap 40 or carrier 40, and the interposer strap 40 can then be attached to an inductor on a support film 50. /antenna 52.

This process may involve various physical bonding techniques such as adhesive or via wire bonding, anisotropic conductive epoxy bonding, ultrasonic, bump-bonding or flip-chip ( flip-chip) method to establish electrical internal connections. The bonding process typically involves the use of heat, time and/or UV light exposure. Since the chips 20 are usually made as small as possible (less than 1mm) to reduce the cost of each chip 20, the pad elements for electrical connection on the chip 20 may be quite small. This means that the placement operation of the chip 20 requires a relatively high accuracy for high-speed mechanical operations (eg, positioning within 50 microns of a predetermined position is usually required).

The process involves picking an individual chip, bonding the chip to the correct location on the antenna, inductor, carrier or carrier board, and making physical or electrical interconnections. Overall, the process can be a rather slow and expensive process.

If the process uses a relay carrier board, there will be cost and throughput advantages. First, the chip 20 is attached to a web roll of carrier 40 . This action can be done easily and sometimes in parallel. Because the carriers 40 are usually spaced in close proximity, other novel placement operations, such as fluidic self-assembly or pin bed attachment processes, can be easily accomplished. The carrier 40 generally contains electrical channels 34 , 36 . The distribution of electrical channels 34 , 36 originates from the chip 20 and is distributed elsewhere on the carrier 40 over a relatively large and/or wide area. Electrical channels 34, 36 may allow high throughput and low resolution attach operations such as crimping or conductive adhesive attachment. In contrast to a pick-and-place and/or wire-bonding process used to integrate a chip with an inductor substrate, the conductive adhesive attaches functionally similar to a conventional metal strap (strap) ).

In some instances, low resolution attachment processes for metal strips may cost $0.003 or less depending on commercially available equipment or materials (Mühlbauer TMA 600 or less). The carrier 40 is then attached to an inductor (not shown), so that an electrical connection is made at this location. This load carrying process may also be advantageous for flip-chip or bump-bonding approaches. In contrast, it may be more expensive or less advantageous to form the required stubs, bumps or other internal connection components on a larger inductor/carrier substrate by conventional methods (eg, wire bonding).

To achieve the target cost of about $0.01 per RFID electronic tag, and for single-item sales applications and other low-cost and high-volume applications, it is possible to combine (optimally integrate) a less expensive substrate, A stable and effective antenna, radio frequency front-end device, and an electronic label structure and manufacturing process of high-resolution graphical logic circuits are urgently needed.

Contents of the invention

Preferred embodiments of the present invention relate to a MOS radio frequency and/or radio frequency identification device, sensor or electronic tag with an integrated substrate and methods of making and using the same. The device generally comprises (a) a substrate; (b) an antenna and/or an inductor on a coated sheet, the antenna and/or the inductor attached or affixed to the substrate, the The antenna and/or the inductor have a first terminal and a second terminal; and (c) an integrated circuit formed directly on the substrate. The integrated circuit is electrically connected to the first terminal of the antenna through a first through hole or hole, and is electrically connected to the second terminal of the antenna through a second through hole or hole, and the integrated circuit includes: ( i) a plurality of thin film transistors and diodes, and (ii) metallization interconnecting said thin film transistors and said diodes, the integrated circuit having a bottommost layer in contact with a surface of the substrate.

The manufacturing method generally includes the following steps: (1) forming a lowest layer of an integrated circuit in physical contact with the surface of the substrate; (2) forming a continuous layer of the integrated circuit on the lowest layer of the integrated circuit On the bottom layer, the integrated circuit includes: (i) a plurality of thin film transistors and diodes, and (ii) metallization components interconnecting the thin film transistors and the diodes; and (3) an antenna and/or an inductor attached or attached to the substrate, the antenna and/or the inductor has a first terminal and a second terminal, the first terminal is electrically connected to the integrated circuit through a first via or hole, and the The second terminal is electrically connected to the integrated circuit through a second via or hole. Alternatively, the manufacturing method may comprise the steps of: (1) forming the lowest layer of the integrated circuit on the surface of the substrate; (2) forming the continuous layer of the integrated circuit on the lowest layer of the integrated circuit; and (3) forming a conductive structure from an active layer attached to the substrate.

The method of use generally includes the following steps: (i) causing (causing) or inducing (inducing) a current in the identification device, the current being sufficient to cause the identification device to radiate, reflect or modulate a detectable electromagnetic signal; (ii) detecting the detectable electromagnetic radiation; and optionally (iii) processing information conveyed by the electromagnetic radiation. Optionally, the using method may further include (iv) transporting or transmitting (transmitting) the information from the identification device (or sensor) to a reading device.

Using sheet-fed or web-fed printing technology makes it possible to manufacture RFID tags at very low cost. Printing technology has potential cost advantages because it can increase material utilization (for example, additive or semi-additive (semi-additive) processing), combine deposition and forming steps, and reduce major expenditures and equipment operating costs . In addition, the traditional high-volume printing process can be combined with a flexible substrate (eg, a plastic sheet or a metal foil plate) to increase the application of electronic labels. The material utilization rate and additive processing method make the processed substrate (or chip) have a lower cost per unit area, resulting in a low cost of the attachment process and/or the integration process between the passive device and the active circuit. Moreover, it is easier to achieve customized services for radio frequency identification devices without a mask-less manufacturing process. For example, each RFID device provides a unique identification code and/or a unique response time delay according to an inquiry from a reader.

Furthermore, if the circuit can be printed directly onto the antenna or inductor, the attachment steps and associated costs can be eliminated. This method is different from the traditional cost-saving method of semiconductor wafers, that is, by reducing the size of the chip to reduce the cost of the chip (but this method may be self-limiting for direct-attached silicon-based RFID electronic tags, Because the smaller the chip, the cost of the attachment process will increase). However, fully printed and non-regional RFID electronic tags may further benefit from the development of certain processes, tools and/or materials. These processes, tools and/or materials may not be widely available or may not be commercially available. The "integrated substrate" referred to in this specification allows the integration of printing techniques and development processes with low cost per unit area. For example, the current processing cost of 0.35 micron silicon chip is US$25/in ² , the processing cost of traditional polysilicon imaging is US$0.50-$0.90/in ² , and the processing cost of printing technology is expected to be much less than US$0.50/in ² .

By using an interposer-based process, some or all of the conventional processes for thin-film imaging and optoelectronic materials are possible. The processing of optoelectronic materials includes well-developed roll-to-roll manufacturing processes for inorganic semiconductors, dielectrics, and other thin films on metal foil plates, sheets, and/or other flexible substrates. For a single film, the cost of this process is around US$0.01/in ² or less. Therefore, for a relatively small substrate (approximately 25 mm ² ), the cost of this process is not high. However, if the entire inductor or wire substrate has to be processed (ie, the area is much larger than 100mm ² ), the cost is expected to be more expensive. This process can provide significant cost savings over low-resolution substrate attachment (US$0.003), and it provides an efficient way to integrate RFID electronic labeling with imaging and optoelectronic materials (or, alternatively, with printing The steps combine to result in a complete manufacturing process that does not wait for the development of a complete tool and material for printed RFID electronic tags.

Ultimately, however, such processes include spool-based and/or roll-to-roll printing processes. This process can lead to lower manufacturing costs due to lower capital equipment costs, high throughput (hundreds of square meters per hour), increased material usage, and/or fewer process steps.

The present invention advantageously provides a low-cost radio frequency and/or radio frequency identification device electronic tag. The radio frequency and/or radio frequency identification device electronic tag can have the standard application and operation of traditional radio frequency, radio frequency identification device electronic tag and/or commodity electronic anti-theft system equipment and systems. By reducing the number of expensive and/or low-volume attachment steps and reducing the cost of fabricating active electronic circuitry, a low-cost electronic label can be produced by directly printing or otherwise forming the circuitry on a substrate. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively cheap cost.

Description of drawings

In order to make the above-mentioned and other purposes, features and advantages of the present invention more obvious and understandable, preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings:

1A to 1C are the steps of a conventional process for manufacturing electronic tags for radio frequency identification devices, the process includes attaching a conventional semiconductor chip to a substrate;

2A and 2B are the key steps of an exemplary process for fabricating an RFID electronic tag/device with an integrated substrate according to the present invention; and

3A to 3H are key steps of an exemplary process for fabricating an integrated circuit on a substrate for an RFID electronic tag/device according to the present invention.

Detailed ways

For convenience and brevity, the words "coupled to", "connected to" and "in communication with" when used herein mean directly or indirectly coupled, connected or communicated, unless the context indicates otherwise. These terms are generally interchangeable and may be used interchangeably, but are generally given their art-recognized meanings. Also, for convenience and simplification, the words "radio frequency", "radio frequency identification" and "identification" are interchangeable depending on the purpose of use and/or a device and/or electronic tag. Also, the words "electronic tag" or "device" herein may refer to any radio frequency and/or radio frequency identification sensor, electronic tag and/or device. Also, the term "integrated circuit" means a single structure that includes a plurality of electrically active devices. These active devices are formed from thin films of conductors, semiconductors, and insulators, but typically do not contain discrete, mechanically attached components (such as chips, wire bonds and leads, substrates, or an antenna and/or inductor components) or A material that mainly has an adhesive function. In addition, the terms "item", "object" and "item" are used interchangeably and when one is used, the other term is also included. In the present invention, a "major face" of a structure or object is defined to some extent by at least the largest axis of the structure or object. For example, if the structure is round and has a radius greater than its thickness, the radial surface [s] (radial surface) is the major face of the structure.

The present invention relates to a radio frequency sensor, a radio frequency anti-theft system and/or a radio frequency identification device, comprising (a) a substrate; (b) an antenna and/or an inductor on the substrate; and (c) in addition to the antenna and and/or outside the inductor, an integrated circuit formed at a location on the substrate. The integrated circuit has a bottommost layer in contact with a surface of the substrate. In various preferred embodiments, the integrated circuit includes thin film transistors, diodes, optional capacitors and/or resistors, and metallization components for interconnecting these circuit components. In other preferred embodiments, at least one layer of the integrated circuit includes a printed or laser patterned layer.

Furthermore, the present invention relates to a manufacturing method for manufacturing a radio frequency sensor, a radio frequency anti-theft system and/or a radio frequency identification device. The manufacturing method generally includes the following steps: (1) forming a lowermost layer of an integrated circuit on a surface of a substrate; (2) forming a continuous layer of the integrated circuit on the lowermost layer of the integrated circuit; and (3) Attaching a conductive layer to the substrate. Alternatively, the manufacturing method may comprise the steps of: (1) forming the lowest layer of the integrated circuit on the surface of the substrate; (2) forming a continuous layer of the integrated circuit on the lowest layer of the integrated circuit; and (3) A conductive structure is formed from an active layer attached to the substrate.

In various preferred embodiments, one or more layers of the integrated circuit are formed by printing or laser patterning the layer of material. In a preferred embodiment, the step of forming the bottom layer of the integrated circuit includes printing or laser patterning the bottom layer.

Furthermore, the present invention relates to a method of detecting an item or object. The method generally comprises the steps of: (A) causing or inducing a current in the antitheft system and/or identification device attached to or associated with the item or object sufficient to cause the device to radiate, reflect or modulate changing a detectable electromagnetic signal; (B) detecting the detectable electromagnetic radiation; and optionally (C) processing information conveyed by the electromagnetic radiation. Optionally, the method may further comprise transmitting or transmitting the information by the identification device (or sensor) to a reading device.

Various aspects of the present invention can be further understood through the following exemplary preferred embodiments.

Exemplary MOS RFID device electronic tag/device

An aspect of the present invention relates to a radio frequency identification device comprising (a) a substrate; (b) an antenna and/or an inductor on the substrate; and (c) in addition to the antenna and/or the inductor, An integrated circuit is formed at a location on the substrate. The integrated circuit has a bottommost layer in contact with a surface of the substrate.

Therefore, the present invention provides a low-cost RFID (or electronic article surveillance system) electronic tag (the electronic tag may also include sensors and active RFID devices, such as electronic tags with a battery). The signal modulation behavior of the sensor typically changes due to some external change in the environment (eg temperature, conductivity of the structure or surface to which the sensor is attached, etc.). The electronic tag includes a substrate, an antenna/inductor and an RF front end (or a subset of the RF front end and logic circuits). The electronic tag is capable of operating according to today's radio frequency identification standards.

It has been shown that printed electronic components based on inorganic materials (e.g., laser-printed nanocrystals) can be formed on certain flexible substrates, such as high-temperature polyimide or metal foil sheets, provided that a suitable A thermal insulation/barrier layer is interposed between the substrate (eg metal foil sheet) and the subsequent layer to be laser treated. Therefore, the present invention utilizes this material as a substrate in a flexible (at least partially flexible) printed product electronic anti-theft system, radio frequency, radio frequency identification device electronic tag or device.

The substrate generally has a size that can be cost-effectively processed by conventional thin film processes and/or novel or state-of-the-art printing processes to produce low cost radio frequency circuits. The integrated circuit can be formed on a flexible substrate, such as polyimide, glass/polymer laminate, high temperature polymer, or metal foil, and the above-mentioned substrate can further include one or more barrier layers. In general, such substrates are substantially less expensive than conventional silicon chips of similar dimensions. However, the substrate of a conventional RFID device usually has an area of 1 cm ² . In comparison, conventional silicon chip-based RFID devices may have an area of 0.01 cm ² or less.

For example, it may be advantageous to use the substrate in the following situations: (1) as an electroplated aluminum, aluminum/copper, stainless steel or similar metal foil plate; (2) as an internal connection, electrode and dielectric Electrodes for bulk storage or IC resonant capacitors and inductors; (3) electrodes for diodes, MOS devices or FETs; and (4) use of the substrate as WORM/OTP, deactivation or other Memory storage components. Examples of applications of such substrates can be found in US Pat. No. 10/885,283 (Attorney Docket IDR0121) and US Pat. No. 11/104,375 (Attorney Docket IDR0312). Therefore, in many preferred embodiments, the antenna and/or inductor will be formed on a first surface of the substrate, and the integrated circuit will be formed on a second surface opposite the first surface of the substrate.

Therefore, the present invention relates to an identification device comprising (a) a substrate; (b) an antenna and/or an inductor formed on a first surface of the substrate; An integrated circuit on a second surface of the first surface of the substrate. The integrated circuit has a bottommost layer in physical contact with the second surface of the substrate.

In a preferred embodiment, the integrated circuit includes at least one printed layer. The printing layer may include a semiconductor layer, an interlayer dielectric, an interconnect metal layer and/or a gate metal layer.

Typically, the integrated circuit may include a gate metal layer, one or more semiconductor layers (eg, a transistor channel layer, a source/drain terminal layer, and/or one or more lightly or heavily doped mixed diode layer), a gate insulating layer between the gate metal layer and the semiconductor layer, one or more capacitor electrodes (each capacitor electrode is typically coupled to another capacitor electrode. The capacitor electrodes may also part of the integrated circuit or the capacitor electrode may be integrated with or part of the substrate or antenna/inductor layer), with the gate metal layer, the source terminal and the drain terminal and/or a topmost diode layer and and/or a plurality of metal conductors electrically connected to the capacitor electrodes and/or an interlayer dielectric layer between the metal conductors and the semiconductor layer. The integrated circuit may further include one or more resistors comprising a metal and/or lightly or heavily doped polysilicon.

In a preferred embodiment, the integrated circuit comprises a gate metal layer, several semiconductor layers (a transistor channel layer in contact with a source/drain terminal layer), between the gate metal layer and the transistor A gate insulation layer between the channel layers and a plurality of metal conductors electrically connected with the gate metal layer, the source terminal and the drain terminal. Exemplary layers of the integrated circuit are detailed below for fabricating a MOS RFID electronic tag/device.

The substrate may comprise a flexible material, and the flexible material can withstand relatively high temperature processing (for example, temperatures ranging from 300°C, 350°C, 400°C, 450°C, or higher, to 500°C, 600°C, or 1000°C .The soft material usually has no significant degradation or degradation in its mechanical and/or electrical properties at such temperatures). For example, the substrate may comprise a thin glass sheet (50-200 microns) or slip, a glass/polymer laminate, a high temperature polymer (e.g., polyimide, polyethersulfone, polyethylene naphthalate [PEN], polyether ether ketone [PEEK], etc.) or a metal foil such as aluminum or stainless steel. Typical thicknesses are based on the materials used, but generally range from 25 microns to about 200 microns (eg, from about 50 microns to about 100 microns).

The antenna and/or inductor may include the antenna, the inductor, or both, and may further include a capacitor electrode coupled to or integrated into the structure described above (see U.S. Patent Application Serial No. 10/885,283 filed on July 6, 2004) and U.S. Patent Application No. 11/104,375 (filed April 11, 2005)). Typically, the antenna and/or inductor includes a metal.

In a preferred embodiment, the metal is a commercially available foil (eg, aluminum, stainless steel, copper, or alloys of these metals). In these cases (the antenna and/or inductor are made of the metal foil plate. On the other hand, the integrated circuit is located on the opposite side of the substrate), making a radio frequency identification and/or electronic article anti-theft device (see below The method of paragraph 1) may further comprise removing a portion or more of the metal from the metal foil sheet. The metal is located under (or on the opposite side of) the active integrated circuit (eg, transistors and diodes, but not necessarily capacitors that use a portion of the metal foil plate as an electrode or plate).

In a preferred embodiment, if an inductor includes an antenna and an inductor, the inductor can be used as a variable inductor (eg, see US Patent Application Serial No. 11/104,375). Therefore, the metal forming the antenna and the inductor may be discontinuous, and an electronic article surveillance system and/or identification device according to the present invention may include a first (e.g., external) capacitor coupled to a first plate capacitor. Inductor, a second (e.g. internal) inductor coupled to a second plate capacitor and formed between the first (external) inductor, the second (internal) inductor and the first and second plate capacitors a dielectric film on it. The first dielectric film has holes to expose the ends of the first inductor and the second inductor (eg, outer and inner).

In another preferred embodiment, the panel capacitor may be linear or nonlinear and/or the device may further comprise first and second nonlinear panel capacitors formed on the dielectric film. The first and second nonlinear plate capacitors are respectively coupled to the first and second linear plate capacitors.

The device of the present invention may further include a support and/or backing layer (not shown) formed on a surface of the inductor 110 opposite to the dielectric film 20 . Such supports and/or support layers are common and existing in the field of electronic article surveillance systems and radio frequency identification devices (see US Patent Publication No. 2002/0163434 and US Patent Nos. 5,841,350, 5,608,379, 4,063,229).

Typically, such supports and/or support layers serve the following functions: (1) as an adhesive surface for the electronic tag/device to be subsequently attached or placed on an item to be tracked or monitored; and/or (2) Some mechanical support for the electronic tag/device. For example, the device of the present invention may be attached to the back of an identification brand or price label, and an adhesive layer is applied to or placed on the surface of the device and is opposite to the identification brand or price label (optional overlay). An existing release sheet (release sheet) until the label is to be used) to form a brand or label for a conventional radio frequency identification system.

Exemplary method of manufacturing a MOS radio frequency identification device electronic tag/device

In a preferred embodiment, the present invention relates to a method of manufacturing an identification device. The manufacturing method comprises the steps of: (1) forming a lowermost layer of an integrated circuit on a surface of a substrate; (2) forming a continuous layer of the integrated circuit on the lowermost layer of the integrated circuit; and (3) A conductive layer is attached to the substrate, usually at a location other than the integrated circuit.

Alternatively, the manufacturing method may further comprise the steps of: (1) forming the lowest layer of the integrated circuit on the surface of the substrate; (2) forming the continuous layer of the integrated circuit on the lowest layer of the integrated circuit and (3) from the substrate (for example, when the substrate comprises a conductive material, such as a metal foil plate) or an active layer attached to the substrate (for example, when the substrate comprises a layer of conductive material plate and a non-conductive material, such as a metal foil plate, with a plated oxide film formed or grown thereon) to form a conductive structure. Therefore, the present invention provides a cost-effective method for manufacturing RFID devices.

2A and 2B illustrate a first exemplary method for manufacturing an RFID device according to the present invention. As shown in FIG. 2A , an electronic tag precursor 100 includes a substrate 132 with contacts 134 , 136 and an integrated circuit 110 thereon. Generally, the integrated circuit 110 is formed on a first major surface of the substrate 132 . Integrated circuit 110 may be a printed inorganic circuit, mainly using US Patent Application No. 10/885,283 (filed on July 6, 2004) and US Patent Application No. 11/104,375 (filed on April 11, 2005). day). Exemplary steps for using this method to form a "bottom gate" device are depicted in partial cross-sectional views in FIGS. 3A-3H .

Afterwards, the contacts 134, 136 and the integrated circuit 110 are formed on the same surface of the substrate 132, which is the same as the process for forming the contacts 34, 36 in FIG. 1A. However, as shown in the exemplary process in FIG. 2A, usually the uppermost dielectric layer in the integrated circuit 110 has a via or hole (sometimes an existing passivation layer) therein. , to electrically connect circuit components there (typically, the uppermost metallization or as an internal interconnect, see FIGS. 3G and 3H and their discussion). Contacts 134, 136 provide substantially the same function as contacts 34, 36 in FIG. 1A.

Vias or holes may then be formed on the major surface of substrate 132, and contacts 134, 136 and integrated circuit 110 are formed on the surface opposite the major surface. Generally, referring to FIG. 2A , a via or hole passes through the substrate 132 and exposes a surface of the contacts 134 , 136 to electrically connect a terminal of the antenna/inductor 152 . Typically, each via/hole is located at a location and has its size. By using a rather high-throughput, low-resolution attach operation (see FIG. ), one terminal of the antenna/inductor 152 and the corresponding contact are easily in contact with each other.

See Fig. 2B again. Antenna and/or inductor 152 (possibly attached or positioned to an applicator sheet 150) is then attached or affixed to substrate 132 such that electrical connections are formed at contacts 134, 136, antenna/inductor 152 The positions of the terminals correspond to the vias or holes in the substrate 132 . A short annealing step (which may further include applying a slight pressure to the opposing major surfaces of the substrate 132 and the coating sheet 150 ) ensures that the inductor and/or antenna 152 are formed on the substrate 132 without error.

The processes described herein generally result in a lower cost electronic label by reducing the number of expensive/low volume attachment steps and lowering the cost of manufacturing the active electronic device. A low-cost electronic label can form the circuit on a substrate by direct printing or other methods. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively cheap cost. The integrated circuit can be formed on a flexible substrate, such as polyimide, glass/polymer laminate, high temperature polymer, or metal foil, and the above-mentioned substrate can further include one or more barrier layers.

The substrate generally has a size that can be cost-effectively processed by conventional thin film processes and/or novel or state-of-the-art printing processes to produce low cost radio frequency circuits. These processes include sputtering, evaporation, LPCVD, PECVD, bath etching, dry etching, direct laser printing of device components, inkjet printing of any component or layer, spray coating, doctor blade coating ( blade coating), extrusion coating (extrusion coating), photolithography, any layer of printed etching mask lithography (such as laser or inkjet), screen printing (offset printing), gravure printing (gravure printing), contact printing, screen printing, and combinations of the above and/or other techniques.

Any layer of material in an integrated circuit according to the present invention may generally be fabricated by any of the techniques described above. In particular, through low-cost process technology, such as printing, or the combination of printing and traditional imaging processes (for example, flat-panel displays), the present invention can manufacture radio frequency identification devices and/or commodity electronic anti-theft electronic tags at low cost . In the latter example, the substrate used to fabricate integrated circuits can be reduced to an effective area upon which blanket-deposited (e.g., by CVD) and/or conventionally formed Active materials used in equipment/processes used to fabricate integrated circuits. Thus, for example, the method of the present invention may further comprise the step of forming one or more second layers in the integrated circuit by conventional imaging processes.

As will be known from the following description, the antenna and/or inductor in the present invention can be formed on the same side or different sides of the substrate. Also, the same processes used to process continuous bobbin or roll-to-roll substrates can be used to fabricate integrated circuits formed on the substrate (in addition to attaching the antenna/inductor structure. In the embodiments described above, the antenna and/or inductor attached to the substrate after fabrication of the integrated circuit).

Exemplary method for fabricating integrated circuits

Typically, integrated circuits are formed directly on a first major surface of the substrate 132 . For "top-gate" devices with integrated capacitors and diodes, the integrated circuit 110 can be implemented using U.S. Patent Application No. 11/084,448 (filed March 18, 2005), U.S. Patent Application No. 11/203,563 (filed August 11, 2005) and U.S. Patent Application Serial No. 11/452,108 (filed January 12, 2006) to form a (partially) printed and substantially inorganic circuit integrated circuit 110.

Exemplary steps in forming a "bottom gate" device are described below in partial cross-sectional views in FIGS. 3A-3H . Many of the techniques described below (although not necessarily for making bottom-gate devices) are also described in U.S. Patent Application No. 11/084,448 (filed March 18, 2005), U.S. Patent Application No. 11/203,563 (Filing date is August 11, 2005) and US Patent Application No. 11/452,108 (application date is January 12, 2006).

Prepare the substrate

See Figure 3A. Substrate 210 may comprise any flexible or non-flexible, conductive or insulating substrate. The substrate has the following functions: (i) when the integrated circuit is formed, it provides physical support for the integrated circuit to be formed on the substrate and for the RF transmitter/receiver assembly to be attached to the substrate; (ii) has the integrated circuit formed thereon. circuitry (preferably printed); and (iii) cause electrical connections to be formed through the substrate, i.e. signals can be emitted between integrated circuits formed on one major surface of the substrate and radio frequency emissions attached to the opposite major surface of the substrate transfer between receiver/receiver components. Thus, the substrate 210 may comprise a metal foil (preferably with a dielectric film (possibly plated) thereon), polyimide, thin glass, or an inorganic/organic laminate substrate.

Typically, the substrate 210 is conventionally cleaned and coated with a barrier material 220, such as silicon dioxide or aluminum oxide, prior to further processing. Coating steps may include oxidation and/or electroplating of a surface material of the substrate (e.g., metal foil plate), barrier films (Honeywell AcuGlass columns or others) deposited by spin or fluid coating, sputtering, CVD, Spray coating a barrier material onto the substrate or any combination of the techniques described above. As shown in FIG. 3A , barrier materials 220 a - b are coated on at least two major surfaces of substrate 210 . Optionally, the surface of at least one barrier material layer (eg, 220a) can be treated (eg, roughened and activated, etc.) and/or cleaned before the next step. In part, the substrate comprises a metal sheet or foil, which can be etched and/or trimmed, as described in U.S. Patent Application Serial No. 10/885,283 (filed July 6, 2004), U.S.A. Patent Application No. 11/104,375 (filed April 11, 2005) and US Patent Application No. 11/452,108 (filed January 12, 2006).

Formation of the internal connection between the gate and the gate layer

See Figure 3B. A gate metal layer 230 may conventionally be sputtered onto the barrier material layer 220a. The gate metal layer 230 may include metals commonly used in integrated circuits and/or printed circuits, such as Al, Ti, Ta, Cr, Mo, W, Fe, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Zn, etc. Alternatively, the gate metal layer 230 may include alloys of the above metals, such as Al—Ti, Al—Cu, Al—Si, Mo—W, Ti—W, and the like. Alternatively, the gate metal layer 230 may include conductive compounds of the above metals, such as titanium nitride, titanium silicide, tantalum nitride, tantalum silicide, molybdenum nitride, molybdenum silicide, tungsten nitride, tungsten silicide, and cobalt silicide. The gate metal layer 230 may have an existing thickness, such as 50nm to 5000nm, preferably 80nm to 3000nm, more preferably 100nm to 2500nm, or any range within the existing thickness range.

Afterwards, a resist can be deposited thereon. The resist material may comprise an existing photoresist or thermal resist, and may be formed on the gate metal layer 230 by conventional methods, such as spin coating or inkjet. Conventional lithography or printing/shaping lithography using laser irradiation can be performed (e.g., selectively irradiating portions of the resistive material and then developing the resistive material [based on whether the resistive material is positive or negative, by conventional developer (See, e.g., U.S. Patent Application Serial No. 11/203,563, filed August 11, 2005) to selectively remove illuminated or non-illuminated portions of the resist material) to leave a patterned resist that defines the gate Material 235 (as in FIG. 3B ) is used to connect internally to the gate level. Internal connections are not shown, but can be located outside the device in the form of an existing "landing pad" or in the active area of a transistor, or on other circuit components formed by the gate metal layer 230.

The exposed gate metal layer 230 is then etched, and the patterned resistive material 235 is stripped to form gates (eg, 232 and 234 in FIG. 3C ) and gate-level internal connections. Alternatively, gate metal layer 230 may be deposited and patterned by printing (eg, inkjet) of a metal precursor ink followed by curing and/or laser patterning of a metal precursor layer. The metal precursor layer may include direct conversion (eg, laser-induced direct conversion to metal) and indirect conversion (eg, laser-induced cross-linking of metal-containing species followed by annealing to form a conductive metal film).

form gate dielectric

See Figure 3D. A gate dielectric layer 240 (comprising, for example, a nitride and/or silicon, aluminum oxide, etc.) is formed by sputtering, CVD, or other blanket deposition processes at the gate and gate-level internal connections 232, 234 superior. The gate dielectric layer 240 may have a thickness of 10 nm to 100 nm, preferably 10 nm to 50 nm, more preferably 10 nm to 40 nm, or any range within the existing thickness range.

Alternatively, the gate dielectric layer 240 may be formed by printing (eg, by inkjet or other printing processes, as described in US Patent Application Serial No. 10/885,283 and/or US Patent Application Serial No. 11/104,375). The gate and gate level internal connections 232,234. Appropriate film attributes and/or properties (eg, thickness, density, and dielectric constant, etc.) can be provided by printing and subsequent processing of several layers. Such subsequent processing may include oxidizing a printed dielectric precursor material (such as silicon and/or aluminum nanoparticles), densifying the dielectric material, and doping the dielectric material wait.

Alternatively, a gate dielectric layer may be formed from gate level metal structures 232 and/or 234 by direct, existing thermal or electrochemical (eg electroplating) oxidation. One or more gate-level metal structures can typically be masked (eg, with a photoresist or laser-patternable resistive material) if no dielectric film is formed thereon.

Form the semiconductor layer

Thereafter, as shown in FIG. 3D , a semiconductor layer 250 (which may include silicon or lightly doped silicon) may be sputtered, coated or blanket deposited (eg, CVD) on the gate dielectric layer 240 . The semiconductor layer 250 may have a thickness ranging from 80 nm to 2000 nm, preferably 100 nm to 1500 nm, more preferably 150 nm to 1000 nm, or any range within the above thickness range. The semiconductor layer 250 formed by conventional lithography process or laser patterning process (eg, see US Patent Application No. 11/203,563 filed on August 11, 2005) can generally serve as a transistor channel.

Alternatively, a contact layer can be deposited by existing masking and ion implantation or by sputtering, coating or other blanket deposition (e.g. CVD) to deposit a heavily doped silicon (source The electrode/drain) contact layer is formed on the semiconductor (channel) layer 250 . The source and drain contact structures 252a and 252b can then be deposited by an existing planarization process such as lapping [chemical mechanical polishing], or by depositing a thermally planarizable ( Thermally planarizable) materials, such as a resistive material and non-selective etch back (etch back)).

Moreover, silicon islands can be formed by existing lithography processes, laser irradiation of thermal resistive materials, or lithography patterning of printed (eg, inkjet) resistive materials, followed by etching or Formed by wet etching and stripping the resist material. Portion 255 of the heavily doped silicon layer over the gate may not be formed (eg, not printed) or removed prior to subsequent processing. The removal method can be through lithography and etching, or by forming an amorphous layer 252, then irradiating (for example, crystallizing) the amorphous layer 252 without using laser light, and removing the non-irradiated part by selective etching .

Alternatively, as shown in FIG. 3E, the semiconducting layer 250 and heavily doped silicon contact layers 252a-b may be printed from a semiconducting (e.g., doped or undoped silane) ink at locations corresponding to the silicon islands ( See, for example, U.S. Patent Application Nos. 10/789,317, 10/950,373, 10/949,013, 10/956,714, and 11/246,014, filed February 27, 2004, September 24, 2004, September 2004, respectively 24, 1 October 2004, 8 October 2004 and 6 October 2005). Typically, the semiconductor layer 250 is printed and then processed before the heavily doped silicon contact layers 252a-b (excluding the portion 255 above the gate) are printed on. After printing, the ink dries, cures, and/or is annealed to change its surface morphology (eg, at least partially crystallize the dried ink). Annealing or laser irradiation may also activate some or all of the dopants in the ink. The printing process not only increases throughput by avoiding the deposition and removal steps of resist material, but also enables the direct formation of discrete source and drain contact layers 252a and 252b.

Formation of interlayer dielectric and via holes

The interlayer dielectric and via holes formed by the semiconductor layer and the gate layer are mainly existing manufacturing processes. For example, as shown in FIG. 3F, a relatively thick dielectric layer 260 can be deposited on the semiconductor layer 250 (if viewed from FIG. 3F, it is the contact layer 252), and then the via hole 262 can be formed by existing The lithography process, laser irradiation of thermal resistance material or lithography patterning process of printed resistance material, followed by an existing dielectric etching process. Alternatively, a patterned dielectric layer 260 (eg, having via holes 262 therein) can be printed onto the semiconductor layer 250 (eg, by inkjet, see description of front gate dielectric layer 240). The interlayer dielectric layer 260 has a thickness. For example, the thickness is at least 0.5 μm, preferably 1 μm to 25 μm, 2 μm to 10 μm, or any range within the aforementioned thickness range.

Form source/drain (S/D) and interlayer interconnects

If heavily doped semiconductor layers 252a-b have not yet been formed (eg, see FIG. 3E ), S/D layer 270 may be sputtered, coated, or otherwise blanket deposited onto ILD layer 260 and conductive In hole 262. In general, S/D layer 270 comprises a heavily doped semiconductor material similar to heavily doped semiconductor layers 252a-b. The S/D layer 270 may have, for example, a thickness ranging from 20 nm to 1000 nm, preferably 40 nm to 500 nm, more preferably 50 nm to 100 nm, or any range within the above thickness range.

See Figure 3G. Interconnect metal layer 280 may be sputtered, coated, or otherwise blanket deposited onto S/D layer 270 (including in via holes 262 ). Interconnect metal layer 280 typically includes a metal, alloy or conductive compound. Similar to the gate metal layer 230, the interconnection metal layer 280 may have, for example, a thickness ranging from 0.5 μm to 10 μm, preferably 0.75 μm to 8 μm, more preferably 1 μm to 5 μm, or any thickness within the above-mentioned range. scope. Since the interconnect metal layer 280 may contact a silicon-containing layer, the interconnect metal layer 280 may further include a lower silicon barrier layer (eg, a metal nitride such as TiN).

Blanket-deposited S/D layer and internal interconnection layer formed by conventional lithography process, laser irradiation of thermal resistive material or lithographic patterning process of inkjet resistive material to define the area of S/D layer and internal interconnection layers, and conventional metal (and semiconductor) etch to form the actual interconnects. Similar connections can be formed at predetermined locations along the gate metal, but a preferred location is a location (eg, other than silicon island 255 ) (eg, see FIG. 3E ).

Alternatively, as shown in FIG. 3H, the S/D structures 272-278 can be printed by a semiconductor (eg, doped or undoped silane) ink on the position corresponding to the via hole 262 (see, for example, US Pat. Application Nos. 10/885,283 and/or 11/104,375). If a non-doped ink is used, the process of forming the S/D structures 272-278 may further include a doping step (eg, including conventional ion implantation or ion shower doping). Thereafter, the interconnect metal structure 280 may be added with low-level adhesive and/or silicon barrier layers, if desired, and formed as previously described.

After the integrated circuit is substantially formed, the method according to the invention may further comprise the step of passivating the integrated circuit and/or the device (for example, forming a passivation layer or dielectric layer on the integrated circuit (to some extent exposed) and part of the substrate). The passivation layer typically inhibits or prevents the ingress of water, oxygen, and/or other species that can cause degradation or failure of the integrated circuit or device, and may add mechanical support to the device, especially during further processing of the device middle.

Traditionally, the passivation layer can be applied by coating one or more inorganic barrier layers on the upper surface of integrated circuits and/or devices. The inorganic barrier layer can be a polysiloxane (polysiloxane), silicon and/or aluminum nitride, oxide and/or and/or one or more inorganic barrier layers (such as paraxylene (parylene) ), a fluoroorganic polymer or other barrier material. Alternatively, the passivation layer may further include an underlying dielectric layer, and the dielectric layer includes a material with a lower stress than the passivation layer. For example, the dielectric layer may comprise an oxide, such as silicon dioxide (e.g., CVD TEOS), USG, FSG, and BPSG, etc., and the passivation layer may comprise silicon nitride or silicon oxynitride . Also, the passivation layer is slightly thicker than the dielectric layer.

With this process feature (or a material further providing some physical or mechanical support to the integrated circuit), the physical or mechanical support function of the substrate is no longer necessary. Accordingly, portions of the substrate supporting the integrated circuit may be completely removed (eg, where the substrate is normally used for insulation) or partially removed. In partially removed examples, the substrate is conductive (eg, a metal foil plate), and the remaining portion of the substrate can form an antenna, one or more inductors, and/or wires. Through the "remaining" substrate to the integrated circuit or to a separate wire connected to the integrated circuit, the wire is used to electrically connect the antenna and/or inductor to a via or contact. In such instances, the substrate in the final device, electronic tag, or sensor may be a dielectric film or other insulator formed on the same surface of the metal foil board and the integrated circuit formed on the metal foil board.

hybrid integrated circuit

Alternatively, the electronic tag precursor (eg, substrate 132 in FIG. 2A with integrated circuit 110 and contacts 132, 134 thereon) may take a "hybrid" form. For example, combining a printed, inorganic semiconductor and/or conductor substrate for an RF "front end" with a relatively cheap, easy-to-manufacture and highly functional organic or off-the-shelf silicon wafer substrate (digital) logic and/or memory circuitry would be beneficial. "RF Front End" means inductors, capacitors, diodes and field effect transistors operating at or near the carrier frequency and/or inductors, capacitors, diodes and field effect transistors used to modulate the carrier frequency . The RF front end is shown by the "IC" region 110 in FIGS. 2A and 2B . These components (and circuit blocks primarily consisting of or consisting of them) are generally analog in nature (e.g., function and/or operate in analog or sequential fashion) and are relatively slow compared to digital logic circuits In this case, a higher performance device may be required.

In the case of organic circuits, this "hybrid" form has certain advantages in terms of material and/or cost of manufacture. Organic circuits may be suitable for use in the controller, logic and/or memory regions of circuits that typically operate at frequencies well below radio frequencies (eg, below MHz or lower). However, organic field effect transistor circuits may not operate efficiently at carrier frequencies (eg, around 13.56 MHz or higher). For example, diodes based on organic materials with desirable rectification, leakage and breakdown characteristics present difficulties in design and fabrication. Also, it is difficult to make organic modulating field effect transistors or organic clock-related field effect transistors operate at the carrier frequency. In this case, a hybrid circuit disclosed herein includes an RF front end and is fabricated directly on the RF front end (to be made on the underlying substrate or carrier) from high performance printed inorganics and an organic logic and/or memory circuit made on top. Therefore, the hybrid circuit is feasible in manufacture.

Accordingly, the present invention relates to a method of manufacturing an identification device or electronic tag. The manufacturing method includes the steps of: (1) forming a lowermost layer of an integrated circuit on a first surface of a substrate; (2) forming a continuous layer of the integrated circuit on the lowermost layer of the integrated circuit; and ( 3) Attaching a conductive layer to a second surface opposite to the first surface of the substrate. Therefore, the present invention can provide a low-cost manufacturing process for manufacturing a radio frequency identification device (or commodity electronic anti-theft system) electronic tag. The electronic tag includes a substrate, a radio frequency front end or a subset of a radio frequency front end and logic circuits.

Exemplary method of reading the radio frequency identification device electronic tag of the present invention

The invention further relates to a detection of an item or object located in a detection zone. The method comprises the steps of: (a) causing or inducing a current in the identification device sufficient to cause the identification device to radiate a detectable electromagnetic signal (preferably, the frequency of the signal is a frequency of an applied electromagnetic field an integer multiple, or the frequency of the applied electromagnetic field is an integer multiple of the frequency of the signal); (b) detecting the detectable electromagnetic radiation; and optionally (c) processing information conveyed by the electromagnetic radiation. Typically, currents and voltages are induced in the identification device sufficient to cause the identification device to radiate detectable electromagnetic signals when the device is located in a detection zone containing an oscillating electromagnetic field. The oscillating electromagnetic field is manufactured or generated by existing electronic anti-theft systems and/or radio frequency identification devices and/or systems.

Accordingly, the method may further comprise the steps of: (d) transmitting or emitting the information from the identification device (or sensor) to a reading device, or prior to step (a), attaching or attaching the identification device to the An object or commodity (for example, a packaged identification card for goods to be shipped). Or, the identification device is included in the object or commodity, or packaged in the object or commodity.

To some extent, the electronic tag of the present invention is designed to work with electronic identification and/or security systems. The electronic identification and/or security system is capable of sensing disturbances in radio frequency electromagnetic fields. Such electronic systems typically create an electromagnetic field in a controlled area defined by portals. Commodities must pass through the controlled area when leaving the controlled premises (for example, a retail store and library, etc.), or the commodities must be placed in a place to be read and identified. An electronic tag having a resonant circuit is attached to each such commodity and is sensed by a receiving system when the electronic tag circuit is located in the controlled area. The receiving system is used to detect the electronic label and process the information obtained from the electronic label (for example, to determine the removal of an unauthorized commodity, or to determine the identity of the item in a container affixed with the electronic label) . Most electronic labels operating on this principle are single-use or disposable, so such electronic labels are manufactured in very large quantities and at low cost.

Alternatively, the electronic tag of the present invention may be in the form of a sensor. When the characteristics and/or properties of the object or commodity to which the electronic tag is attached change, the radio frequency signal modulation characteristics and/or properties of the electronic tag may Follow the change. For example, the sensor of the present invention can be attached to a stainless steel (or other metal) object, structure or surface. As the object, structure or surface changes, the characteristics and/or properties of the RF signal radiated, reflected or modulated by the sensor of the present invention also change in a detectable manner. For example, when steel oxidizes, or a metal with electromagnetic properties is magnetized or carries a current of a minimum threshold value, or the object or surface changes temperature by a predetermined amount or a threshold amount (neglecting the material of the object or surface composition).

The electronic tag of the present invention can be used in (and/or applicable, reusable, if desired) any commercial commodity electronic anti-theft system and/or radio frequency identification device application, and mainly this application any frequency band. For example, the electronic tag of the present invention can use the frequencies and regions and/or ranges described in the following table.

Applications represented in Table 1

Therefore, the present invention also relates to merchandise monitoring technology in which electromagnetic waves are transmitted to an area of the site and the site is protected with a primary frequency (eg 13.56 MHz). Unauthorized merchandise located in this area is sensed by the reception and detection of electromagnetic radiation. Electromagnetic radiation is emitted by the device 100 of the present invention. This emitted electromagnetic radiation may comprise electromagnetic waves of a second or subsequent harmonic frequency and the electromagnetic waves are radiated by the sensor-emitter assembly, brand or film comprising the device of the invention. The device of the present invention is attached to or embedded in the commodity and, in the above circumstances, the trademark or film is not deactivated or, otherwise, the trademark or film leaves the premises with authorization is adjusted.

Conclusion / Summary

Therefore, the present invention provides a MOS identification device with an integrated substrate and methods of manufacturing and using the same.

The device generally includes (a) a substrate; (b) an antenna and/or an inductor formed on a first surface of the substrate; and (c) formed on the first surface opposite the substrate An integrated circuit on a second surface of the . The integrated circuit has a lowermost layer in physical contact (and in some preferred embodiments, electrical contact) with the second surface of the substrate.

The manufacturing method generally includes the following steps: (1) forming the lowest layer of the integrated circuit on a surface of a substrate; (2) forming a continuous layer of the integrated circuit on the lowest layer of the integrated circuit; and (3) Attaching a conductive layer to the other opposite surface of the substrate.

The method of use generally comprises the following steps: (i) causing or inducing a current in the identification device of the present invention sufficient to cause the device to radiate a detectable electromagnetic signal; (ii) detecting the detectable electromagnetic radiation; and optionally (iii) processing the information conveyed by the electromagnetic radiation and/or (iv) transmitting or transmitting the information by the identification device (or sensor) to a reading device.

The present invention advantageously provides a low-cost radio frequency and/or radio frequency identification device electronic tag. The radio frequency and/or radio frequency identification device electronic tag can have the standard application and operation of traditional radio frequency, radio frequency identification device electronic tag and/or commodity electronic anti-theft system equipment and systems. By reducing the number of expensive and/or low-volume attachment steps and reducing the cost of fabricating active electronic circuitry, a low-cost electronic label can be produced by directly printing or otherwise forming the circuitry on a substrate. The substrate is then attached to an inductor/carrier with relatively low accuracy and relatively cheap cost.

The novelty of the present invention may include: (i) direct integration of fabrication/processing steps of the circuitry onto a substrate and/or (ii) direct printing onto a substrate carrier which is then inexpensively attached to a substrate formed on An inductor on the substrate, or the inductor is derived from a low cost substrate material such as metal foil.

In a preferred embodiment, the inductor has a larger area (and thus possibly two larger dimensions) than the substrate. This straightforward manufacturing/processing step is compatible with web, continuous, roll and/or sheet processing, and is compatible with existing soft, thin RF labels, and in electronic labels In the process, the output is increased. Fabrication of circuit components directly on a substrate can result in low-cost manufacturing due to the resolution of the pick-and-place process used to combine the substrate and the inductor/antenna.

The method of the present invention enables the low-cost and cost-effective use of the substrate material of the device. The substrate material is thermally and chemically compatible with the manufacture of radio frequency identification devices and/or electronic product anti-theft system electronic tags and/or provides suitable barrier properties. But in addition, if the substrate material is used for the substrate of an entire electronic tag, the cost may be too expensive.

The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent modifications or replacements without departing from the spirit of the present invention. , these equivalent modifications or replacements are all included within the scope defined by the claims of the present application.

Claims (15)

1. a recognition device, is characterized in that, comprises:

A) substrate, this substrate comprises metal foil plate;

B) an individual layer antenna, is positioned in a coated sheets, and described individual layer antenna adheres to or is attached on described substrate, and described antenna has the first terminal and the second terminal; And

C) integrated circuit, described integrated circuit is directly formed on main on described substrate, described integrated circuit is electrically connected to the described the first terminal of described individual layer antenna by the first through hole or hole, and described second terminal of described individual layer antenna is electrically connected to by the second through hole or hole, described integrated circuit comprises: (i) multiple thin film transistor (TFT) and multiple diode, and the metalized component that (ii) makes described thin film transistor (TFT) and described diode be connected to each other, described integrated circuit comprises at least one printed layers, with the successive layers of a bottom of a surface contact of described substrate and the described integrated circuit on the described bottom.

2. recognition device as claimed in claim 1, is characterized in that: described integrated circuit comprises a gate metal level, semi-conductor layer and the gate insulation layer between described gate metal level and described semiconductor layer.

3. recognition device as claimed in claim 2, is characterized in that: described semiconductor layer comprises one source pole and drain terminal layer.

4. recognition device as claimed in claim 3, is characterized in that: described integrated circuit comprises the several metallic conductors be electrically connected with described gate metal level, source terminal and drain terminal further.

5. recognition device as claimed in claim 4, is characterized in that: described integrated circuit comprises further between the described interlayer dielectric layer waited between metallic conductor and described semiconductor layer.

6. recognition device as claimed in claim 1, is characterized in that: described at least one printed layers comprises at least one in the group be made up of a gate metal level, an interlayer dielectric layer and an interconnecting metal layer.

7. manufacture a method for a recognition device, comprise:

(a) formed an integrated circuit, be positioned at substrate main and a bottom of main physical contact with substrate, described substrate comprises metal foil plate;

B successive layers that () forms described integrated circuit is on main of the bottom of described integrated circuit and described substrate, described integrated circuit comprises: (i) at least one printed layers, (2) multiple thin film transistor (TFT) and diode, and the metalized component that (ii) makes described thin film transistor (TFT) and described diode be connected to each other; And

C () is by an individual layer antenna attachment or be attached to described substrate, described individual layer antenna has the first terminal and the second terminal, described the first terminal is electrically connected to described integrated circuit by the first through hole or hole, and described second terminal is electrically connected to described integrated circuit by the second through hole or hole.

8. method as claimed in claim 7, is characterized in that: the bottom forming described integrated circuit comprises the bottom printing described integrated circuit.

9. method as claimed in claim 7, is characterized in that: the successive layers forming described integrated circuit comprises at least one deck printed in described successive layers.

10. method as claimed in claim 9, is characterized in that: at least one deck in described successive layers comprises semi-conductor layer.

11. methods as claimed in claim 7, is characterized in that: the described successive layers of described integrated circuit comprises: one source pole/drain layer, a brake-pole dielectric layer, a gate metal level and one interconnection/metal layer.

12. methods as claimed in claim 7, is characterized in that: at least one deck in the described bottom of described integrated circuit and described successive layers comprises a transistor channels layer.

13. methods as claimed in claim 7, it is characterized in that: the described bottom forming described integrated circuit comprises the described bottom of printing or forms the described bottom by traditional video picture process, and at least one deck that the described successive layers forming described integrated circuit comprises at least one deck in the described successive layers of printing or formed by traditional video picture process in described successive layers.

14. methods as claimed in claim 7, is characterized in that: described individual layer antenna package containing metal.

15. methods as claimed in claim 7, is characterized in that, comprise further:

Etch a metal foil plate, to form described individual layer antenna.