CN101360393A - Circuit board structure with embedded semiconductor chip and manufacturing method thereof - Google Patents

Abstract

The invention discloses a circuit board structure with embedded semiconductor chip and its making method, the structure includes: the bearing plate is provided with at least one through opening; the semiconductor chip is accommodated in the opening of the bearing plate and provided with an active surface and a non-active surface, and the active surface is provided with a plurality of electrode pads; a dielectric layer formed on the surface of the carrier plate and the semiconductor chip and having multiple openings to expose the electrode pads of the semiconductor chip; the composite circuit layer is formed on the dielectric layer and sequentially consists of a thinned metal layer, a conductive layer and an electroplated metal layer, and a conductive structure is formed in the opening of the dielectric layer so that the composite circuit layer is electrically connected to the electrode pad of the semiconductor chip; therefore, the composite circuit layer formed on the dielectric layer has the characteristics of firmness and better bonding force, so as to reduce the warping caused by the thermal effect of the manufacturing process.

Description

Circuit Board Structure and Manufacturing Method for Embedding Semiconductor Chips

technical field

The invention relates to a structure of a circuit board embedded with a semiconductor chip and a manufacturing method thereof, in particular to a structure with a semiconductor chip embedded in the circuit board and a manufacturing method thereof.

Background technique

Since IBM introduced Flip Chip Package technology in the early 1960s, compared to Wire Bond technology, flip chip technology is characterized by the fact that the electrical connection between the semiconductor chip and the substrate is through solder balls. No ordinary gold thread. The advantage of this flip-chip technology is that the technology can increase the packaging density to reduce the size of the packaging components, and does not need to use long metal wires, so the electrical function can be improved.

Furthermore, in recent years, due to the increase in the demand for high-density, high-speed and low-cost semiconductor chips, and in response to the trend of gradually shrinking the size of electronic products and the requirements for high integration, the industry has developed a method of introducing semiconductor chips into circuits. In the opening of the board, a circuit build-up structure is formed on the surface of the circuit board and the semiconductor chip, so as to increase the packaging density of the semiconductor chip; and the fabrication of the circuit build-up structure is shown in Figures 1A to 1C.

Please refer to FIG. 1A, a carrier plate 11 with an opening 110 is provided, a semiconductor chip 12 is accommodated in the opening 110, and the semiconductor chip 12 has an active surface 12a and a non-active surface 12b corresponding to the active surface, The active surface 12 a has a plurality of electrode pads 121 .

Referring to FIG. 1B , a dielectric layer 13 is formed on the carrier board 11 and the active surface 12 a of the semiconductor chip 12 , and a plurality of openings 130 are formed in the dielectric layer 13 to expose the electrode pads 121 of the semiconductor chip 12 .

Referring to FIG. 1C, a circuit layer 14 is formed on the surface of the dielectric layer 13, and a conductive structure 141 is formed in the opening 130 of the dielectric layer, and the conductive structure 141 is electrically connected to the electrode pad 121 of the semiconductor chip 12; Wherein the circuit layer 14 is made by a semi-additive method, and this is a mature technology so that it will not be described in detail; the above-mentioned process can be repeated later to form a multi-layer circuit, and the semiconductor chip 12 can be packaged in the carrier board 11 , and achieve electrical connection.

However, in the aforementioned manufacturing process, the coefficient of thermal expansion (Coefficient of thermal expansion, CTE) of the carrier board 11, the dielectric layer 13, and the wiring layer 14 differs greatly, and it is easy to cause warpage (Warpage) phenomenon under the temperature change in the manufacturing process. Reduce the quality of the product.

Therefore, how to provide a method that can avoid the problem of poor reliability caused by the large difference in material expansion coefficient in the existing circuit build-up process for embedding semiconductor chips has become an urgent problem to be overcome in the industry.

Contents of the invention

In view of the above-mentioned defects in the prior art, the main purpose of the present invention is to provide a circuit board structure for embedding semiconductor chips and its manufacturing method, which can have firmness and better combination through the adhesive-backed components with a metal layer formed on the dielectric layer. The characteristics of force can improve the bonding force between the composite circuit layer and the dielectric layer composed of thinned metal layer, conductive layer and electroplated metal layer, and effectively reduce the warping phenomenon of the circuit board.

In order to achieve the above-mentioned main purpose, a method for manufacturing a circuit board structure embedded with semiconductor chips of the present invention includes: providing a carrier board, the carrier board is formed with at least one through opening; At least one semiconductor chip is placed, the semiconductor chip has an active surface and a non-active surface corresponding to the active surface, and a plurality of electrode pads are arranged on the active surface; an adhesive-backed element is pressed on the active surface of the carrier plate and the semiconductor chip, The adhesive element is formed with a metal layer on a dielectric layer; a thinning process is performed on the surface of the metal layer of the adhesive element to form a thinned metal layer; the adhesive element is formed with a plurality of openings to expose the An electrode pad of a semiconductor chip; a conductive layer is formed on the surface of the thinned metal layer of the adhesive element and in the opening; a resistance layer is formed on the surface of the conductive layer, and the resistance layer is patterned to form a plurality of openings to Exposing part of the conductive layer; forming an electroplated metal layer on the surface of the conductive layer in the opening of the resistance layer; and removing the resistance layer and its covered conductive layer and thinned metal layer to expose the dielectric of the adhesive element electrical layer, so as to form a composite circuit layer composed of a thinned metal layer, a conductive layer and an electroplated metal layer, and form a conductive structure in the opening of the dielectric layer of the adhesive-backed component.

The back-adhesive element is pressed on the surface of a dielectric layer with a metal layer, or the back-adhesive element is combined with a metal layer with an adhesive layer on the surface of a dielectric layer.

The metal layer of the adhesive component can be copper foil, and the dielectric layer of the adhesive component can be a prepreg; the surface of the metal layer of the adhesive component is thinned by physical or chemical means to form the thinning process. metal layer.

According to the above manufacturing method, a circuit build-up structure is formed on the surface of the dielectric layer and the composite circuit layer of the adhesive component. The circuit build-up structure is composed of a plurality of dielectric layers and composite circuit layers of the adhesive component. , and the circuit build-up structure has a conductive structure to electrically connect the semiconductor chip, and a plurality of electrical connection pads are formed on the outer surface of the circuit build-up structure, and the circuit build-up structure includes at least one dielectric layer stacked on the A composite circuit layer on the dielectric layer, and a conductive structure formed in the dielectric layer, and a solder resist layer is formed on the circuit build-up structure, and a plurality of openings are formed in the solder resist layer to expose the Electrical connection pads.

In addition, according to the above-mentioned manufacturing method, further comprising forming a circuit build-up structure on the surface of the dielectric layer and the composite circuit layer of the adhesive-backed component, and the circuit build-up structure is composed of a plurality of dielectric layers and circuit layers, and The circuit layer is composed of a conductive layer and an electroplated metal layer, the circuit build-up structure includes at least one dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and The conductive structure is electrically connected to the circuit layer, and a plurality of electrical connection pads are formed on the outer surface of the circuit build-up structure, and a solder resist layer is formed on the circuit build-up structure, and a plurality of openings are formed in the solder resist layer holes to expose the electrical connection pads.

According to the method described above, the present invention also provides a circuit board structure for embedding semiconductor chips, comprising: a carrier board having at least one through opening; a semiconductor chip accommodated in the opening of the carrier board, and the semiconductor chip The chip has an active surface and a non-active surface, and there are a plurality of electrode pads on the active surface; a dielectric layer is formed on the carrier plate and the surface of the semiconductor chip, and the dielectric layer has a plurality of openings to expose the electrodes of the semiconductor chip pad; and a composite circuit layer formed on the dielectric layer, the composite circuit layer sequentially includes a thinned metal layer, a conductive layer and an electroplated metal layer, and a conductive structure is formed in the opening of the dielectric layer The composite circuit layer is electrically connected to the electrode pad of the semiconductor chip.

According to the above structure, it further includes a circuit build-up structure formed on the surface of the dielectric layer and the composite circuit layer, and the circuit build-up structure is composed of a plurality of dielectric layers and circuit layers of adhesive-backed components, or the circuit The build-up structure is composed of a plurality of dielectric layers and circuit layers; the circuit build-up structure has a conductive structure to be electrically connected to the composite circuit layer, and a plurality of electrical connection pads are formed on the outer surface of the circuit build-up structure, The circuit build-up structure includes at least one dielectric layer, a composite circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and a solder mask is formed on the circuit build-up structure layer, and a plurality of openings are formed in the solder resist layer to expose the electrical connection pads.

In addition, according to the aforementioned structure, it further includes forming a circuit build-up structure on the surface of the dielectric layer and the composite circuit layer, and the circuit build-up structure is composed of a plurality of dielectric layers and circuit layers, and the circuit layer is Consisting of a conductive layer and an electroplated metal layer, the circuit build-up structure includes at least one dielectric layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and the conductive structure is electrically To connect the composite circuit layer, a plurality of electrical connection pads are formed on the outer surface of the circuit build-up structure, and a solder resist layer is formed on the circuit build-up structure, and a plurality of openings are formed in the solder resist layer to The electrical connection pad is exposed.

In the adhesive-backed component of the present invention, a metal layer is formed on the dielectric layer. The metal layer is preferably copper foil, and the rough surface of the copper foil is used to press a dielectric layer. The material is prepreg, or by The adhesive layer combines the rough surface of the copper foil with the prepreg to produce better bonding force. Among them, using the prepreg containing glass fiber as the dielectric layer can effectively reduce warpage and size variation. Due to the combination of the metal layer and the dielectric layer, the present invention improves the bonding force between the composite circuit layer and the dielectric layer composed of the thinned metal layer, the conductive layer and the electroplated metal layer, and effectively reduces the warpage of the circuit board. bending phenomenon.

Description of drawings

1A to 1C are cross-sectional schematic diagrams of the manufacturing method of semiconductor chips embedded in circuit boards in the prior art;

2A to 2G are schematic cross-sectional views of the circuit board structure of the embedded semiconductor chip of the present invention and its manufacturing method;

Fig. 2A ' is another implementation sectional schematic diagram of Fig. 2A of the circuit board structure of the embedded semiconductor chip of the present invention and its manufacturing method;

Fig. 2B ' is another implementation cross-sectional schematic diagram of Fig. 2B of the circuit board structure of the embedded semiconductor chip of the present invention and its manufacturing method;

3A and FIG. 3B are schematic cross-sectional views of circuit board structure of the present invention for circuit build-up structure; and

FIG. 4 is a schematic cross-sectional view of another embodiment of the circuit board structure of the present invention with a circuit build-up structure.

Description of component symbols

11, 21 Loading board

110, 210 opening

12, 22 Semiconductor chips

121, 221 Electrode pads

12a, 22a Active face

12b, 22b Non-active side

13, 231, 271, 271' dielectric layer

130, 230, 250, 280 opening

14. 272 Line layer

141, 261, 273, 273' conductive structure

20 Composite line layer

21a Release film

21b Adhesive materials

23, 23' Adhesive components

232’ thinned metal layer

232 metal layer

233 Adhesive layer

24 Conductive layer

25 barrier layer

26 Electroplated metal layer

27, 27' Line-increased structure

274, 274' electrical connection pad

28 Solder mask

Detailed ways

The implementation of the present invention is described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

Please refer to FIG. 2A to FIG. 2G , which are schematic cross-sectional views of an embodiment of a circuit board structure and manufacturing method for embedding semiconductor chips according to the present invention.

As shown in FIG. 2A, at least one through opening 210 is formed in a carrier plate 21, and at least one semiconductor chip 22 is accommodated in the opening 210. The semiconductor chip 22 has an active surface 22a and an active surface corresponding to the active surface. The non-active surface 22b has a plurality of electrode pads 221 on the active surface 22a; and an adhesive element 23 is provided, and the adhesive element 23 is formed on a dielectric layer 231 with a metal layer 232, and the metal layer 232 has The rough surface has better bonding to be integrated with the dielectric layer 231; wherein the metal layer 232 can be copper foil, and the dielectric layer is a prepreg; please also refer to FIG. 2A', or the The adhesive-backed component 23 can also bond the metal layer 232 with an adhesive layer 233 on the surface of a dielectric layer 231 . The aforesaid metal layer 232 can preferably be copper foil, and a prepreg can be bonded on the rough surface of the copper foil or the rough surface of the copper foil can be combined with the prepreg through the adhesive layer 233 to produce a better Combining force, and using the prepreg material containing glass fiber as the dielectric layer 231 can effectively reduce warping and size variation; for the convenience of description, the diagram in FIG. 2B is used for illustration below.

As shown in FIG. 2B , the dielectric layer 231 of the adhesive-backed component 23 is pressed onto the carrier plate 21 and the active surface 22a of the semiconductor chip 22, and the dielectric layer 231 is pressed into the gap between the semiconductor chip 22 and the opening 210. the gap between them, so as to fix the semiconductor chip 22 in the opening 210 .

Also refer to FIG. 2B', the bottom surface of the carrier board 21 can be pasted with a release film 21a first, and then the semiconductor chip 22 is placed in the opening 210, and then the semiconductor chip 22 and the opening 210 are filled with an adhesive material 21b. In the gap between, so as to fix the semiconductor chip 22 in the opening 210; for the convenience of description, the diagram of FIG. 2B is used for illustration below.

As shown in FIG. 2C, the surface of the metal layer 232 of the adhesive-backed component 23 is then subjected to a physical or chemical thinning process to form a thinned metal layer 232'.

As shown in FIG. 2D , a plurality of openings 230 are formed in the adhesive-backed component 23 to expose the electrode pads 221 of the semiconductor chip 22 .

As shown in FIG. 2E , a conductive layer 24 is formed on the surface of the thinned metal layer 232 ′ of the adhesive-backed element 23 and in the opening 230 , and the conductive layer 24 is electrically connected to the electrode pad 221 of the semiconductor chip 22 , and A resist layer 25 is formed on the surface of the conductive layer 24 , and the resist layer 25 is patterned (eg, exposed, developed) to form an opening 250 to expose part of the conductive layer 24 .

As shown in FIG. 2F, an electroplated metal layer 26 is formed on the surface of the conductive layer 24 of the resistance layer opening 250 through the conductive layer 24 as a current conduction path, and a conductive layer 26 is formed in the opening 230 of the dielectric layer 231. Structure 261.

As shown in FIG. 2G, the resistive layer 25, the conductive layer 24 and the thinned metal layer 232' covered by it are then removed, so as to form the electroplated metal layer 26, the conductive layer 24 and the thinned metal layer 232'. The composite circuit layer 20 is formed, and the composite circuit layer 20 is electrically connected to the electrode pad 221 of the semiconductor chip 22 through the conductive structure 261 .

Since the composite circuit layer 20 forms the conductive layer 24 and the electroplated metal layer 26 on the thinned metal layer 232' of the adhesive element 23, the warpage caused by the difference in coefficient of thermal expansion ( Warpage) phenomenon to improve product quality.

Please refer to Fig. 3A and Fig. 3B, in addition, on the dielectric layer 231 of the adhesive-backed element 23 and the surface of the composite circuit layer 20, another adhesive-backed element 23' is pressed together, as shown in Fig. 3A; then the adhesive-backed element 23' will form another composite circuit layer through the aforementioned manufacturing process, so as to form a circuit build-up layer structure 27 with a plurality of dielectric layers 231 of adhesive-backed components 23 and composite circuit layer 20, as shown in FIG. 3B, the circuit The build-up structure 27 includes at least one dielectric layer 271, a circuit layer 272 stacked on the dielectric layer 271, and a conductive structure 273 formed in the dielectric layer 271, and the conductive structure 273 is electrically connected to the formed On the composite circuit layer 20, a plurality of electrical connection pads 274 are formed on the outer surface of the circuit build-up structure, and a solder resist layer 28 is formed on the circuit build-up structure 27, and multiple solder resist layers are formed in the solder resist layer 28. An opening 280 is provided to expose the electrical connection pad 274.

Please refer to FIG. 4, a circuit build-up structure 27' is formed on the surface of the dielectric layer 231 and the composite circuit layer 20 of the adhesive component 23, which is formed on the dielectric layer 231 and the composite circuit layer of the adhesive component 23. 20, a dielectric layer 271' is first formed on the surface of the dielectric layer 271', and then a circuit layer 272' is formed on the surface of the dielectric layer 271', and at least one conductive structure 273' is formed in the dielectric layer 271', and the circuit layer is formed by It is composed of a conductive layer and an electroplated metal layer. This kind of circuit build-up technology is a mature technology, so it will not be described in detail here; and a plurality of electrical connection pads 274' are formed on the outer surface of the circuit build-up structure 27', and are A solder resist layer 28 is formed on the circuit build-up structure 27 ′, and a plurality of openings 280 are formed in the solder resist layer 28 to expose the electrical connection pads 274 ′.

The adhesive-backed component of the present invention forms a metal layer on a dielectric layer, and the metal layer can be preferably copper foil, and is pressed on the dielectric layer with the rough surface of the copper foil, and the dielectric layer The material is prepreg, or the rough surface of the copper foil is combined with the prepreg through the adhesive layer, which can produce better bonding force. Among them, the use of glass fiber-containing prepreg as the dielectric layer can also effectively reduce the Warpage and size variation. Due to the combination of the metal layer and the dielectric layer, the present invention improves the bonding force between the composite circuit layer and the dielectric layer composed of the thinned metal layer, the conductive layer and the electroplated metal layer, and effectively reduces the warpage of the circuit board. bending phenomenon.

The above-mentioned embodiments are only illustrative to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope of the claims.

Claims (24)

1. A circuit board structure for embedding semiconductor chips, comprising: The carrying plate has at least one through opening; A semiconductor chip is accommodated in the opening of the carrier plate, the semiconductor chip has an active surface and a non-active surface, and a plurality of electrode pads are arranged on the active surface; a dielectric layer formed on the surface of the carrier plate and the semiconductor chip, and the dielectric layer has a plurality of openings to expose the electrode pads of the semiconductor chip; and A composite circuit layer is formed on the dielectric layer, the composite circuit layer is sequentially composed of a thinned metal layer, a conductive layer and an electroplated metal layer, and a conductive structure is formed in the opening of the dielectric layer for The composite circuit layer is electrically connected to the electrode pads of the semiconductor chip. 2. The circuit board structure for embedding semiconductor chips according to claim 1, further comprising a circuit build-up structure forming the dielectric layer and the composite circuit layer surface. 3. The circuit board structure for embedding semiconductor chips according to claim 2, wherein the circuit build-up structure is composed of a plurality of dielectric layers and composite circuit layers. 4. The circuit board structure for embedding semiconductor chips according to claim 3, wherein the circuit build-up structure has a conductive structure to be electrically connected to the compound circuit layer formed on the circuit layer, and the circuit build-up structure Multiple electrical connection pads are formed on the surface. 5. The circuit board structure for embedding semiconductor chips according to claim 4, further comprising a solder resist layer formed on the surface of the circuit build-up layer structure, and a plurality of openings are formed in the solder resist layer to expose the electrical connection pad. 6. The circuit board structure for embedding semiconducting elements according to claim 3, wherein the circuit build-up structure comprises at least one dielectric layer, a composite circuit layer stacked on the dielectric layer, and formed on Conductive structures in the dielectric layer. 7. The circuit board structure for embedding semiconductor chips according to claim 2, wherein the circuit build-up structure is composed of a plurality of dielectric layers and circuit layers, and the circuit layer is composed of an electroplated metal layer and a conductive layer constituted. 8. The circuit board structure for embedding semiconductor chips according to claim 7, wherein the circuit build-up structure has a conductive structure to be electrically connected to the composite circuit layer formed on the circuit layer, and the outer surface of the circuit build-up structure is formed A plurality of electrical connection pads. 9. The circuit board structure for embedding semiconductor chips according to claim 8, further comprising a solder resist layer formed on the circuit build-up structure, and a plurality of openings are formed in the solder resist layer to expose the electrical connection pad. 10. The circuit board structure for embedding semiconducting elements according to claim 7, wherein the circuit build-up structure comprises at least one dielectric layer, a circuit layer stacked on the dielectric layer, and a circuit layer formed on the dielectric layer. Conductive structures in electrical layers. 11. The circuit board structure for embedding semiconductor chips according to claim 1, wherein the dielectric layer is a prepreg material. 12. A method for manufacturing a circuit board structure embedded with semiconductor chips, comprising: providing a carrying plate, the carrying plate is formed with at least one through opening; Accommodating at least one semiconductor chip in the opening of the carrier plate, the semiconductor chip has an active surface and a non-active surface corresponding to the active surface, and has a plurality of electrode pads on the active surface; Pressing an adhesive-backed component on the active surface of the carrier board and the semiconductor chip, the adhesive-backed component is formed with a metal layer on a dielectric layer; performing a thinning process on the surface of the metal layer of the adhesive element to form a thinned metal layer; The adhesive-backed element is formed with a plurality of openings to expose the electrode pads of the semiconductor chip; A conductive layer is formed on the surface of the thinned metal layer and the openings of the adhesive-backed component; A resistance layer is formed on the surface of the conductive layer, and the resistance layer is patterned to form a plurality of openings to expose part of the conductive layer; forming an electroplated metal layer on the surface of the conductive layer in the opening of the resistance layer; and Remove the resistance layer and its covered conductive layer and thinned metal layer to expose the dielectric layer of the adhesive component, so as to form a composite circuit composed of thinned metal layer, conductive layer and electroplated metal layer layer, and form a conductive structure in the opening of the adhesive-backed component dielectric layer for the composite circuit layer to be electrically connected to the electrode pad of the semiconductor chip. 13. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 12, further comprising forming a circuit build-up structure on the surface of the dielectric layer and the composite circuit layer. 14. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 12, wherein the circuit build-up structure is composed of a plurality of dielectric layers and composite circuit layers of adhesive-backed components. 15. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 14, wherein the circuit build-up layer has a conductive structure to be electrically connected to the composite circuit layer formed on the circuit board, and the circuit build-up layer A plurality of electrical connection pads are formed on the outer surface of the layer structure. 16. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 15, further comprising a solder resist layer formed on the surface of the circuit build-up layer structure, and forming a plurality of openings in the solder resist layer to expose the Electrical connection pads. 17. The method for manufacturing a circuit board structure embedded with semiconducting elements according to claim 14, wherein the circuit build-up structure comprises at least one dielectric layer and a composite circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer. 18. The method for manufacturing a circuit board structure for embedding semiconductor chips according to claim 13, wherein the circuit build-up structure is composed of a plurality of dielectric layers and circuit layers, and the circuit layer is composed of a conductive layer and a circuit layer. Composed of electroplated metal layers. 19. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 18, wherein the circuit build-up structure has a conductive structure to be electrically connected to the composite circuit layer formed on the circuit layer, and the circuit build-up structure A plurality of electrical connection pads are formed on the outer surface. 20. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 19, further comprising a solder resist layer formed on the circuit build-up structure, and forming a plurality of openings in the solder resist layer to expose the Electrical connection pads. 21. The method for manufacturing a circuit board structure embedded with semiconducting elements according to claim 18, wherein the circuit build-up structure comprises at least one dielectric layer, a circuit layer stacked on the dielectric layer, and forming Conductive structures in the dielectric layer. 22. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 12, wherein the adhesive-backed component is laminated with a metal layer on the surface of a dielectric layer. 23. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 12, wherein the adhesive-backed component is bonded to a metal layer with an adhesive layer on the surface of a dielectric layer. 24. The method for manufacturing a circuit board structure embedded with semiconductor chips according to claim 12, wherein the dielectric layer is a prepreg material.

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