CN101359670A - Active driving TFT matrix construction and manufacturing method thereof - Google Patents
Active driving TFT matrix construction and manufacturing method thereof Download PDFInfo
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- CN101359670A CN101359670A CNA200710119784XA CN200710119784A CN101359670A CN 101359670 A CN101359670 A CN 101359670A CN A200710119784X A CNA200710119784X A CN A200710119784XA CN 200710119784 A CN200710119784 A CN 200710119784A CN 101359670 A CN101359670 A CN 101359670A
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- 239000011159 matrix material Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000010276 construction Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 20
- 239000002131 composite material Substances 0.000 claims description 18
- 239000012528 membrane Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910004205 SiNX Inorganic materials 0.000 claims description 12
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000003860 storage Methods 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 2
- 229910016048 MoW Inorganic materials 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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Abstract
The invention discloses an active driving TFT matrix structure, comprising a baseplate, grid lines and a gate electrode which are formed on the baseplate, and a gate electrode insulating layer formed above the grid lines, the gate electrode and the baseplate. A gate electrode insulating layer via hole is arranged between two neighboring grid lines. The matrix structure further comprises a data line, part of which is formed above the gate electrode insulating layer; the other part of the data line is formed in the gate electrode insulating layer via hole between two neighboring grid lines and is crossed with the grid lines, defining pixel units; and each pixel unit is at least composed of a thin film transistor and a pixel electrode. The invention also discloses a method for fabricating the active driving TFT matrix structure. The invention increases the distance of the pixel electrode and the data line by forming the gate electrode insulating layer via hole on the gate electrode insulating layer, thus effectively reducing the parasitic capacitance between the pixel electrode and the data line.
Description
Technical field
The present invention relates to a kind of LCD (LCD) structure and manufacture method thereof, relate in particular to a kind of active drive thin film transistors (TFT) matrix structure and manufacture method thereof in the LCD.
Background technology
In recent years, along with popularizing of digital to television, traditional CRT shows because its digitlization difficulty, and volume is big, weight big and shortcoming such as radiation is arranged, occurred by the alternative trend of Display Technique of new generation, representational new Display Technique has PDP, OLED, LCD etc.Wherein, LCD is in light weight owing to having, and volume is thin, radiationless, power consumption is little and the display resolution advantages of higher, has begun a large amount of popularizing, begins to become main product.
The array processes of LCD Display Technique generally adopts BCE (back of the body channel etching) structure and ES (etching blocking-up) structure; Wherein the BCE structure can reduce advantages such as channel length because it can reduce mask (Mask) technology number of times, is generally adopted in present stage.
But existing LCD technology still has much room for improvement.Existing TFT mostly is the n type greatly, is conducting state when applying the gate electrode voltage pulse Vg of positive polarity, and the voltage Vs that puts on drain electrode is written among the load capacitance of being made up of storage capacitance Cs and liquid crystal layer capacitor C lc; When gate electrode voltage is 0V, TFT becomes off-state, the electric charge that is written into load capacitance is held, to liquid crystal layer continue to apply voltage Vlc=Vp-Vcom. wherein Vp be load capacitance, Vcom is the bias voltage of the public electrode of folder liquid crystal layer, this state remains to always next time that TFT becomes conducting state, till the work that next time writes begins.But, the voltage Vp of hold mode load capacitance and the voltage Vpo that writes fashionable load capacitance and inconsistent, produce Cha Zhi ⊿ P=Vpo-Vp, this is owing to the drift value that various parasitic capacitances generation electric charges are redistributed the ⊿ P that causes is preferably revised with the drive circuit of signal voltage in advance, but general easy method is very little at design Shi Shi ⊿ P, and by adjusting Vcom voltage, with compensation average drift amount, when compensation is abundant inadequately, liquid crystal layer has DC component to apply, and because of the influence of the removable ion in the liquid crystal layer etc. produces the existing picture of V-Block Mura (the vertically banded non-uniform areas that shows), has a strong impact on the picture display quality.
It shown in Fig. 1 a the schematic diagram of a pixel cell of prior art array plane structure; Fig. 1 b is the schematic cross-section in its A-A zone.Shown in Fig. 1 a and Fig. 1 b, this array structure comprises: one group of grid line 1 and one group of vertical with it data wire 5, adjacent grid line and data wire have defined pixel region.Each pixel packets contains a TFT switching device and pixel electrode 10.The TFT device is made up of gate electrode 2, grid electrode insulating layer 4, semiconductor active layer 3 and source electrode 6 and drain electrode 7.Passivation layer 8 covers on the above-mentioned each several part, and forms the via hole 9 of transpassivation layer above drain electrode 7.Pixel electrode 10 is connected with the drain electrode 7 of TFT by the via hole 9 of passivation layer.Pixel electrode 10 parts and grid line ledge 11 form storage capacitance together.
Between pixel electrode 10 that indicates among Fig. 1 b and the data wire 5 because grid electrode insulating layer 4 forms parasitic capacitance Cpd, difference in height T1 between the size of Cpd and pixel electrode 10 and the data wire is closely related, because Cpd is excessive, cause the voltage Piao Yi ⊿ P of load excessive, thereby cause V-Block Mura, have a strong impact on picture quality.
Said structure can be by following technology manufacture method preparation.
At first deposition grid metal on glass substrate forms grid line 1 by grid line mask (Gate Mask) and grid line etching (Gate Etch) technology then, and grid line ledge 11 is used as follow-up formation storage capacitance, gate electrode 2, as shown in Figure 2; Deposit grid electrode insulating layer 4 then, amorphous silicon layer and N+ silicon layer form semiconductor active layer 3 by active layer mask (Active Mask) and active layer etching (Active Etch), shown in Fig. 3 a and 3b; Sedimentary origin leaks (SD) metal level afterwards, forms data wire 5 and source electrode 7 and drain electrode 6 by source-drain electrode mask (SD Mask) and source-drain electrode etching (SD Etch), and is as shown in Figs. 4a and 4b; Then deposit passivation layer (PVX) 8 forms via hole 9 by passivation layer mask (PVXMask) and passivation layer etching (PVX Etch); Last pixel deposition electrode (ITO) layer forms pixel electrode 10 and makes pixel electrode 10 contact conducting with source electrode 7 by via hole by pixel electrode mask (ITO Mask) and pixel electrode etching (ITO Etch), shown in Fig. 5 a and 5b.
Summary of the invention
The objective of the invention is in order to overcome the defective of prior art, a kind of active driving TFT matrix construction is provided, by on the grid electrode insulating layer, forming grid electrode insulating layer via hole, increase the spacing between pixel electrode and the data wire, thereby effectively reduce pixel electrode and data wire parasitic capacitance between the two.
To achieve these goals, the invention provides a kind of active driving TFT matrix construction, comprising:
One substrate;
One grid line and gate electrode are formed on the described substrate;
One grid electrode insulating layer is formed on described grid line and gate electrode and the substrate, and is formed with grid electrode insulating layer via hole between described adjacent grid line;
One data wire, part is formed on the described grid electrode insulating layer, part is formed between the described adjacent grid line in the grid electrode insulating layer via hole, and and grid line intersect definition one pixel cell;
Wherein each pixel cell comprises at least with a film transistor device and a pixel electrode.
In the such scheme, described grid line further comprises a grid line ledge, and described pixel electrode part is formed on the top of this grid line ledge, constitutes storage capacitance jointly with the grid line ledge.Described grid line and gate electrode can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr etc., perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr etc. or composite membrane that combination in any constituted.Described grid electrode insulating layer can be the monofilm of SiNx, SiOx or SiOxNy etc., perhaps can be the monofilm of Mo, MoW or Cr etc., perhaps be constituted composite membrane by one of Mo, MoW or Cr etc. or combination in any for one of SiNx, SiOx or SiOxNy etc. or the described source-drain electrode of composite membrane that combination in any constituted.
To achieve these goals, the present invention provides a kind of manufacture method of active driving TFT matrix construction simultaneously, comprising:
In the such scheme, described step a kind can further form the grid line ledge when forming grid line, and the pixel electrode part that step 6 forms is positioned at the top of grid line ledge, forms storage capacitance jointly.The grid metal level that obtains of deposition can be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr etc. in the described step 1, perhaps can be one of AlNd, Al, Cu, Mo, MoW or Cr etc. or composite membrane that combination in any constituted.The grid electrode insulating layer that obtains of deposition can be the monofilm of SiNx, SiOx or SiOxNy etc. or one of SiNx, SiOx or SiOxNy etc. or composite membrane that combination in any constituted in the described step 2.Deposition obtains the source and leaks monofilm that metal level is Mo, MoW or Cr etc. or one of Mo, MoW or Cr etc. or composite membrane that combination in any constituted in the described step 4.
The present invention is with respect to prior art, owing to below data wire, form grid electrode insulating layer via hole, effectively reduced the parasitic capacitance between pixel electrode and the data wire, increased the technology degree of freedom, reduce the picture quality bad phenomenon of vertical banded Mura, improved rate of finished products.
Description of drawings
Fig. 1 a is the schematic diagram of a pixel cell of prior art array plane structure;
Fig. 1 b is the sectional view in A-A zone among Fig. 1 a;
Fig. 2 is the floor map that forms in the prior art behind grid line and the gate electrode;
Fig. 3 a is the floor map behind the formation semiconductor active layer in the prior art;
Fig. 3 b is the sectional view in B-B zone among Fig. 3 a;
Fig. 4 a is the floor map that forms in the prior art behind data wire and the source-drain electrode;
Fig. 4 b is the sectional view in C-C zone among Fig. 4 a;
Fig. 5 a is the floor map behind the formation via hole in the prior art;
Fig. 5 b is the sectional view in D-D zone among Fig. 6 a;
Fig. 6 a is the schematic diagram of a pixel cell of array plane structure of the present invention;
Fig. 6 b is the sectional view in E-E zone among Fig. 6 a;
Fig. 7 is the floor map that forms among the present invention behind grid line and the gate electrode;
Fig. 8 a is the floor map behind the formation grid electrode insulating layer via hole among the present invention;
Fig. 8 b is the sectional view in F-F zone among Fig. 8 a;
Fig. 9 a is the floor map behind the formation semiconductor active layer among the present invention;
Fig. 9 b is the sectional view in G-G zone among Fig. 9 a;
Figure 10 a is the floor map that forms among the present invention behind data wire and the source-drain electrode;
Figure 10 b is the sectional view in H-H zone among Figure 10 a;
Figure 11 a is the floor map behind the formation via hole among the present invention;
Figure 11 b is the sectional view in I-I zone among Figure 11 a.
Mark among the figure: 1, grid line; 2, gate electrode; 3, semiconductor active layer; 4, grid electrode insulating layer; 5, data wire; 6, drain electrode; 7, source electrode; 8, passivation layer; 9, via hole; 10, pixel electrode; 11, grid line ledge; 12, grid electrode insulating layer via hole.
Embodiment
Below in conjunction with description of drawings and first-selected specific embodiment, the present invention is illustrated in further detail.
It shown in Fig. 6 a the schematic diagram of a pixel cell of array plane structure of the present invention; Fig. 6 b is the schematic cross-section at its E-E position.Shown in Fig. 6 a and Fig. 6 b, this array structure comprises: one group of grid line 1 and one group of vertical with it data wire 5, adjacent grid line and data wire have defined a pixel cell.Each pixel cell includes a TFT switching device and pixel electrode 10.The TFT device is made up of gate electrode 2, grid electrode insulating layer 4, semiconductor active layer 3 and source electrode 7 and drain electrode 6.Passivation layer 8 covers on the above-mentioned each several part, and forms the via hole 9 of transpassivation layer above drain electrode 7.Pixel electrode 10 is connected with the source electrode 7 of TFT by the via hole 9 of passivation layer.Pixel electrode 10 parts and grid line ledge 11 form storage capacitance together, and said structure is with of the prior art identical.The present invention is different from prior art and is characterised in that: grid electrode insulating layer 4 is formed with grid electrode insulating layer via hole 12 in the position that forms data wire, and in grid electrode insulating layer via hole 12 positions, data wire 5 is formed directly in this grid electrode insulating layer via hole 12.
Shown in Fig. 6 b, because data wire 5 is formed directly in the grid electrode insulating layer via hole 12, increased distance between pixel electrode 10 and the data wire 5, shown in T2 among the figure, therefore the present invention can effectively reduce the parasitic capacitance between pixel electrode 10 and the data wire 5, can increase the technology degree of freedom, reduce vertical banded Mura and picture quality bad phenomenon, improve the product yield.
Grid line of the present invention and gate electrode may further be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.The grid electrode insulating layer may further be the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.Source-drain electrode may further be the monofilm of Mo, MoW or Cr, is perhaps constituted composite membrane by one of Mo, MoW or Cr or combination in any.
To achieve these goals, the present invention provides a kind of manufacture method of active driving TFT matrix construction simultaneously, comprising:
At first, deposition grid metal forms grid line 1 by grid line mask (Gate Mask) and grid line etching (Gate Etch) technology then on glass substrate, comprises grid line ledge 11 (as follow-up formation storage capacitance), gate electrode 2, as shown in Figure 7;
Then, deposition grid electrode insulating layer 4 by insulating barrier mask and etching technics, forms grid electrode insulating layer via hole 12, shown in Fig. 8 a and 8b below data wire;
Then, deposited amorphous silicon layer and N+ silicon layer form semiconductor active layer 3 by active layer mask (Active Mask) and active layer etching (Active Etch), shown in Fig. 9 a and 9b;
Afterwards, sedimentary origin leaks (SD) metal level, form data wire 5 and source electrode 7 and drain electrode 6 by source-drain electrode mask (SD Mask) and source-drain electrode etching (SD Etch), wherein the data wire 5 of grid electrode insulating layer 4 top is embedded in the grid electrode insulating layer via hole 12, shown in Figure 10 a and 10b;
Again, deposit passivation layer (PVX) 8 forms via hole 9 by passivation layer mask (PVX Mask) and passivation layer etching (PVX Etch), shown in Figure 11 a and Figure 11 b;
At last, pixel deposition electrode (ITO) layer, form pixel electrode 10 and make pixel electrode 10 contact conducting by pixel electrode mask (ITO Mask) and pixel electrode etching (ITO Etch) with source electrode 7 by via hole, and finish the making of active driving TFT matrix construction, the final figure that forms is shown in Fig. 6 a and 6b.
Owing to formed grid electrode insulating layer via hole, data wire is deposited in this grid electrode insulating layer via hole, has increased the spacing between pixel electrode and the data wire, has effectively reduced parasitic capacitance between the two in the above-mentioned manufacture method.
In the above-mentioned manufacture method, the grid metal level that obtains of deposition may further be the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps is one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.The grid electrode insulating layer that obtains of deposition may further be the monofilm of SiNx, SiOx or SiOxNy or one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.Deposition obtains the source and leaks metal level and may further be the monofilm of Mo, MoW or Cr or one of Mo, MoW or Cr or composite membrane that combination in any constituted.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (10)
1, a kind of active driving TFT matrix construction is characterized in that, comprising:
One substrate;
One grid line and gate electrode are formed on the described substrate;
One grid electrode insulating layer is formed on described grid line and gate electrode and the substrate, and is formed with grid electrode insulating layer via hole between described adjacent grid line;
One data wire, a part are formed on the described grid electrode insulating layer, and another part is formed between the described adjacent grid line in the grid electrode insulating layer via hole, and and grid line intersect definition one pixel cell;
Wherein each pixel cell comprises at least with a film transistor device and a pixel electrode.
2, matrix structure according to claim 1 is characterized in that: described grid line comprises a grid line ledge, and described pixel electrode part is formed on the top of this grid line ledge, constitutes storage capacitance jointly with the grid line ledge.
3, matrix structure according to claim 1 and 2 is characterized in that: described grid line and gate electrode are the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
4, matrix structure according to claim 1 and 2 is characterized in that: described grid electrode insulating layer is the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted.
5, matrix structure according to claim 1 and 2 is characterized in that: described source-drain electrode is the monofilm of Mo, MoW or Cr, is perhaps constituted composite membrane by one of Mo, MoW or Cr or combination in any.
6, a kind of manufacture method of active driving TFT matrix construction is characterized in that, comprising:
Step 1, deposition grid metal level by mask and etching technics, forms grid line and gate electrode on substrate;
Step 2, deposition grid electrode insulating layer on the substrate of completing steps 1 is by mask and etching technics, at the lower portion formation grid electrode insulating layer via hole of follow-up formation data wire;
Step 3, depositing semiconductor layers and doping semiconductor layer on the substrate of completing steps 2 by mask and etching technics, form semiconductor active layer;
Step 4, sedimentary origin leaks metal level on the substrate of completing steps 3, by mask and etching technics, forms data wire and source-drain electrode, and wherein the data wire of grid electrode insulating layer top is embedded in the grid electrode insulating layer via hole;
Step 5, deposit passivation layer on the substrate of completing steps 4 by mask and etching technics, forms via hole and to the protection of raceway groove;
Step 6, pixel deposition electrode layer on the substrate of completing steps 5 by mask and etching technics, forms pixel electrode, and makes pixel electrode contact conducting with the source electrode by via hole.
7, manufacture method according to claim 6 is characterized in that: form the grid line ledge when described step a kind forms grid line, the pixel electrode part that step 6 forms is positioned at the top of grid line ledge, forms storage capacitance jointly.
8, according to claim 6 or 7 described manufacture methods, it is characterized in that: the grid metal level that obtains of deposition is the monofilm of AlNd, Al, Cu, Mo, MoW or Cr in the described step 1, perhaps is one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
9, according to claim 6 or 7 described manufacture methods, it is characterized in that: the grid electrode insulating layer that obtains of deposition is the monofilm of SiNx, SiOx or SiOxNy or one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted in the described step 2.
10, according to claim 6 or 7 described manufacture methods, it is characterized in that: deposition obtains the source and leaks monofilm that metal level is Mo, MoW or Cr or one of Mo, MoW or Cr or composite membrane that combination in any constituted in the described step 4.
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| CN200710119784XA CN101359670B (en) | 2007-07-31 | 2007-07-31 | Active driving TFT matrix construction and manufacturing method thereof |
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| CN101359670B (en) | 2011-08-17 |
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