CN101355361B - A High Speed Wide Range Multimode Programmable Frequency Divider with Duty Cycle Adjustment - Google Patents

Abstract

A high-speed wide-range multi-mode programmable frequency divider with duty cycle adjustment, including a main frequency division stage composed of cascaded 2/3 frequency division units and a series of OR gates for expanding the frequency division ratio range , also includes control stage and output stage circuits. The invention ensures the high-speed characteristics of the traditional 2/3 frequency division unit cascading, increases the pulse width of the output signal, and eliminates the influence of the input signal period on the output signal pulse width; only a small amount of AND gates and OR gates are added as The control stage and the output stage increase the duty cycle of the output signal, so that the duty cycle is controlled between 33.3%-66.6%. When the frequency division ratio is 2 ⁿ , the duty cycle is 50%; when the frequency division ratio is When 2 ⁿ -1, the duty cycle is closer to 50% with the increase of n; under a specific frequency division ratio, the duty cycle in the extreme case is 33.3% or 66.6%, compared with common high-speed Wide-range programmable frequency divider, the driving ability has been greatly improved.

Description

A High Speed Wide Range Multimode Programmable Frequency Divider with Duty Cycle Adjustment

technical field

The invention relates to the design of a frequency divider, in particular to the technical field of designing a high-speed and wide-range multi-mode programmable frequency divider, in particular to a high-speed and wide-range multi-mode programmable frequency divider with duty cycle adjustment.

Background technique

High-performance programmable frequency dividers are widely used in radio frequency and high-speed digital integrated circuits. High operating frequency, wide frequency division ratio range, low power consumption, large drive capacity, etc. are usually the general requirements of the system for frequency dividers. In July 2000, the article "A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology" published on pages 1039 to 1045 of IEEE "Journal of Solid-State Circuits" (JSSC), disclosed a high-speed low-power Programmable frequency divider circuit structure with wide frequency division ratio range. However, due to the circuit structure itself, the pulse width of the output signal is only 2 to 3 times the period of the input signal. If the frequency of the input signal is higher, the pulse width will be narrower and the driving ability will be weaker, which limits its application range.

In December 2007, the article "Efficient driving-capability programmable frequency divider with a wide division ratio range" on pages 485 to 493 of IET's "Devices, Circuits and Systems" improved the above circuit structure and obtained a duty cycle close to 50% of the output signal. However, this article uses a combination of two schemes to adjust the duty cycle, adding additional multi-bit half-adders and many gate circuits, which increases the complexity of the circuit and power consumption.

Contents of the invention

The technical problem to be solved by the present invention is: the pulse width of the output signal of the existing programmable frequency divider is affected by the operating frequency, the higher the operating frequency, the narrower the output pulse width, so as the frequency division ratio increases, the duty cycle Decreases sharply, driving capability is limited.

The technical solution of the present invention is: a high-speed wide-range multi-mode programmable frequency divider with duty ratio adjustment, including cascaded 2/3 frequency division units and a series of OR gates for expanding the frequency division ratio range The main frequency division stage formed is determined by the maximum value of the required frequency division ratio. The total number of 2/3 frequency division units n: 2 ⁿ ≤ the maximum frequency division ratio <2 ⁿ⁺¹ is determined by the minimum frequency division ratio. No need The number n' of 2/3 frequency division units connected forward in series with the OR gate: 2 ^n' ≤ the minimum frequency division ratio <2 ^n'+1 , also including the control stage and output stage circuits:

The control stage is composed of two-input AND gates of n-n'+1 level. The first input terminals of the AND gates at each level are connected to the mode control signal output terminal Mo corresponding to the 2/3 frequency division unit in the main frequency division stage. After the second input terminal is connected The setting terminal P of the first-level 2/3 frequency division unit;

The output stage is composed of nn'-level two-input OR gates, the two input ends of the first-stage OR gates are sequentially connected to the output ends of the first and second-level AND gates in the control stage, and the second and subsequent OR gates of the second and subsequent stages are connected to each other. One input terminal is connected to the output terminal of the AND gate of the corresponding stage in the control stage, and the second input terminal is connected to the output terminal of the OR gate of the previous stage; the output of the two-input OR gate of the last stage is the final output f _out of the frequency divider.

The further improvement of the present invention is: the main frequency division stage is connected in series with an improved 2/3 frequency division unit from the n'-1th level, and the improved 2/3 frequency division unit includes three two-input AND gates, four Level D latch, a trigger signal input terminal Fin, a mode control signal input terminal Mi, a set number terminal P, a trigger signal output terminal Fo, and a mode control signal output terminal Mo, the output trigger signal Fo is from the first The Q terminal of the first-level D latch is drawn out, so that compared with the existing traditional 2/3 frequency division unit, the output trigger signal has changed, so that the triggered 2/3 frequency division unit mode of the latter stage controls the output signal Mo The pulse width can change with the change of the frequency division ratio.

In the present invention, the control stage is preferably connected to the main frequency division stage from the n'th 2/3 frequency division unit of the main frequency division stage.

In the present invention, the design of the main frequency division stage makes the high-level width of the Mo signal of the 2/3 frequency division unit from the n' level and the following stages change with the frequency division ratio, so as to avoid the division caused by the constant pulse width. When the frequency ratio is increased, the duty cycle is severely reduced; the control circuit is used to shield the Mo signal of the invalid 2/3 frequency division unit; the output stage is to take out the Mo signal pulse from the 2/3 frequency division unit in normal operation The level with the widest width takes its Mo signal as the output signal, thus increasing and stabilizing the duty cycle of the output signal.

The high-speed and wide-range multi-mode programmable frequency divider with duty cycle adjustment of the present invention adopts two 2/3 frequency division units with different structures, which ensures the high-speed characteristics of the traditional 2/3 frequency division unit cascading, and The pulse width of the output signal is increased, and the influence of the period of the input signal on the pulse width of the output signal is eliminated. Only a small amount of AND gates and OR gates are added as the control stage and output stage, and the duty ratio of the output signal is increased, so that the duty ratio is controlled between 33.3%-66.6%, and the driving ability of the frequency divider is greatly improved. When the frequency division ratio is 2 ⁿ , the duty cycle is 50%; when the frequency division ratio is 2 ⁿ -1, the duty cycle approaches 50% as n increases; under a specific frequency division ratio, The duty cycle at the limit is 33.3% or 66.6%, and the driving capability is greatly improved compared with common high-speed wide-range programmable frequency dividers.

Description of drawings

Figure 1 is a common arbitrary programmable frequency divider with high speed, low power consumption and wide range.

Figure 2(a) is a traditional 2/3 frequency division unit.

Fig. 2(b) is a 2/3 frequency division unit in the present invention.

Figure 3(a) is the simulation waveform of three traditional 2/3 frequency division units cascaded.

Fig. 3(b) is a simulation waveform after three 2/3 frequency division units of the present invention are cascaded.

FIG. 4 is a high-speed and wide-range multi-mode programmable frequency divider with duty cycle adjustment of the present invention.

Figure 5 shows the output waveform of a common high-speed, low-power, wide-range arbitrary programmable frequency divider.

FIG. 6 is the output waveform of the high-speed and wide-range multi-mode programmable frequency divider with duty cycle adjustment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The high-speed and wide-range programmable frequency divider in the prior art is cascaded with traditional 2/3 frequency division units, and the mode control output signal Mo only needs to be fed forward step by step, so it has a strong speed advantage. Connect the OR gate network and add a digital terminal to expand the range of the frequency division ratio, making it an arbitrary programmable frequency divider, as shown in Figure 1, determine the 2/3 frequency division unit according to the maximum value of the required frequency division ratio The total number n: 2 ⁿ ≤ the maximum frequency division ratio <2 ⁿ⁺¹ , and then determine the number n′ of 2/3 frequency division units that do not need to be connected in series with the forward OR gate according to the minimum frequency division ratio: 2 ^n′ ≤ minimum Frequency division ratio <2 ^n'+1 , each 2/3 frequency division unit is connected in series, only the mode control signal input terminal Mi of the first n'-1 level 2/3 frequency division unit is directly connected to the latter level of frequency division unit The mode control signal output terminal Mo, and one or two input OR gates are connected in series between the other units, the first input terminal of the OR gate is connected to the mode control signal output terminal Mo of the next-level unit, and the second input terminal is connected to each digital terminal signal through The inverse signal of the corresponding signal after the logic gate network, the output of the OR gate is connected to the mode control signal input terminal Mi of the previous 2/3 frequency division unit, and the mode control signal input terminal Mi of the last 2/3 frequency division unit is externally connected to Mode control signal; in addition, the OR gate network connected in series between the stages is: from the last stage 2/3 frequency division unit, the OR gate is connected in series forward, and the first input terminal of the first stage OR gate is connected to the last stage 2/3 The setting terminal P _n-1 of the frequency division unit, the second input terminal is connected to the external control terminal P _n , the output terminal of the OR gate is connected to the second input terminal of the subsequent OR gate, and the inverse signal connection corresponds to 2/3 division The second input end of the two-input OR gate connected in series between the frequency units, the first input end of the two-input OR gate of each level of the remaining OR gate network is connected to the set number terminal P of the corresponding 2/3 frequency division unit, or the gate network The output end of the last stage two-input OR gate is only connected to the second input end of the two-input OR gate connected in series between the corresponding 2/3 frequency division units. This structure has been widely used due to its advantages of high speed, low power consumption and convenient layout design. However, due to the requirement of a wide range of frequency division ratio, the output signal f _out can only be drawn from the second or third stage mode control signal output terminal Mo, and in this case the output pulse width is narrow, so the driving capability is limited. It does not work well with large capacitive loads. In order to broaden its application range, it is urgent to increase the duty cycle of its output signal.

Fig. 2(a) is a schematic diagram of a conventional 2/3 frequency division unit, and Fig. 2(b) is a schematic diagram of an improved 2/3 frequency division unit in the present invention. Both the traditional 2/3 frequency division unit 30 and the improved 2/3 frequency division unit 20 have a trigger signal input terminal Fin, a mode control signal input terminal Mi, a set number terminal P, a trigger signal output terminal Fo, and a The mode control signal output terminal Mo, the trigger signal output terminal Fo are connected to the trigger signal input terminal Fin of the subsequent frequency division unit, and the number terminal P is used to receive the divisor signal to select the frequency division unit for division by 2 or division by 3. mode, the trigger signal input terminal Fin of the first stage 2/3 frequency division unit is connected to the source pulse. The trigger signal output terminal Fo of the conventional 2/3 frequency division unit 30 is derived from the Q terminal of the second-stage D flip-flop 31 . The improved 2/3 frequency division unit 20 in the present invention is similar to the traditional 2/3 frequency division unit 30, including: three two-input AND gates, four-stage D latches, three input terminals and two output terminals, They are the trigger signal input terminal Fin 21, the mode control signal input terminal Mi 23, the number setting terminal P 25, the trigger signal output terminal Fo 22, and the mode control signal output terminal Mo 24, but the trigger signal output terminal Fo 22 is from the first The Q end of the stage D latch 26 is drawn, and then used as the input trigger signal of the 2/3 frequency division unit of the next stage, so that the pulse width of the triggered 2/3 frequency division unit mode control output signal Mo of the latter stage follows the division Varies with changes in the frequency ratio. The output signal of the frequency divider is related to the mode control output signal Mo signal of the 2/3 frequency division unit, thus directly improving the pulse width of the output signal, thereby achieving the purpose of increasing the duty cycle of the output signal.

Fig. 3(a) is a simulation waveform diagram of a frequency divider composed of three traditional 2/3 frequency division units, and Fig. 3(b) is a simulation result after cascading the improved 2/3 frequency division units of the present invention. From Figure 3(a), it is not difficult to find that the result of cascading traditional 2/3 frequency division units is that the mode control of the Nth-stage 2/3 frequency division unit that provides the output signal f _out has a pulse width of the output signal Mo that is the period of the input signal 2 ^N-1 times, and in the prior art, in order to meet the requirements of the large frequency division ratio range, only one of the 2/3 frequency division unit Mo signals in the previous stages can be selected as the output signal f _out , so that the N value is small , resulting in a very narrow pulse width of the output signal f _out , and if the operating frequency of the frequency divider is higher and the input signal period is shorter, the output signal pulse width will be narrower, which severely limits its driving capability. It can be seen from Figure 3(b) that the pulse width of the mode control output signal Mo of the improved 2/3 frequency division units at all levels is related to the specific frequency division ratio. Assuming that there are n levels of 2/3 frequency division units working normally, Then there is the following formula:

The pulse width of the nth level Mo signal=(p ₀ +p ₁ *2 ¹ +p ₂ *2 ² +…+p _n-2 *2 ^n-2 +2 ^n-1 )*T _in so the output signal can be obtained The empty ratio is:

$\frac{{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="p"\; filenames="H2008101570948E00011.png,H2008101570948E00032.png"\; state="\{\{state\}\}">p</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="p"\; filenames="H2008101570948E00011.png,H2008101570948E00032.png"\; state="\{\{state\}\}">p</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="p"\; filenames="H2008101570948E00011.png,H2008101570948E00032.png"\; state="\{\{state\}\}">p</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="p"\; filenames="H2008101570948E00011.png,H2008101570948E00032.png"\; state="\{\{state\}\}">p</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; p</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}}$

According to the above two formulas, the pulse width and duty cycle of the Mo signal under any frequency division ratio can be calculated. Considering the limit situation, it can be known that the duty cycle is controlled at 33.3% to 66.6%. The following is to consider how to extract the mode control output signal Mo of the last stage, that is, the nth stage 2/3 frequency division unit (its pulse width is the widest), as the output signal of the frequency divider.

FIG. 4 is a schematic diagram of a high-speed wide-range multi-mode programmable frequency divider circuit with duty ratio adjustment according to the present invention, which includes a main frequency division stage 10, a control stage 11 and an output stage 12. The structure of the main frequency division stage 10 is a common high-speed multi-mode programmable frequency divider structure, but as an improvement, some of the 2/3 frequency division units adopt the improved structure designed by the present invention. When the improved 2/3 frequency division unit 20 is connected in series, the maximum delay time allowed by the Mo signal feedforward is slightly smaller than the original structure, so the traditional 2/3 frequency division unit 30 is still used in the previous stages of 2/3 frequency division units. According to the n' determined by the minimum frequency division ratio, it can be seen that the improved 2/3 frequency division unit 20 of the present invention is most suitable for the n'-1th stage. The control stage 11 is composed of multi-level AND gates, which are nn'+1 levels in total. Compared with the main frequency division level 10, the number of OR gate stages connected in series is one more, and the first input terminals of the AND gates at all levels are connected to correspond to 2/ The mode control signal output terminal Mo of the 3 frequency division unit 20, the second input terminal is connected to the number terminal P of the rear stage 2/3 frequency division unit, that is to say only when the signal of the number terminal signal of the latter stage is high, the current stage The Mo signal is gated. According to the working principle of the main frequency division level 10, if P _n-2 is the last bit that is set high, then all 2/3 frequency division units from the n-2th level and forward work normally, and its backward Unit: Although the n-1st and nth 2/3 frequency division units work, the output signal is invalid. Since the signals of the digital terminals of their subsequent stages are all low at this time, they pass through the AND gate of the control stage 11. , their output signals will be shielded. In all normal working 2/3 frequency division units, the mode control output signal Mo of each level is the same frequency, that is, the target frequency. It can be seen from Figure 3(b) that as the number of stages increases, the Mo signal The pulse width also increases, so the 2/3 frequency division unit that works normally in the last stage has the largest pulse width, and of course it becomes the best choice for the output signal f _out . How to select the signal we want, the design of the output stage 12 solves this problem. Although the output stage 12 is formed by multi-stage two-input OR gate cascaded, its overall function is still to carry out OR logic to the outputs of all levels of AND gates in the control stage 11, which is equivalent to the effect of a multi-input OR gate, only from the design From the perspective of convenience, two-input OR gates are cascaded. From Figure 3(b), it can be found that not only the higher the number of stages, the wider the pulse width of the Mo signal, but also the pulses of the latter stage completely cover the pulses of the current stage. Based on this characteristic, the outputs of the AND gates of the control stage 11 pass through After the output stage 12 or the logic, the pulse signal Mo of the 2/3 frequency division unit in the last stage of normal operation is obtained, which is used as the final output f _out 13 of the frequency divider, which is the working principle of the present invention.

The main frequency division stage of the present invention can all adopt the traditional 2/3 frequency division unit, and can also all adopt the improved 2/3 frequency division unit. If the traditional 2/3 unit is simply used, the output signal duty cycle can be increased to 25 %~50%; if the improved unit structure is adopted, the allowable maximum delay value is slightly smaller than the traditional structure, but this effect will only occur at very high speed (that is, the trigger signal period is very small) Influence. Since in the circuit structure, the higher the front 2/3 frequency division unit, the higher the working speed, so it should be given a slightly larger delay range; in addition, from the n'-1 level and forward 2/3 frequency division unit, their Mo signal is not needed, so it is not necessary to replace it with an improved structure, which also helps to maintain the advantages of high speed, and it is also the main frequency division stage selected by the present invention to adopt the improved 2/ The reason for the series connection of 3 frequency division units.

FIG. 5 is the output waveform of a common high-speed, low-power, wide-range, arbitrary programmable frequency divider, and FIG. 6 is the output waveform of the high-speed, wide-range, multi-mode programmable frequency divider with duty cycle adjustment of the present invention. It can be seen from the figure that the duty cycle of the output signal of the frequency divider of the present invention is far greater than that of the output signal of the original structure, and the technical effect is obvious.

In summary, the present invention has the following technical features: (1) simple circuit structure: only a row of AND gates and OR gates are added on the basis of the original structure; (2) low power consumption: the added gate circuits all work at the output The signal frequency, that is, the lowest frequency, hardly increases the power consumption; (3) the effect is remarkable: the duty cycle can be well controlled between 33.3% and 66.6%, and the driving ability of the frequency divider is enhanced.

The manufacture of the high-speed and wide-range multi-mode programmable frequency divider circuit with duty ratio adjustment of the present invention can be realized through the CMOS process of the prior art.

Claims (3)

1. A high-speed wide-range multi-mode programmable frequency divider with duty ratio adjustment, including a main divider composed of cascaded 2/3 frequency division units and a series of OR gates for expanding the frequency division ratio range Frequency level (10), determined by the maximum value of the required frequency division ratio. The total number of 2/3 frequency division units n: 2 ⁿ ≤ the maximum frequency division ratio <2 ⁿ⁺¹ , determined by the minimum frequency division ratio, no need to go forward The number n′ of 2/3 frequency division units connected in series or gates: 2 ⁿ ′≤minimum frequency division ratio<2 ⁿ ′ ⁺¹ , is characterized in that it also includes a control stage (11) and an output stage (12) circuit: The control stage (11) is made up of n-n'+1 level two-input AND gates, and the first input terminals of each level of AND gates are connected to the mode control signal output terminal Mo corresponding to the 2/3 frequency division unit in the main frequency division stage (10), The second input terminal is connected to the setting terminal P of the second-stage 2/3 frequency division unit; Output stage (12) is made up of two input OR gates of nn ' level, and two input ends of its first stage OR gate are connected successively with the output ends of the first and second AND gates in the control stage (11), the second stage and the rear The first input end of each OR gate of each stage is connected to the AND gate output end of the corresponding stage in the control stage (11), and the second input end is connected to the output end of the OR gate of the previous stage; the output of the two-input OR gate of the last stage is the dividing The frequency converter's final output f _out (13). 2. A kind of high-speed wide-range multi-mode programmable frequency divider with duty cycle adjustment according to claim 1, characterized in that the main frequency division stage (10) adopts the improved 2 from the n'-1th stage. /3 frequency division unit (30) is connected in series, and described improved 2/3 frequency division unit (30) comprises three two-input AND gates, four-level D latch, a trigger signal input terminal Fin (21), a Mode control signal input terminal Mi (23), a set number terminal P (25), a trigger signal output terminal Fo (22), and a mode control signal output terminal Mo (24), its trigger signal output terminal Fo (22) Draw from the non-inverting output end of the first stage D latch (26), so that starting from the n'th stage 2/3 frequency division unit, the pulse width of the mode control signal output end Mo (24) follows the variation of the frequency division ratio And change. 3. A kind of high-speed wide-range multi-mode programmable frequency divider with duty cycle adjustment according to claim 1 or 2, characterized in that the control stage (11) is from the n'th' of the main frequency division stage (10) The stage 2/3 divider unit starts to connect with the main divider stage (10).

Images