CN101351088A - Embedded circuit structure and process thereof - Google Patents

Abstract

A process for an embedded circuit structure. At least one through hole is formed on a core board, which penetrates the core board itself. A first recessed pattern and a second recessed pattern are formed on a first surface of the core board and a second surface relative to the first surface, respectively. A conductive material is electroplated to the through hole, the first recessed pattern and the second recessed pattern to form a conductive path in the through hole, and a first circuit pattern is formed in the first recessed pattern, which partially exceeds the first recessed pattern, and a second circuit pattern is formed in the second recessed pattern, which partially exceeds the second recessed pattern. The first circuit pattern partially exceeding the first recessed pattern is removed to flatten the first circuit pattern to the first surface of the core board, and the second circuit pattern partially exceeding the second recessed pattern is removed to flatten the second circuit pattern to the second surface of the core board.

Description

Embedded circuit structure and its technology

technical field

The present invention relates to a circuit structure and its technology, and in particular to an embedded circuit structure and its technology.

Background technique

As the number of contacts and the contact density of integrated circuit chips increase, the contact density and wiring density of the circuit carrier used to package the chips must also match accordingly. In addition to the circuit carrier used for chip packaging, with the miniaturization and thinning of electronic products, the circuit carrier used in the motherboard of electronic products is also gradually developing towards a trend of high wiring density. Therefore, the demand for circuit substrates with high wiring density is gradually increasing.

The current manufacturing methods of circuit substrates generally include laminating process and build-up process.

In the lamination method, after the patterned circuit layer on the surface of the dielectric layer is completed, the required patterned circuit layer and dielectric layer are laminated to form a laminated structure, and then plated through holes are performed. hole, that is, PTH) step to connect patterned circuit layers located at two different levels. The build-up method is to sequentially form patterned circuit layers on a substrate, and make conductive vias connecting the previous layer of patterned circuit layers together during the process of sequentially fabricating the patterned circuit layers.

U.S. Patent No. 5,504,992 discloses a "circuit board process", which forms a photoresist pattern on a thin metal layer on one side of a metal sheet, and then uses the thin metal layer as an electroplating seed layer on the remaining surface of the thin metal layer. A circuit pattern is formed on the portion covered by the photoresist pattern, and then the photoresist pattern is removed. Next, after embedding the above two circuit patterns on both sides of the same dielectric layer to form a stacked structure, and forming a through hole in the stacked structure, electroplating conductive material to the inner wall of the through hole to form a conductive path To connect the above two line patterns. Finally, the metal sheets and the thin metal layers are removed, leaving the dielectric layer, the wiring patterns on both sides of the buried dielectric layer, and the conductive paths connecting the wiring patterns. It is worth noting that the thin metal layer used as the electroplating seed layer in the above-mentioned US patent will be removed after the process is completed and will not remain between the circuit pattern and the dielectric layer.

Contents of the invention

The invention provides an embedded circuit structure process, which is used to relatively improve the positioning accuracy between these circuit patterns.

The invention provides an embedded circuit structure, which can relatively improve the positioning accuracy between these circuit patterns in the process.

The invention proposes an embedded circuit structure technology. A core board is provided. At least one through hole is formed on the core board, which runs through the core board itself. A first concave pattern is formed on the first surface of the core board. A second concave pattern is formed on a second surface of the core board opposite to the first surface. Electroplating conductive material to the through hole, the first recessed pattern and the second recessed pattern to form a conductive channel in the through hole, and form a first line pattern in the first recessed pattern, which partially exceeds the first recessed pattern, and A second circuit pattern is formed in the second concave pattern, which partially exceeds the second concave pattern, wherein the electroplating includes electroless electroplating and then electrolytic electroplating. removing the first circuit pattern partially beyond the first recessed pattern to planarize the first circuit pattern to the first surface of the core board, and removing the second circuit pattern partially exceeding the second recessed pattern to planarize the second circuit pattern to the second side of the core board.

In an embodiment of the present invention, the step of forming the through hole may include mechanical processing or laser processing.

In an embodiment of the present invention, the step of forming the first concave pattern and the second concave pattern may include laser processing.

In an embodiment of the present invention, the step of removing the partial first circuit pattern and the partial second circuit pattern may include etching or grinding.

In an embodiment of the invention, the conductive channel may have a tubular space.

In an embodiment of the present invention, the process may further include filling the plug material into the tubular space of the conductive channel.

In an embodiment of the present invention, the process may further include removing the partially protruding plug posts to planarize the two ends of the plug posts to the first surface and the second surface of the core board respectively.

The invention proposes an embedded circuit structure, which includes a core board, a first circuit pattern, a second circuit pattern, a conductive channel and a plurality of electroplating seed layers. The core board has a first surface and a second surface opposite to it. The first circuit pattern is embedded in the first surface of the core board. The second circuit pattern is embedded in the second surface of the core board. The conductive channel runs through the core board, and the two ends of the conductive channel are respectively connected to the first circuit pattern and the second circuit pattern. These electroplating seed layers are respectively located between the core board and the first circuit pattern, between the core board and the second circuit pattern, and between the core board and the conductive channel.

In an embodiment of the present invention, the structure may further include a plug post filled in a tubular space of the conductive channel.

The invention proposes an embedded circuit structure technology. A core board is provided having a first side and a second side opposite thereto. At least one through hole is formed on the core board, which runs through the core board itself. The conductive material is electroplated to the through hole to form a conductive channel in the through hole, wherein the conductive channel has a tubular space. The plug material is filled into the tubular space of the conductive channel to form the plug post. The plug hole posts partially protruding from the first surface and the second surface of the core board are removed so as to planarize the two ends of the plug hole posts to the first side and the second side of the core board respectively. A first concave pattern is formed on the first surface of the core board. A second concave pattern is formed on the second surface of the core board. Electroplating a conductive material to the first and second recessed patterns to form a first circuit pattern in the first recessed pattern partially beyond the first recessed pattern, and to form a second circuit pattern in the second recessed pattern Partially beyond the second concave pattern, wherein the electroplating includes electroless electroplating followed by electrolytic electroplating. removing the first circuit pattern partially beyond the first recessed pattern to planarize the first circuit pattern to the first surface of the core board, and removing the second circuit pattern partially exceeding the second recessed pattern to planarize the second circuit pattern to the second side of the core board.

In an embodiment of the present invention, the step of forming the through hole includes mechanical processing or laser processing.

In an embodiment of the invention, the step of forming the first concave pattern and the second concave pattern includes laser processing.

In an embodiment of the present invention, the step of removing the partial first circuit pattern and the partial second circuit pattern includes etching or grinding.

The present invention proposes an embedded circuit structure, which includes a core board, a first circuit pattern, a second circuit pattern, a conductive channel, a first electroplating seed layer, a plurality of second electroplating seed layers, and plug holes. The core board has a first surface and a second surface opposite to it. The first circuit pattern is embedded in the first surface of the core board. The second circuit pattern is embedded in the second surface of the core board. The conductive channel runs through the core board, and the two ends of the conductive channel are respectively connected to the first circuit pattern and the second circuit pattern. The first electroplating seed layer is located between the core board and the conductive channels. These second electroplating seed layers are respectively located between the core board and the first circuit pattern and between the core board and the second circuit pattern. The plug column is filled in a tubular space of the conductive channel.

In an embodiment of the present invention, the first electroplating seed layer is further located between the second electroplating seed layers and the conductive channels.

In the present invention, since the recessed patterns on both sides of the core board can directly define the positions of the circuit patterns, the positioning accuracy of the circuit patterns can be relatively improved.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, a number of embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1D illustrate a buried circuit structure process according to an embodiment of the present invention.

FIG. 2A to FIG. 2E illustrate the buried wiring structure process according to another embodiment of the present invention.

FIG. 3A to FIG. 3H illustrate the buried circuit structure process according to another embodiment of the present invention.

Description of main component symbols

100: core board

100a: first side

100b: second side

102: through hole

104: First Debossed Pattern

106: Second concave pattern

108: Conductive channel

108a: Tubular spaces

110: The first line pattern

112: Second line pattern

114: Plating seed layer

116: plug hole column

200: core board

200a: first side

200b: second side

202: through hole

204: conductive channel

204a: Tubular space

206: First electroplating seed layer

206': Part of the first plating seed layer

207: Plating layer

207': Part of the electroplating layer

208: plug hole column

210: First Debossed Pattern

212: Second concave pattern

214: First line pattern

216: Second line pattern

218: Second electroplating seed layer

Detailed ways

FIG. 1A to FIG. 1D illustrate a buried circuit structure process according to an embodiment of the present invention.

Referring to FIG. 1A , a core board 100 is provided. In this embodiment, the core board 100 is a dielectric board.

Referring to FIG. 1B , at least one through hole 102 is formed on the core board 100 , which runs through the core board 100 itself, wherein the step of forming the through hole 102 may include machining or laser processing. In addition, a first concave pattern 104 is further formed on a first surface 100 a of the core board 100 , wherein the step of forming the first concave pattern 104 may include laser processing. In addition, a second concave pattern 106 is formed on a second surface 100 b opposite to the first surface 100 a of the core board 100 , wherein the step of forming the second concave pattern 106 may include laser processing.

Please refer to FIG. 1C , electroplating conductive material to the through hole 102 , the first recessed pattern 104 and the second recessed pattern 106 to form a conductive channel 108 in the through hole 102 and form a first line in the first recessed pattern 104 The pattern 110 partially exceeds the first concave pattern 104 , and forms a second line pattern 112 in the second concave pattern 106 , and partially exceeds the second concave pattern 106 .

In this embodiment, the conductive material will fill the through hole 102 to form a solid conductive channel 108 . Therefore, the conductive channel 108 runs through the core board, and the two ends of the conductive channel 108 are respectively connected to the first circuit pattern 110 and the second circuit pattern 112 . In addition, the first circuit pattern 110 is embedded in the first surface 100 a of the core board 100 , and the second circuit pattern 112 is embedded in the second surface 100 b of the core board 100 .

In this embodiment, the electroplating includes electroless plating to form the electroplating seed layer 114 , and then electrolytic plating to form the conductive channel 108 , the first circuit pattern 110 and the second circuit pattern 112 . Therefore, the conductive channel 108 runs through the core board 100 , and the two ends of the conductive channel 108 are respectively connected to the first circuit pattern 110 and the second circuit pattern 112 . In addition, the first circuit pattern 110 is embedded in the first surface 100 a of the core board 100 , and the second circuit pattern 112 is embedded in the second surface 100 b of the core board 100 .

Please refer to FIG. 1D, remove the first line pattern 110 that partially exceeds the first recessed pattern 104 to planarize the first line pattern 110 to the first surface 100a of the core board 100, and remove the portion that exceeds the second recessed pattern 106. The second circuit pattern 112 is used to planarize the second circuit pattern 112 to the second surface 100 b of the core board 100 . In this embodiment, the step of removing the part of the first circuit pattern 110 and the part of the second circuit pattern 112 may include etching or grinding.

FIG. 2A to FIG. 2E illustrate the buried wiring structure process according to another embodiment of the present invention.

Referring to FIG. 2A , a core board 100 is provided. In this embodiment, the core board 100 is a dielectric board.

Referring to FIG. 2B , at least one through hole 102 is formed on the core board 100 , which runs through the core board 100 itself, wherein the step of forming the through hole 102 may include machining or laser processing. In addition, a first concave pattern 104 is further formed on a first surface 100 a of the core board 100 , wherein the step of forming the first concave pattern 104 may include laser processing. In addition, a second concave pattern 106 is formed on a second surface 100 b opposite to the first surface 100 a of the core board 100 , wherein the step of forming the second concave pattern 106 may include laser processing.

Please refer to FIG. 2C , electroplating conductive material to the through hole 102 , the first recessed pattern 104 and the second recessed pattern 106 to form a conductive channel 108 in the through hole 102 and form a first line in the first recessed pattern 104 The pattern 110 partially exceeds the first concave pattern 104 , and forms a second line pattern 112 in the second concave pattern 106 , and partially exceeds the second concave pattern 106 . In this embodiment, the conductive material does not fill the through hole 102 . The conductive channel 108 has a tubular space 108a.

In this embodiment, the electroplating includes electroless plating to form the electroplating seed layer 114 , and then electrolytic plating to form the conductive channel 108 , the first circuit pattern 110 and the second circuit pattern 112 . Therefore, the conductive channel 108 runs through the core board 100 , and the two ends of the conductive channel 108 are respectively connected to the first circuit pattern 110 and the second circuit pattern 112 . In addition, the first circuit pattern 110 is embedded in the first surface 100 a of the core board 100 , and the second circuit pattern 112 is embedded in the second surface 100 b of the core board 100 .

Referring to FIG. 2D , the plug material is filled into the tubular space 108 a of the conductive channel 108 to form a plug post 116 .

Please refer to FIG. 2E , remove the first line pattern 110 that partially exceeds the first recessed pattern 104 to planarize the first line pattern 110 to the first surface 100a of the core board 100, and remove the portion that exceeds the second recessed pattern 106. The second circuit pattern 112 is used to planarize the second circuit pattern 112 to the second surface 100 b of the core board 100 . In this embodiment, the step of removing the part of the first circuit pattern 110 and the part of the second circuit pattern 112 may include etching or grinding. In this embodiment, it further includes removing the partially protruding plug hole post 116 to planarize the two ends of the plug hole post 116 to the first surface 100 a and the second surface 100 b of the core board 100 .

FIG. 3A to FIG. 3G illustrate the embedded circuit structure process according to another embodiment of the present invention.

Referring to FIG. 3A , a core board 200 is provided. In this embodiment, the core board 200 is a dielectric board.

Referring to FIG. 3B , at least one through hole 202 is formed on the core board 200 , which runs through the core board 200 itself, wherein the step of forming the through hole 202 may include machining or laser processing.

Referring to FIG. 3C , electroplating conductive material to the through hole 202 to form a conductive channel 204 in the through hole 202 , wherein the conductive channel 204 has a tubular space 204 a. In this embodiment, since the conductive channel 204 is formed by electroplating, a first electroplating seed layer 206 is first formed between the inner wall of the through hole 202 and the conductive channel 204, and the electroplating layer 207 is also formed on the core board 200. On the first surface 200a and the second surface 200b. Therefore, the portion 206' of the first electroplating seed layer 206 located in the through hole 202 and the portion 207' of the electroplating layer 207 located in the through hole 202 form the conductive channel 204.

Referring to FIG. 3D , the plug material is filled into the tubular space 204 a of the conductive channel 204 to form a plug post 208 .

Please refer to FIG. 3E , remove the plug holes 208 partially protruding from the first surface 200a and the second surface 200b of the core board 200, so as to planarize the two ends of the plug holes 208 to the first surface 200a of the core board 200 respectively. and the second side 200b. In this embodiment, the part of the first electroplating seed layer 206 on the first surface 200a and the part of the electroplating layer 207 on the second surface 200b are further removed.

Referring to FIG. 3F , a first concave pattern 210 is formed on the first surface 200 a of the core board 200 , wherein the step of forming the first concave pattern 210 may include laser processing. In addition, a second concave pattern 212 is further formed on the second surface 200 b of the core board 200 , wherein the step of forming the second concave pattern 212 may include laser processing.

Please refer to FIG. 3G, electroplating conductive material to the first recessed pattern 210 and the second recessed pattern 212 to form a first line pattern 214 in the first recessed pattern 210, which partially exceeds the first recessed pattern 210, and in the first recessed pattern 210. A second line pattern 216 is formed in the second concave pattern 212 , and partially exceeds the second concave pattern 212 .

In this embodiment, the electroplating includes first electroless plating conductive material to form two second electroplating seed layers 218 on the first surface 100a and the second surface 200b of the core board 200 respectively, and then electrolytically electroplating the conductive material to form two second electroplating seed layers 218 respectively. A first circuit pattern 214 and a second circuit pattern 216 are formed on the layer 218 . Therefore, the first circuit pattern 214 is embedded in the first surface 200a of the core board 200, and the second circuit pattern 216 is embedded in the second surface 200b of the core board 200, and the two ends of the conductive channel 204 are connected to the first circuit pattern 214 and the first circuit pattern 214 respectively. The second line pattern 216 .

Please refer to FIG. 3H , remove the first line pattern 214 that partially exceeds the first recessed pattern 210 to planarize the first line pattern 214 to the first surface 200a of the core board 200, and remove the portion that exceeds the second recessed pattern 212. The second circuit pattern 216 is used to planarize the second circuit pattern 214 to the second surface 200 b of the core board 200 .

In this embodiment, the second electroplating seed layer 218 partially beyond the first concave pattern 210 will also be removed to planarize the second electroplating seed layer 218 to the first surface 200a of the core board 200, and partially beyond the second The second electroplating seed layer 218 of the concave pattern 212 is also removed to planarize the second electroplating seed layer 218 to the second surface 200 b of the core board 200 .

In this embodiment, the step of removing the partial first circuit pattern 214 and the partial second circuit pattern 216 may include etching or grinding. Likewise, the step of removing the partial second electroplating seed layer 218 may also include etching or grinding.

US Patent No. 5,504,992 discloses that the thin metal layer used as the plating seed layer is removed after the process is completed and does not remain between the circuit pattern and the dielectric layer. However, compared with US Patent No. 5,504,992, the electroplating seed layer produced in the process of the present invention will be located between the two circuit patterns and the core board.

To sum up, in the present invention, after the two concave patterns are respectively formed on both sides of the core board, conductive materials are filled into these concave patterns by electroplating to form circuit patterns embedded in the core board, thus producing an embedded circuit structure, which can be used as a circuit board or a part of a circuit board. In addition, one or more conductive channels connecting two circuit patterns on different levels can be formed before or at the same time as the circuit patterns are formed.

It is worth noting that since the recessed patterns on both sides of the core board can directly define the positions of the circuit patterns, the positioning accuracy between the circuit patterns can be relatively improved.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. An embedded circuit structure process, comprising: Provide the core board; forming at least one through hole on the core board, which runs through the core board itself; forming a first concave pattern on the first surface of the core board; forming a second concave pattern on a second surface of the core board opposite to the first surface; Electroplating conductive material to the through hole, the first recessed pattern and the second recessed pattern to form a conductive channel in the through hole, and form a first circuit pattern in the first recessed pattern, which partially exceeds the second A concave pattern, and a second circuit pattern is formed in the second concave pattern, which partially exceeds the second concave pattern, wherein the electroplating includes electroless plating followed by electrolytic plating; and removing the first circuit pattern partially beyond the first recessed pattern to planarize the first circuit pattern to the first surface of the core board, and removing the second circuit pattern partially exceeding the second recessed pattern , to planarize the second circuit pattern to the second surface of the core board. 2. The embedded circuit structure process as claimed in claim 1, wherein the conductive channel has a tubular space. 3. The embedded circuit structure process as claimed in claim 1, further comprising: Plugging material is filled into the tubular space of the conductive channel. 4. The embedded circuit structure process as claimed in claim 1, further comprising: The partially protruding plug hole post is removed to planarize the two ends of the plug hole post to the first surface and the second surface of the core board respectively. 5. An embedded circuit structure, comprising: a core board having a first surface and a second surface opposite thereto; a first circuit pattern embedded in the first surface of the core board; a second circuit pattern embedded in the second surface of the core board; A conductive channel runs through the core board, and the two ends of the conductive channel are respectively connected to the first circuit pattern and the second circuit pattern; and A plurality of electroplating seed layers are respectively located between the core board and the first circuit pattern, between the core board and the second circuit pattern, and between the core board and the conductive channel. 6. The embedded circuit structure according to claim 5, further comprising: The plug column is filled in the tubular space of the conductive channel. 7. An embedded circuit structure process, comprising: providing a core board having a first side and a second side opposite thereto; forming at least one through hole on the core board, which runs through the core board itself; electroplating a conductive material to the through hole to form a conductive channel within the through hole, wherein the conductive channel has a tubular space; filling a plug material into the tubular space of the conductive channel to form a plug post; removing the plug hole posts partially protruding from the first face and the second face of the core board to planarize the two ends of the plug hole posts to the first face and the second face of the core board, respectively ; forming a first concave pattern on the first surface of the core board; forming a second concave pattern on the second surface of the core board; Electroplating a conductive material to the first and second recessed patterns to form a first circuit pattern in the first recessed pattern, which partially exceeds the first recessed pattern, and forms a second line pattern in the second recessed pattern. Two line patterns partially protruding from the second recessed pattern, wherein electroplating includes electroless plating followed by electrolytic plating; and removing the first circuit pattern partially beyond the first recessed pattern to planarize the first circuit pattern to the first surface of the core board, and removing the second circuit pattern partially exceeding the second recessed pattern , to planarize the second circuit pattern to the second surface of the core board. 8 . The embedded circuit structure process as claimed in claim 7 , wherein the step of removing part of the first circuit pattern and part of the second circuit pattern comprises etching or grinding. 9. An embedded circuit structure, comprising: a core board having a first surface and a second surface opposite thereto; a first circuit pattern embedded in the first surface of the core board; a second circuit pattern embedded in the second surface of the core board; A conductive channel runs through the core board, and the two ends of the conductive channel are respectively connected to the first circuit pattern and the second circuit pattern; a first electroplating seed layer located between the core board and the conductive path; A plurality of second electroplating seed layers are respectively located between the core board and the first circuit pattern and between the core board and the second circuit pattern; and The plug column is filled in the tubular space of the conductive channel. 10. The embedded wiring structure as claimed in claim 9, wherein the first electroplating seed layer is further located between the second electroplating seed layers and the conductive channel.

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