CN101345028B - Circuitry for the display to read memory data - Google Patents
Circuitry for the display to read memory data Download PDFInfo
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- CN101345028B CN101345028B CN2007101283737A CN200710128373A CN101345028B CN 101345028 B CN101345028 B CN 101345028B CN 2007101283737 A CN2007101283737 A CN 2007101283737A CN 200710128373 A CN200710128373 A CN 200710128373A CN 101345028 B CN101345028 B CN 101345028B
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Abstract
A circuit system for reading memory data of a display comprises a plurality of memory blocks, a plurality of segment data buses and a latch circuit. Each memory block is used for storing a plurality of pixel data and outputting the pixel data according to an output control signal. The plurality of segment data buses are connected in series to form a row and used for transmitting the pixel data output by the plurality of memory blocks, each segment data bus comprises a data bus section and a transmission gate, wherein the data bus section is coupled with one memory block of the plurality of memory blocks and used for transmitting the pixel data output by the memory block, and the transmission gate is coupled between the data bus section and the other data bus section and used for conducting or blocking transmission connection between the data bus section and the other data bus section according to a switch control signal. The latch circuit is coupled to the segment data buses for receiving pixel data transmitted by the segment data buses according to a read control signal.
Description
Technical field
The present invention relates to a kind of Circuits System that is used for a display, particularly a kind of Circuits System that is used for a reading memory data by display device.
Prior art
LCD (liquid crystal display) is a kind of flat display apparatus (flat panel display), it has low radiation, external form is frivolous and advantage such as low power consuming, thereby be widely used in mobile computer (notebook computer), personal digital assistant (personal digital assistant, PDA), flat-surface television, or on the information products such as mobile phone.The principle of work of LCD is after converting viewdata signal (as red, blue, green signal) to suitable voltage signal, reverse liquid crystal molecule by voltage signal, change the angle that penetrates liquid crystal molecule backlight,, and then show whole image so that each pixel presents different colors.
Usually know that as this area tool the knowledgeable knows, LCD utilizes control and driving circuit to come the conversion image data signal to become suitable voltage signal.Please refer to Fig. 1, Fig. 1 is the existing control of a display and the block schematic diagram of driving circuit 10 of being used for.Control and driving circuit 10 comprise a storer 100, a sequential control device (Timing Controller) 110, one shift register (Shift Register) 112, one line bolt lock device (Line Latch) 114, one level shifter (Level Shifter) 116, one D/A (DAC) 118 and one source pole driver (Source Driver) 120.Storer 100 is used for storing image data, and by a data bus DB1 output image data to time sequence control device 110.In general, owing to display is adopted by the column scan mode, so storer 100 is once exported the view data (to call the row display data signal in the following text) of row.Time sequence control device 110 can carry out easy logical operation (as crack down upon evil forces, anti-white or the like) to the row display data signal, and then is sent to shift register 112 by a data bus DB2.Shift register 112 is used for gradual ground memory row display data signal, and after complete memory row display data signal, once delivers to line bolt lock device 114, and line bolt lock device 114 is sent to video data level shifter 116 again and does the level adjustment.At last, D/A 118 converts the row display data signal to analog voltage signal, exports analog voltage signal to corresponding pixel by source electrode driver 120 again.In addition, time sequence control device 110 not only needs the logical operation of processes and displays data-signal, also need receive the control signal from the outside, with control store 100 in time and shift register 112 outputs and receive the time and the order of data.
In control and driving circuit 10, time sequence control device 110 have simultaneously the logical operation function with to the sequential control function of other peripheral units, thus, on the real work of the hardware of time sequence control device 110, will face the big problem of complexity height and chip area.In addition, the view data that storer 100 is stored is successively to pass through data bus DB1 and data bus DB2, is sent to time sequence control device 110 and shift register 112.Twice data bus transmission can cause more power consumption.In addition, for the LCD of big panel size, time sequence control device 110 once needs the data volume handled also increasing.Therefore, in the view data process of processing memory 100, how to design a low-power consumption, data reading system that transfer efficiency is high is important problem.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of Circuits System that is used for a reading memory data by display device, transmits power consumption to reduce, and promotes transmission usefulness.
The present invention discloses a kind of Circuits System that is used for a reading memory data by display device.This Circuits System includes a plurality of memory blocks (Memory Bank), a plurality of segment data bus and a latch circuit.Each memory block of these a plurality of memory blocks is used for storing a plurality of pixel datas and according to an output control signal, exports this a plurality of pixel datas.These a plurality of segment data buses are connected into row, are used for transmitting the pixel data that this a plurality of memory block is exported.Wherein, each segment data bus packet contains a data bus section and a transmission gate.This data bus section is coupled to a memory block of these a plurality of memory blocks, and is used for transmitting the pixel data that this memory block is exported.This transmission gate is coupled between this data bus section and another data bus section, and is used for according to a switch controlling signal, conducting or block this data bus section and this another data bus section between transmission link.This latch circuit is coupled to this a plurality of segment data buses, and is used for reading control signal according to one, receives the pixel data that these a plurality of segment data buses are transmitted.
The present invention discloses a kind of Circuits System that is used for a reading memory data by display device in addition.This Circuits System includes a sequential control device, a plurality of memory block, a plurality of segment data bus and a latch circuit.This time sequence control device is used for producing an output control signal, a switch controlling signal and reads control signal.Each memory block of these a plurality of memory blocks is used for storing a plurality of pixel datas and according to this output control signal, exports this a plurality of pixel datas.These a plurality of segment data buses are connected into row, are used for transmitting the pixel data that this a plurality of memory block is exported, and each segment data bus packet contains a data bus section and a transmission gate.This data bus section is coupled to a memory block of these a plurality of memory blocks, is used for transmitting the pixel data that this memory block is exported.This transmission gate is coupled between this data bus section and another data bus section, be used for according to this switch controlling signal, conducting or block this data bus section and this another data bus section between transmission link.This latch circuit is coupled to this a plurality of segment data buses and this time sequence control device, is used for reading control signal according to this, receives the pixel data that these a plurality of segment data buses are transmitted.
Description of drawings
Fig. 1 is the existing control of a display and the block schematic diagram of driving circuit of being used for.
Fig. 2 is used for the control of a display and the block schematic diagram of driving circuit for one embodiment of the invention.
Fig. 3 to 6 is one embodiment of the invention according to the synoptic diagram of the Circuits System of the control of Fig. 2 and driving circuit.
The reference numeral explanation
10,20 control and driving circuits
100,300,400 storeies
110,210 time sequence control devices
112 shift registers
114,212 line bolt lock devices
116,214 level shifters
118,216 D/As
120,218 source electrode drivers
22,32,42,52,62 Circuits System
310,410,610 latch circuits
320 demoders
M_READ exports control signal
L_READ reads control signal
The SC switch controlling signal
TG1, TG2, TG3, TG4 transmission gate
MBK1, MBK2, MBK3, MBK4 memory block
M_DB1, M_DB2, M_DB3, M_DB4 internal data bus
LR1, LR (N/4), LR (N/4+1), LR (N/2), LR (N/2+1), LR (3N/4), LR (3N/4+1), LRN bolt lock device
LC1, LC (N/4), LC (N/4+1), LC (N/2), LC (N/2+1), LC (3N/4), LC (3N/4+1), LCN logical circuit
SGDB1, SGDB2, SGDB3, SGDB4 segment data bus
SDB1, SDB2, SDB3, SDB4 data bus section
DB1、DB2、DB3、EX_DB、M_DB1、M_DB2、M_DB3、M_DB4
Data bus.
Embodiment
Please refer to Fig. 2, Fig. 2 is used for the control of a display and the block schematic diagram of driving circuit 20 for one embodiment of the invention.The function of control and driving circuit 20 is same as control and the driving circuit 10 of Fig. 1, and the view data that is used for changing in the note body becomes suitable voltage signal, to export the pixel on the display pannel to.Control and driving circuit 20 include a Circuits System 22, a sequential control device 210, a line bolt lock device 212, a level shifter 214, a D/A 216 and one source pole driver 218.Circuits System 22 is used for reading inner memory data, and delivers to the action that line bolt lock device 212 is carried out row video data bolt-lock signal.Time sequence control device 210 is by associated control signal and setting, the running of control circuit system 22, for example the time of data read, in proper order, position and quantity.Line bolt lock device 212, level shifter 214, D/A 216 and source electrode driver 218 are same as the corresponding intrument of control and driving circuit 10, and relevant operation principles repeats no more.
Please continue with reference to figure 3, Fig. 3 is the synoptic diagram of one embodiment of the invention Circuits System 32.Circuits System 32 is used for realizing the Circuits System 22 of Fig. 2, and it includes a storer 300, a data bus DB3 and a latch circuit 310.Storer 300 is used for storing the pixel data that shows usefulness, and comes output pixel data according to the output control signal M_READ that time sequence control device 210 is exported.Be similar to the storer 100 of Fig. 1, storer 300 is preferably once exported the pixel data (to call the row display data signal in the following text) of row, and data bus DB3 is used for passing the row display data signal of storer 300 outputs.Latch circuit 310 is used for receiving the row display data signal that data bus DB3 is transmitted, and it comprises bolt lock device LR1～LRN and logical circuit LC1～LCN.As shown in Figure 3, bolt lock device LR1～LRN and logical circuit LC1～LCN are arranged in a crossed manner, and couple in mode one to one.Bolt lock device LR1～LRN is respectively coupled to data bus DB3, is used for the row display data signal that memory data bus DB3 transmitted.In the present embodiment, the quantity of bolt lock device is the number of pixels of display frame one row, and the data-signal of a pixel of each bolt lock device storage, makes bolt lock device LR1～LRN just in time can store the display data signal of row.Logical circuit LC1～LCN one is read control signal L_READ according to what time sequence control device 210 exported, and the pixel data signal that bolt lock device LR1～LRN is stored carries out logical operation respectively, as cracks down upon evil forces or anti-GTG value adjustment such as white.From the above, storer 300 is delivered to latch circuit 310 abreast with the row display data signal and is carried out the interrelated logic computing by data bus DB3.Therefore, the row display data signal only needs data bus once to transmit from the process that storer 300 is sent to line bolt lock device 212, and come the actuating logic computing by latch circuit 310, can lower the complexity in the design of time sequence control device 210 and dwindle its chip area.
In addition, on real the work, owing to storer 300 and latch circuit 310 sizes differ, so the row display data signal is different with the location definition that exports latch circuit 310 in the position of storer.In order to allow storer read correct row display data signal and to allow the row display data signal correctly be stored in latch circuit 310, time sequence control device 210 output is given latch circuit 310 corresponding to first address information (initial address) of row display data signal, and output corresponding to the replay address information (remapped address) of this address information to storer 300.In addition, latch circuit 310 decodings first address information is to learn the storage object of each bolt lock device among bolt lock device LR1～LRN.Storer 300 is by a demoder 320 replay address information of decoding.
For instance, suppose that picture dimension that display uses is 640 * 480 (OK * be listed as), latch circuit 310 should have 640 bolt lock devices, and storer 300 comprises 600 * 512 mnemon arrays.When if storer 300 is originated the picture data that provides by row storage external image, in picture data first row the row video data, storer 300 is by 600 pixel datas of memory cell stores of first row, in addition by 40 remaining pixel datas of preceding 40 memory cell stores of secondary series.Therefore, when the row display data signal of first row need export display pannel to, the replay address information that time sequence control device 210 is exported is after decoding, and storer 300 learns that the scope of the pixel data that needs output is the pixel data that first row all reach preceding 40 memory cells of secondary series.First address information of time sequence control device 210 outputs is after decoding, the data of latch circuit 310 control bolt lock device LR1～LRN memory 300 outputs in regular turn, be the data of first pixel of first row in the bolt lock device LR1 memory 300, and the data of the 40th pixel of bolt lock device LRN storage secondary series.In other words, first address information and replay address information are used for the data kenel of two dimension changeed and reflect (Remap) and be a data kenel of one dimension.
Please refer to Fig. 4, Fig. 4 is the synoptic diagram of another embodiment of the present invention Circuits System 42.Circuits System 42 is used for realizing the Circuits System 22 of Fig. 2, and it includes a storer 400 and a latch circuit 410.Storer 400 comprises memory block (Memory Bank) MBK1～MBK4, and it comprises an internal data bus M_DB1～M_DB4 respectively.Memory block MBK1～MBK4 is used for storing a plurality of pixel datas and according to the output control signal M_READ that time sequence control device 210 is exported, exports these a plurality of pixel datas by interior data bus M_DB1～M_DB4.In this enforcement, the pixel data that memory block MBK1～MBK4 is stored can be formed complete row display data signal, i.e. the row display data signal of each storage part of each memory block.The structure of latch circuit 410 and operation principles are same as the latch circuit 310 of Fig. 3, also comprise bolt lock device LR1～LRN and logical circuit LC1～LCN, and be used for one being read control signal L_READ the row display data signal of reception memorizer 400 outputs according to what time sequence control device 210 exported.As shown in Figure 4, bolt lock device LR1～LR (N/4), LR (N/4+1)～LR (N/2), LR (N/2+1)～LR (3N/4) and LR (3N/4+1)～LRN are used for storing internal data bus M_DB1～M_DB4 institute output pixel data respectively.Preferably, the data of a pixel in each bolt lock device memory row display data signal, thus, by bolt lock device LR1～LRN, latch circuit 410 can receive complete row display data signal.The pixel data signal that bolt lock device LR1～LRN is stored exports line bolt lock device 212 to after then carrying out logical operation via logical circuit LC1～LCN.As from the foregoing, the row display data signal is stored in different memory blocks after segmentation, and the internal data bus by its memory block exports latch circuit abreast to respectively.Therefore, directly transmit data by the sectional type internal data bus and give latch circuit, the embodiment of the invention can lower the power consumption of data transmission procedure.
In Circuits System 42, the internal data bus M_DB1～M_DB4 of storer 400 may couple an external data bus EX_DB, view data is sent to the outer peripheral assembly.In the case, in order to export the row display data signal smoothly, a transmission gate is set respectively between internal data bus M_DB1～M_DB4 and the external data bus in memory block MBK1～MBK4 to latch circuit 410.When memory block MBK1～MBK4 output row display data signal during the latch circuit 410, transmission gate blocking-up transmission between the two links, and just is unlikely making the row display data signal be sent to external data bus.If when storer 400 need carry out the pixel data transmission with external data bus, transmission gate then conducting transmission between the two linked, wherein, this external data bus can be by time sequence control device 210 controls.In addition, be similar to the Circuits System 32 of Fig. 3, can correctly be transmitted and be received for making the row display data signal, time sequence control device 210 also need be exported corresponding to first address information of row display data signal and give latch circuit 410, and output corresponding to the replay address information of this address information to memory block MBK1～MBK4.Latch circuit 410 also is used for first address information of decoding, and learning the storage object of bolt lock device LR1～LRN, and memory block MBK1～MBK4 respectively comprises a demoder, the replay address information that is used for decoding, with the memory location of pivot column display data signal.Its principle of work is explained in detail in preamble, is repeated no more herein.
What pay special attention to is, this field has knows that usually visual memory block size of using of the knowledgeable and pixel data amount decide the quantity of memory block, only as convenient explanation notion of the present invention, the quantity of its memory block is not limited only to four to present embodiment.The situation that couples of the internal bus of memory block and the bolt lock device of latch circuit is not also limited in present embodiment, the visual demand of bolt lock device quantity that it couples and adjusting.Therefore, under the enough big situation of the frequency range of the internal bus of and memory block less in pixel data amount (row video data amount), the Circuits System 42 of Fig. 4 can only utilize a memory block to finish.Please refer to Fig. 5, Fig. 5 is for utilizing the synoptic diagram of the Circuits System 52 that a memory block realizes according to the Circuits System 42 of Fig. 4.As shown in Figure 5, internal data bus M_DB1 is coupled to bolt lock device LR1～LRN, makes memory block MBK1 once export the object of complete row display data signal to latch circuit 410.
Please refer to Fig. 6, Fig. 6 is the synoptic diagram of another embodiment of the present invention Circuits System 62.Circuits System 62 is used for realizing the Circuits System 22 of Fig. 2, and it includes memory block (Memory Bank) MBK1～MBK4, segment data bus SGDB1～SGDB4 and a latch circuit 610.Each memory block of memory block MBK1～MBK4 is used for storing a plurality of pixel datas and according to an output control signal M_READ, exports this a plurality of pixel datas.In this enforcement, the pixel data that memory block MBK1～MBK4 is stored can be formed complete row display data signal, and meaning is the row display data signal of each memory block storage part.As shown in Figure 6, segment data bus SGDB1～SGDB4 is connected into row, and is used for transmitting the pixel data that memory block MBK1～MBK4 is exported.Segment data bus SGDB1～SGDB4 respectively comprises a data bus section and a transmission gate, is data bus section SDB1～SDB4 and transmission gate TG1～TG4 in regular turn.Data bus section SDB1～SDB4 is respectively coupled to memory block MBK1～MBK4, and transmits the pixel data that memory block MBK1～MBK4 is exported respectively.Each transmission gate is used for according to a switch controlling signal SC, conducting or block two transmission between the continuous segment data bus and link.Therefore for instance, as shown in Figure 6, transmission gate TG2 is coupled between data bus section SDB1 and the SDB2, and when segment data bus SGDB1 and SGDB2 had data to share or transmit, binding was transmitted in transmission gate TG2 conducting; When segment data bus SGDB1 and the independently working of SGDB2 need, transmission gate TG2 then blocks transmission binding between the two, and the data transmission of segment data bus SGDB1 and SGDB2 can not influenced each other.In addition, in the time of need carrying out data transmission with the outer peripheral assembly as if memory block MBK2, can link by transmission gate TG2～TG4 conducting transmission and reach transmission destination, wherein, this outer peripheral assembly can be time sequence control device 210.
Be similar to the latch circuit 410 of Fig. 4, latch circuit 610 comprises bolt lock device LR1～LRN and logical circuit LC1～LCN, and is used for reading control signal L_READ, the pixel data that reception segment data bus SGDB1～SGDB4 is transmitted according to one.Bolt lock device LR1～LR (N/4), LR (N/4+1)～LR (N/2), LR (N/2+1)～LR (3N/4) and LR (3N/4+1)～LRN are used for the pixel data that memory data bus section SDB1～SDB4 is transmitted respectively.Logical circuit LC1～LCN2 carries out logical operation to the pixel data signal that bolt lock device LR1～LRN is stored.Preferably, the data of a pixel in each bolt lock device memory row display data signal, thus, by bolt lock device LR1～LRN, latch circuit 610 can receive complete row display data signal.In addition, be similar to the Circuits System 42 of Fig. 4, can correctly be transmitted and be received for making the row display data signal, time sequence control device 210 output is given latch circuit 610 corresponding to first address information of row display data signal, and output corresponding to the replay address information of this address information to memory block MBK1～MBK4.Latch circuit 610 decodings first address information is learnt the storage object of bolt lock device LR1～LRN, and memory block MBK1～MBK4 respectively comprises a demoder, and the replay address information that is used for decoding is to get the memory location of pivot column display data signal.Its principle of work is explained in preamble in detail, in repeat no more herein.Therefore, as from the foregoing, by the data bus of series connection, independence and segmentation, the embodiment of the invention can transmit the data of a plurality of memory blocks simultaneously, and the data bus that therefore can utilize low frequency range is with the saving cost, and the increase data transmission efficiency.
What pay special attention to is, this field has knows that usually visual memory block size of using of the knowledgeable and pixel data amount decide the quantity of memory block, the purpose of present embodiment is to explain the notion of the data bus of series connection, independence, segmentation, and the quantity of its memory block is not limited only to four.The situation that couples of the bus segment of each segment data bus and the bolt lock device of latch circuit is not also limited in present embodiment, the visual demand of bolt lock device quantity that it couples and adjusting.In addition, present embodiment is to be example once to export a row video data, therefore simply comes control transmission door TG1～TG4 with the switch controlling signal SC that shares.For the application of some display, this field has knows that usually the knowledgeable utilizes time schedule controller 210 to produce other switch controlling signal and comes the conducting of independent control transmission door TG1～TG4 or blocking-up to link.
In a word, in the prior art, the pixel data of storer output needs to be undertaken exporting shift register to behind the image operation by time schedule controller earlier, delivers to the line bolt lock device at last again.In the meantime, pixel data needs the bus transfer through twice.Therefore, the power that the transmission course of pixel data consumes is more, and the design of existing time schedule controller needs lot of complexity and bigger chip area.With respect to prior art, the latch circuit of the embodiment of the invention is not only replaced shift register and is had the image operation function of existing time schedule controller, so pixel data only needs a bus transfer.In second embodiment of Circuits System of the present invention (Fig. 4 and 5), because external bus is responsible for the data transfer between many assemblies usually, pixel data transmits by internal data bus, can lower the charge capacity and the consumed power of external bus.In the 3rd embodiment of Circuits System of the present invention (Fig. 6), pixel data transmits by the data sink current drainage of series connection, independence and sectional type, also can be as external data remittance current drainage is divided into several individual section, thus, the output of the data in the memory block can multitask and independent control.Therefore, under the big situation of data volume, the embodiment of the invention does not need to increase the frequency range of external data remittance current drainage, increases the elasticity in the control yet.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (15)
1. Circuits System that is used for a reading memory data by display device includes:
A plurality of memory blocks, each memory block are used for storing a plurality of pixel datas and according to an output control signal, export this a plurality of pixel datas;
A plurality of segment data buses are connected into row, are used for transmitting the pixel data that this a plurality of memory block is exported, and each segment data bus packet contains:
One data bus section is coupled to a memory block of these a plurality of memory blocks, is used for transmitting the pixel data that this memory block is exported; And
One transmission gate is coupled between this data bus section and another data bus section, be used for according to a switch controlling signal, conducting or block this data bus section and this another data bus section between transmission link; And
One latch circuit is coupled to this a plurality of segment data buses, is used for reading control signal according to one, receives the pixel data that these a plurality of segment data buses are transmitted.
2. Circuits System as claimed in claim 1, it comprises a sequential control device in addition, is used for producing this output control signal, this switch controlling signal and this reads control signal.
3. Circuits System as claimed in claim 1, wherein, this latch circuit includes:
A plurality of bolt lock devices are used for storing the pixel data that these a plurality of segment data buses are transmitted; And
A plurality of logical circuits are respectively coupled to this a plurality of bolt lock devices, are used for the pixel data that this a plurality of bolt lock device is stored is carried out logical operation.
4. Circuits System as claimed in claim 1, wherein, the transmission gate of each segment data bus is during this data bus section transmits pixel data, the transmission of blocking between this data bus section and this last segment data bus links.
5. Circuits System as claimed in claim 1, wherein, this latch circuit be used in addition decoding one first address information of the pixel data that receives corresponding to this latch circuit.
6. Circuits System as claimed in claim 5, wherein, this first address information is corresponding to a replay address information.
7. Circuits System as claimed in claim 6, wherein, each memory block of this at least one memory block comprises a demoder in addition, and this replay address information is used for decoding.
8. Circuits System as claimed in claim 1, it comprises a line latch unit in addition, is coupled to this latch circuit, is used for receiving the data that this latch circuit is exported.
9. Circuits System that is used for a reading memory data by display device includes:
One sequential control device is used for producing output control signal, a switch controlling signal and and reads control signal;
A plurality of memory blocks are coupled to this time sequence control device, and each memory block is used for storing a plurality of pixel datas and according to this output control signal, exports this a plurality of pixel datas;
A plurality of segment data buses are connected into row, are used for transmitting the pixel data that this a plurality of memory block is exported, and each segment data bus packet contains:
One data bus section is coupled to a memory block of these a plurality of memory blocks, is used for transmitting the pixel data that this memory block is exported; And
One transmission gate is coupled between this data bus section and another data bus section, be used for according to this switch controlling signal, conducting or block this data bus section and this another data bus section between transmission link; And
One latch circuit is coupled to this a plurality of segment data buses and this time sequence control device, is used for reading control signal according to this, receives the pixel data that these a plurality of segment data buses are transmitted.
10. Circuits System as claimed in claim 9, wherein, this latch circuit includes:
A plurality of bolt lock devices are used for storing the pixel data that these a plurality of segment data buses are transmitted; And
A plurality of logical circuits are respectively coupled to this a plurality of bolt lock devices, are used for the pixel data that this a plurality of bolt lock device is stored is carried out logical operation.
11. Circuits System as claimed in claim 9, wherein, the transmission gate of each segment data bus is during this data bus section transmits pixel data, and the transmission of blocking between this data bus section and this last segment data bus links.
12. Circuits System as claimed in claim 9, wherein, this latch circuit be used in addition decoding one first address information of the pixel data that receives corresponding to this latch circuit.
13. Circuits System as claimed in claim 12, wherein, this first address information is corresponding to a replay address information.
14. Circuits System as claimed in claim 13, wherein, each memory block of this at least one memory block comprises a demoder in addition, and this replay address information is used for decoding.
15. Circuits System as claimed in claim 9, it comprises a line latch unit in addition, is coupled to this latch circuit, is used for receiving the data that this latch circuit is exported.
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| CN2007101283737A CN101345028B (en) | 2007-07-10 | 2007-07-10 | Circuitry for the display to read memory data |
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| CN2007101283737A CN101345028B (en) | 2007-07-10 | 2007-07-10 | Circuitry for the display to read memory data |
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| US10593256B2 (en) * | 2018-03-22 | 2020-03-17 | Sct Ltd. | LED display device and method for operating the same |
| CN109064991B (en) * | 2018-10-23 | 2020-12-29 | 京东方科技集团股份有限公司 | Gate drive circuit, control method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5406518A (en) * | 1994-02-08 | 1995-04-11 | Industrial Technology Research Institute | Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration |
| CN1131815A (en) * | 1994-11-10 | 1996-09-25 | 东芝株式会社 | Semi-conductor storage device |
| CN1388500A (en) * | 2001-05-24 | 2003-01-01 | 三星Sdi株式会社 | Flat Panel Display Driver |
| CN1395253A (en) * | 2001-06-28 | 2003-02-05 | 三菱电机株式会社 | Film magnetic storage of storage unit containing tunnel magnetoresistive element |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5406518A (en) * | 1994-02-08 | 1995-04-11 | Industrial Technology Research Institute | Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration |
| CN1131815A (en) * | 1994-11-10 | 1996-09-25 | 东芝株式会社 | Semi-conductor storage device |
| CN1388500A (en) * | 2001-05-24 | 2003-01-01 | 三星Sdi株式会社 | Flat Panel Display Driver |
| CN1395253A (en) * | 2001-06-28 | 2003-02-05 | 三菱电机株式会社 | Film magnetic storage of storage unit containing tunnel magnetoresistive element |
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|---|---|
| CN101345028A (en) | 2009-01-14 |
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