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CN101336477B - Chip stage integrated radio frequency passive device, manufacturing method thereof and system comprising the same - Google Patents

Chip stage integrated radio frequency passive device, manufacturing method thereof and system comprising the same Download PDF

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Publication number
CN101336477B
CN101336477B CN2006800523879A CN200680052387A CN101336477B CN 101336477 B CN101336477 B CN 101336477B CN 2006800523879 A CN2006800523879 A CN 2006800523879A CN 200680052387 A CN200680052387 A CN 200680052387A CN 101336477 B CN101336477 B CN 101336477B
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CN
China
Prior art keywords
tube core
passive
layer
passive device
wafer
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Expired - Fee Related
Application number
CN2006800523879A
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Chinese (zh)
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CN101336477A (en
Inventor
X·曾
何江奇
B·徐
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Intel Corp
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Intel Corp
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  • Semiconductor Integrated Circuits (AREA)

Abstract

A chip package includes a radio-frequency passive-device layer disposed below a dielectric layer on that backside surface of the die in the chip package. The inductive loop between the active surface of the die and the radio-frequency passive-device layer is small because any radio-frequency passive device is directly below the footprint of the die. A method of assembling a radio-frequency passive device layer includes die-level and board-level radio-frequency passive device layers. A computing system includes a radio-frequency passive device layer in a chip package.

Description

Chip stage integrated radio frequency passive device, its manufacture method and contain its system
Technical field
It is integrated that embodiment generally relates to the chip-scale of device.
Background technology
User for convenience makes the more and more littler pressure of the encapsulation of Miniature RF (RF) device just increasing.The RF device can use inductor in its operation, this inductor need be with respect to the high induction coefficient (high Q) of the transmitting-receiving power of RF device.
Usually, this high Q device is placed near the plank of integrated circuit (IC) tube core, and this tube core for example is its semiconductor chip that is provided with active circuit.The active device that high Q device makes it possible to the resource of semiconductor chip active surface is used for being integrated into circuit is set on plank.
Description of drawings
In order to describe the mode that obtains embodiment, the one exemplary embodiment is with reference to the accompanying drawings provided the above more detailed description of the embodiment of summary.Be appreciated that these accompanying drawings have only described exemplary embodiments, they may not be draw in proportion and therefore should not be regarded as limiting its scope, will utilize accompanying drawing to describe each embodiment with extra specificity and details, in the accompanying drawing:
Figure 1A is the sectional view according to the wafer during the processing of embodiment;
Figure 1B is the sectional view of wafer shown in Figure 1A during according to the further processing of embodiment;
Fig. 1 C is the sectional view of wafer shown in Figure 1B after applying adhesive tape according to embodiment;
Fig. 1 D is the sectional view of wafer shown in Fig. 1 C after forming dielectric layer according to embodiment;
Fig. 1 E is the sectional view of wafer shown in Fig. 1 D after forming the radio frequency passive device layer according to embodiment;
Fig. 1 F is the sectional view of wafer shown in Fig. 1 E after forming the through hole that penetrates tube core according to embodiment;
Fig. 1 G is the sectional view of wafer shown in Fig. 1 F after removing adhesive tape according to embodiment;
Fig. 2 is the cross section of facing according to the die-level radio frequency passive device layer in the Chip Packaging of embodiment;
Fig. 3 is the cross section of facing according to the radio frequency passive device floor in the hiding tube core occupation of land district in the substrate of the Chip Packaging of embodiment;
Fig. 4 is the cross section of facing according to the radio frequency passive device floor in the hiding tube core occupation of land of the part in the substrate of the Chip Packaging of embodiment district;
Fig. 5 take up an area of for the hiding tube core of having sealed in the substrate according to the Chip Packaging of embodiment the district the radio frequency passive device floor face the cross section;
Fig. 6 is the cross section of facing according to the flip chip tube core level radio frequency passive device layer in the Chip Packaging of embodiment;
Fig. 7 is according to the detail section of embodiment from Fig. 1 E intercepting;
Fig. 8 for according to embodiment, comprise the cross section of facing of die-level radio frequency passive device layer in the Chip Packaging of the centralized through hole that penetrates tube core;
Fig. 9 for according to embodiment, comprise the cross section of facing of die-level radio frequency passive device layer in the Chip Packaging of the centralized through hole that penetrates tube core; This Chip Packaging also comprises the radio frequency passive device floor that takes up an area of the district according to the hiding tube core in the Chip Packaging substrate of embodiment;
Figure 10 is the flow chart of describing method flow implementation example;
Figure 11 is the part excision view that illustrates according to the computing system of embodiment; And
Figure 12 is the schematic diagram according to the computing system of embodiment.
Embodiment
Embodiment in the disclosure relates to the equipment that comprises radio frequency (RF) passive-device layer, and this passive-device layer is deployed near the IC tube core with chip-scale.Embodiment relates on the tube core of RF passive-device layer and the deployment in the substrate.Embodiment also relates to the method with this RF passive-device layer and the assembling of IC tube core.Embodiment also relates to the computing system that is combined with die-level RF passive-device layer.Embodiment also relates to the computing system of the substrate deployments with RF passive-device layer.
Below describe comprise such as upper and lower, first, second etc. term, using them only is for descriptive purpose, but not is regarded as restriction.Can make, use or transport the equipment described here or the embodiment of article with a variety of positions and orientation.Term " tube core " and " chip " are often referred to the physical object as basic workpiece, described basic workpiece are transformed into the integrated circuit (IC)-components of hope by various technological operations.Tube core normally comes out from wafer-separate, and wafer can be made by the combination of semiconductor, non-semiconductor or semiconductor and non-semiconductor material.Plank normally flooded the glass fibre structure of resin, and it is serving as the installation base plate of tube core.
Referring now to accompanying drawing, will provide similar Reference numeral suffix for similar structures in the accompanying drawing.In order to be shown clearly in most the structure of each embodiment, the accompanying drawing that this paper comprises is the graphic representation of integrated circuit structure.Therefore, for example in microphoto, the actual look of manufacturing structure may be different, although it still contains the essential structure of illustrated embodiment.In addition, accompanying drawing shows and understands the necessary structure of illustrated embodiment.Do not comprise that other known structures of prior art are to keep the clarity of accompanying drawing.
Figure 1A is the sectional view according to the wafer during the processing of embodiment 100.Wafer 100 can be any semi-conductive material that contains.During handling, control wafer 100 to keep active device.
Figure 1B is the sectional view of wafer 100 shown in Figure 1A during according to the further processing of embodiment.Wafer 101 is processed, to comprise untreated semi-conducting material 110 (being called " Semiconductor substrate 110 " hereinafter) and active device circuit 112, active device circuit 112 is depicted as the structure that is independent of wafer 101 arbitrarily.Realizing passing in and out the connection of wafer 101 by a plurality of die bond pads, is that one of die bond pad is specified Reference numeral 114.After this processing, wafer 101 comprises active surperficial 116 and back surface 118.
In an embodiment, active device circuit 112 comprises that transistor in the semiconductor and other active devices are to constitute such as circuit such as static RAM (SRAM), embedded type dynamic random access memory (eDRAM), logical circuits.
Fig. 1 C is the sectional view of wafer 101 shown in Figure 1B after applying adhesive tape 120 according to embodiment.Wafer 102 has been adhered to adhesive tape 120, with permission it is handled, and realizes the layer that contains the RF passive device according to embodiment.In an embodiment, adhesive tape 120 loses significantly fusible hot charge releasing belt after for heating, thereby peels off adhesive tape 120 and can significantly not change circuit and die bond pads 114 from active surperficial 116.
Fig. 1 D is the sectional view of wafer 102 shown in Fig. 1 C after forming dielectric layer 122 according to embodiment.Handling dielectric layer 122 makes active device circuit 112 and will isolate with the layer electricity that contains the RF passive device that chip-scale is installed realizing.
In an embodiment, use thermal process to grow oxidation film 122 as dielectric layer 122.In an embodiment, (Figure 1A) carries out preliminary treatment to wafer 100, to realize oxidation film 122 under the heat condition of processing wafer 100 with use before realizing active device circuit 112.In an embodiment, dielectric layer 122 is that handle wafer 100 (Figure 1A) is to realize active device circuit 112 grown oxide film afterwards.In an embodiment, native oxide is used as dielectric layer 122.
In one embodiment, dielectric layer 122 is the oxide of deposit, for example the oxide that forms by decomposition of tetraethylene orthosilicate (TEOS).In one embodiment, dielectric layer 122 is the nitrogen oxide of deposit.In one embodiment, dielectric layer 122 is the carbide of deposit.In one embodiment, dielectric layer 122 is the sulfide of deposit.In one embodiment, dielectric layer 122 is the oxysulfide of deposit.In one embodiment, dielectric layer 122 is the boride of deposit.In one embodiment, dielectric layer 122 is the nitrogen boride of deposit.In one embodiment, dielectric layer 122 is for adhering to the organic layer of die backside surface 118.In one embodiment, dielectric layer 122 is the combination of any above-mentioned material.In one embodiment, dielectric layer 122 is the dielectric substance of deposit.
Under any circumstance, after forming dielectric layer 122, form die backside surface 119, it covers original die backside surface 118.After forming dielectric layer 122, " die backside surface " presentation surface 119 is unless point out to be original die backside surface 118 clearly.
In an embodiment, has the gross thickness of active device circuit 112, Semiconductor substrate 110 and dielectric layer 122 through the wafer of handling to realize dielectric layer 122 103.In an embodiment, die thickness 126 comprises the thickness of active device circuitry 112 and Semiconductor substrate 110, and gross thickness 124 comprises the thickness of die thickness 126 and dielectric layer 122.In one embodiment, for example, die thickness 126 is about 1000: 1001 with the ratio of gross thickness 124, and wherein dielectric layer 122 is the native oxide film on Semiconductor substrate 110 back surface 118.In one embodiment, for example, die thickness 126 is about 0.5: 1 with the ratio of gross thickness 124, and wherein dielectric layer is the thermal oxide layer of making in advance on the wafer 100 (Figure 1A).In one embodiment, for example, die thickness 126 is about 3: 1 with the ratio of gross thickness 124, wherein for SiO 2 Dielectric layer 122, dielectric layer 122 have and are equivalent to dielectric layer to the only about half of electric insulation quality of Semiconductor substrate thickness.In one embodiment, for example, die thickness 126 is about 1: 1 with the ratio of gross thickness 124, and wherein dielectric layer 122 is SiO 2 Dielectric layer 122.
Fig. 1 E is the sectional view of wafer 103 shown in Fig. 1 D after forming RF passive-device layer 128 according to embodiment.By RF passive-device layer 128 is adhered on the die backside surface 119, wafer 104 is handled.
Fig. 7 is according to the detail section of embodiment from Fig. 1 E intercepting.In an embodiment, RF passive-device layer 128 is a laminated material.The illustration illustration in wafer 104 left sides constitute the embodiment of the laminated material of RF passive-device layer 128.In this embodiment, RF passive-device layer 128 comprises the base dielectric 130 that is provided with near dielectric layer 122.RF passive-device layer 128 also comprises first conductive layer 132, intermediate dielectric 134, conductive interconnection 136, second conductive layer 138 and the external electric medium 140 that is provided with near base dielectric 130.
For this laminar structure, according to embodiment, RF passive-device layer 128 provides structure for the device such as inductor.In one embodiment, the laminar structure shown in Fig. 1 E 128 has helical (spiral) inductor according to known technology.In one embodiment, this laminar structure 128 has spiral (helical) inductor according to known technology.In one embodiment, this laminar structure 128 has the two-electrode thin-film capacitor (TFC) according to known technology.In one embodiment, laminar structure 128 comprises than two conductive layers 132 shown in Fig. 1 E and 138 more layers, to realize the interdigited capacitor (IDC) according to known technology.In one embodiment, RF passive-device layer 128 comprises that single conductive layer is to form the metal resistor according to known technology.In one embodiment, RF passive-device layer 128 comprises the diode resistance device according to known technology.
In one embodiment, conductive layer 132 and 138 and conductive interconnection 136 be metal such as copper, according to known technology, it can be by plating, lamination or composition.In one embodiment, base dielectric 130, intermediate dielectric 134 and external electric medium 140 are the high-k dielectric material, and this high-k dielectric material is flexible and can utilizes etching technique or (stenciling) technology of biting is come composition.
Fig. 1 F is the sectional view of wafer 104 shown in Fig. 1 E after forming the through hole 142 that penetrates tube core according to embodiment.According to an embodiment, form the through hole 142 that penetrates tube core by technology such as machine drilling.According to an embodiment, form the through hole 142 that penetrates tube core by technology such as laser drill.According to an embodiment, form the through hole 142 that penetrates tube core by technology such as reactive ion etching (RIE).
In one embodiment, during carrying out the processing shown in Figure 1B, in wafer 101, form the through hole 142 that penetrates tube core.In one embodiment, in wafer 102, forming the through hole 142 that penetrates tube core during the processing shown in the execution graph 1C.In one embodiment, in wafer 103, forming the through hole 142 that penetrates tube core during the processing shown in the execution graph 1D.In one embodiment, in wafer 104, forming the through hole 142 that penetrates tube core during the processing shown in the execution graph 1E.
Fig. 1 G is the sectional view of wafer 105 shown in Fig. 1 F after removing adhesive tape according to embodiment.During handling, in wafer 104, form under the situation of the through hole 142 that penetrates tube core, further handle the interconnection that comprises that formation is also represented by Reference numeral 142, subsequently by arranging RF passive-device layer 128 such as the technology of using the reference mark on the wafer backside surface 119, and deposit RF passive-device layer 128 is to make RF passive-device layer 128 and the electrical connection between 142 of interconnecting.
Reveal the bigger viscosity of specific viscosity crossed belt 120 if be arranged at structural table on the tube core active surperficial 116, then can by draw back the adhesive tape 120 shown in Fig. 1 F from tube core active surperficial 116 it be removed simply.In one embodiment, adhesive tape 120 is hot releasable material, at first to its heating, from tube core active surperficial 116 it is drawn back then.
Fig. 2 is the cross section of facing according to the die-level RF passive-device layer 228 in the Chip Packaging 200 of embodiment.In an embodiment, the wafer such as wafer 106 is separated to obtain tube core 201.Tube core 201 comprises active device circuit 212, dielectric layer 222, the RF passive-device layer 228 on the Semiconductor substrate 210, active surperficial 216 and interconnects 242.According to embodiment tube core 201 is adhered to installation substrate 248.In one embodiment, the adhesive 244 that utilizes all tube cores as is well known to attach adhesive adheres to tube core 201 and installs on the substrate 248.In an embodiment, any known RF passive device can be set in RF passive-device layer 228.
Between tube core 201 and installation substrate 248, carry out the transmission of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 250 according to embodiment.Joint line 250 utilizes die bond pads 214 and the substrate bond pad is installed at tube core 201 with install between the substrate 248 and be communicated with, with one of them mark in addition of 252 pairs of bond pads of Reference numeral.
In an embodiment, in RF passive-device layer 228, comprise at least one RF passive device, and by carry out all electric connections between tube core active surperficial 216 and the RF passive-device layer 228 according to the interconnection 242 of embodiment.Therefore, any inductance loop (inductive-loop) effect is minimized, because the electric connection between tube core active surperficial 216 and the RF passive device is included within the occupation of land district that the tube core on the substrate 248 is installed.As a comparison, in the time must the RF passive device laterally being installed with respect to tube core according to old technology, the some embodiment that set forth with the disclosure compare, and inductive-loop effect will be very remarkable.
Fig. 3 is the cross section of facing according to the RF passive-device layer 328 in the hiding tube core occupation of land district in the installation substrate 348 of the Chip Packaging 300 of embodiment.In an embodiment, the wafer such as wafer 106 is separated to obtain tube core 301.Tube core 301 comprises active device circuit 312, the dielectric layer 322 on the back surface 318 on the Semiconductor substrate 310, active surperficial 316 and interconnects 342.
According to embodiment tube core 301 is adhered on the installation substrate 348.In an embodiment, RF passive-device layer 328 in company with being installed, substrate 348 is provided with together.Therefore, during substrate 348 make to be installed, RF passive-device layer 328 be with trace, in conjunction with refer to, interconnect and the bonding installation substrate 348 that go between in other structures of common needs make on the spot.In an embodiment, any known RF passive device can be set in RF passive-device layer 328.
Between tube core 301 and installation substrate 348, carry out the transmission of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 350 according to embodiment.Joint line 350 utilizes die bond pads 314 and the substrate bond pad is installed at tube core 301 with install between the substrate 348 and link up, with one of them mark in addition of 352 pairs of bond pads of Reference numeral.
In an embodiment, in RF passive-device layer 328, comprise at least one RF passive device, and utilize interconnection bond pad 354 according to embodiment by 342 all electric connections that carry out between tube core active surperficial 316 and the RF passive-device layer 328 that interconnect.Therefore, any inductive-loop effect is minimized, take up an area of within the district because the electric connection between tube core active surperficial 316 and the RF passive device is included in the tube core of installing on the substrate 348.Because substrate dielectric coating 347 or 349 and the electricity that causes is isolated among the very sufficient embodiment exist to be installed, can cancel dielectric layer 322.
Fig. 4 is the cross section of facing according to the RF passive-device layer 428 in the hiding tube core occupation of land of the part in the installation substrate 448 of the Chip Packaging 400 of embodiment district.In an embodiment, the wafer such as wafer 106 is separated to obtain tube core 401.Tube core 401 comprises active device circuit 412, the dielectric layer 422 on the back surface 418 on the Semiconductor substrate 410, active surperficial 416 and interconnects 442.
Tube core 401 is adhered on the installation substrate 448 in dielectric layer backside surface 419 according to embodiment.In an embodiment, within installation substrate 448, RF passive-device layer 428 is set.Therefore, during substrate 448 make to be installed, RF passive-device layer 428 be with trace, in conjunction with refer to, interconnect and the bonding installation substrate 448 that go between in other structures of common needs make on the spot.In an embodiment, any known RF passive device can be set in RF passive-device layer 428.
Between tube core 401 and installation substrate 448, carry out the transmission of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 450, represent one of them with Reference numeral 456 according to embodiment.First joint line 450 utilizes die bond pads 414 and substrate first bond pad is installed and is communicated with between tube core 401 and installation substrate 448, represents one of first bond pad with Reference numeral 452.Second joint line 456 utilizes and may be communicated with between tube core 401 and installation substrate 448 in die bond pads outside the plane shown in Fig. 4 sectional view 414 and installation substrate second bond pad, represents one of second bond pad with Reference numeral 460.
In an embodiment, in RF passive-device layer 428, comprise at least one RF passive device, by interconnect 442 and interconnection bond pad 454 carry out some electric connections between tube core active surperficial 416 and the RF passive-device layer 428.By second joint line 456 and second some electric connections that substrate bond pad 460 carries out between tube core active surperficial 416 and the RF passive-device layer 428 are installed.Therefore, most of inductive-loop effect is minimized, because the electric connection between tube core active surperficial 416 and the RF passive device is included within the occupation of land district that the tube core 401 on the substrate 448 is installed.Because inductance loop takes up an area of the second installation substrate bond pad 460 outside the district from the tube core active surperficial 416 proper tube cores of installing on the substrate 448 401 that lead to, so can produce some inductive-loop effect between tube core active surperficial 416 and RF passive device.Be that tube core takes up an area of when selecting to lead to the inlet of the RF passive device in the RF passive-device layer 428 outside the district, and this embodiment can take place.In one embodiment, the position of substrate first bond pad 452 and substrate second bond pad 460 is on a line, because the sectional plane that intercepts among Fig. 4, they stashes for a moment in Fig. 4.
Fig. 5 take up an area of for the hiding tube core of having sealed in the substrate 548 according to the Chip Packaging 500 of embodiment the district RF passive-device layer 528 face the cross section.In an embodiment, the wafer such as wafer 106 is separated to obtain tube core 501.Tube core 501 comprises active device circuit 512, the dielectric layer 522 on the back surface 518 on the Semiconductor substrate 510, active surperficial 516 and interconnects 542.
According to embodiment, tube core 501 is adhered to installation substrate 548 also protected with sealing 562.In an embodiment, can seal the arbitrary structures shown in Fig. 2-9.
Between tube core 501 and installation substrate 548, carry out the connection of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 550 according to embodiment.Joint line 550 utilizes die bond pads 514 and the substrate bond pad is installed at tube core 501 with install between the substrate 548 and be communicated with, and with 552 pairs of Reference numerals in addition mark of one of substrate bond pad is installed.
Fig. 6 is the cross section of facing according to the flip chip tube core level RF passive-device layer 628 in the Chip Packaging 600 of embodiment.In an embodiment, the wafer such as wafer 106 is separated to obtain tube core 601.Tube core 601 comprises active device circuit 612 on the Semiconductor substrate 610, active surperficial 616, is arranged at the dielectric layer 622 on Semiconductor substrate 610 back surface 618.Tube core 601 also comprises RF passive-device layer 628 and interconnection 642.According to embodiment RF passive-device layer 628 is adhered to die backside surface 619.In an embodiment, any known RF passive device can be set in RF passive-device layer 628.
Between tube core 601 and installation substrate 648, carry out the connection of the signal of telecommunication and power by a series of solder bumps, express one of solder bump with Reference numeral 664 according to embodiment.Solder bump 664 utilizes die bond pads 614 and the substrate bond pad is installed and is communicated with between tube core 601 and installation substrate 648, represents to install one of substrate bond pad with Reference numeral 652.According to embodiment, further to utilize end underfill material 666 that tube core 601 is adhered to substrate 648 is installed, end underfill material is being protected active surperficial 616 the circuit of tube core.
Fig. 8 for according to embodiment, comprise that centralization penetrates the cross section of facing of die-level RF passive-device layer 828 in the Chip Packaging 800 of through hole 842 of tube core.In an embodiment, separating wafer is to obtain tube core 801.Tube core 801 comprises active device circuit 812, dielectric layer 822, the RF passive-device layer 828 on the Semiconductor substrate 810, active surperficial 816 and interconnects 842.In an embodiment, spatially define tube core 801 by the line of symmetry 870 of laterally dividing tube core 801 equally.Line of symmetry 870 has defined first distance 872 of die edge 874 and has arrived the second distance 876 of interconnection 842.In one embodiment, first distance 872 is approximately 1 divided by second distance 876, and this is the spatial depiction shown in Fig. 1 G and Fig. 2 to 7.In one embodiment, first the distance 872 divided by second distance 876 greater than 1, this is Fig. 8 and spatial depiction shown in Figure 9.For realize first the distance every kind of layout of 872 interconnection of making divided by the given ratio of second distance 876 842 in, can select given ratio, for example, be used for realizing the useful loop inductance (loop inductance) of given layout and RF passive-device layer 828 RF passive device positions to active surperficial 816.
According to embodiment tube core 801 is adhered to installation substrate 848.In an embodiment, the adhesive 844 that utilizes all tube cores as is well known to attach adhesive adheres to tube core 801 and installs on the substrate 848.In an embodiment, any known RF passive device can be set in RF passive-device layer 828.
Between tube core 801 and installation substrate 848, carry out the connection of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 850 according to embodiment.Joint line 850 utilizes die bond pads 814 and the substrate bond pad is installed at tube core 801 with install between the substrate 848 and be communicated with, and with 852 pairs of Reference numerals in addition mark of one of substrate bond pad is installed.
In an embodiment, in RF passive-device layer 828, comprise at least one RF passive device, and according to embodiment by 842 all electric connections that carry out between tube core active surperficial 816 and the RF passive-device layer 828 that interconnect.Therefore, any inductive-loop effect is minimized, because the electric connection between tube core active surperficial 816 and the RF passive device is included within the occupation of land district that the tube core 801 on the substrate 848 is installed.As a comparison, in the time must the RF passive device laterally being installed with respect to tube core, the some embodiment that set forth with the disclosure compare, and inductive-loop effect will be very remarkable.
Fig. 9 for according to embodiment, comprise that centralization penetrates the cross section of facing of die-level radio frequency passive device layer 928 in the Chip Packaging 900 of through hole 942 of tube core.In an embodiment, spatially define tube core 901 by the line of symmetry 970 of laterally dividing tube core 901 equally.Line of symmetry 970 has defined first distance 972 of die edge 974 and has arrived the second distance 976 of interconnection 942.In one embodiment, first distance 972 is approximately 1 divided by second distance 976, and this is the spatial depiction shown in Fig. 1 G and Fig. 2 to 7.In one embodiment, first the distance 972 divided by second distance 976 greater than 1, this is Fig. 8 and spatial depiction shown in Figure 9 just.For realize first the distance every kind of layout of 972 interconnection of making divided by the given ratio of second distance 976 942 in, can select given ratio, for example, be used for realizing the useful loop inductance of given layout and RF passive-device layer 928 RF passive device positions to active surperficial 916.
According to embodiment tube core 901 is adhered on the installation substrate 948.In an embodiment, within installation substrate 948, RF passive-device layer 928 is set.Therefore, during substrate 948 make to be installed, RF passive-device layer 928 be with trace, in conjunction with refer to, interconnect and the bonding installation substrate 948 that go between in other structures of common needs make on the spot.In an embodiment, any known RF passive device can be set in RF passive-device layer 928.
Between tube core 901 and installation substrate 948, carry out the connection of the signal of telecommunication and power by a series of joint lines, express one of joint line with Reference numeral 950 according to embodiment.Joint line 950 utilizes die bond pads 914 and the substrate bond pad is installed at tube core 901 with install between the substrate 948 and be communicated with, and with 952 pairs of Reference numerals in addition mark of one of substrate bond pad is installed.
In an embodiment, in RF passive-device layer 928, comprise at least one RF passive device, and utilize interconnection bond pad 954 by 942 all electric connections that carry out between tube core active surperficial 916 and the RF passive-device layer 928 that interconnect according to embodiment.Therefore, any inductive-loop effect is minimized, because the electric connection between tube core active surperficial 916 and the RF passive device is included within the occupation of land district that the tube core on the substrate 948 is installed.Because substrate dielectric 947 or 949 and the electricity that causes is isolated among the fully good embodiment exist to be installed, can cancel dielectric layer 922.
Figure 10 is the flow chart 1000 of describing method flow implementation example.
1010, this method is included in and forms dielectric layer on the wafer backside surface.In exemplary embodiments, the SiO of dielectric layer 122 for forming by the wafer 100 shown in heat treatment Figure 1A 2Layer.
1020, this method is included in and forms the RF passive laminate on the dielectric layer.In exemplary embodiments, on dielectric layer 122, aim at this RF passive laminate 128 and adhere to (Fig. 1 E) by heat treatment.In exemplary embodiments, dielectric layer 322 is placed and install on the RF passive laminate 328 of substrate 348 one.In one embodiment, this method ends at 1020.
1030, this method comprises wafer or the tube core of taking from wafer is electrically connected to the RF passive laminate.In exemplary embodiments, when placing RF passive laminate 128 on the die backside surface 219, RF passive laminate 128 is electrically connected to tube core 201 (Fig. 2).In exemplary embodiments, in that being placed, tube core RF passive laminate 328 is electrically connected to tube core 301 when installing on the substrate 348, and substrate 348 is installed is comprised the part (Fig. 3) of RF passive laminate 328 as its one.In exemplary embodiments, when being bonded to tube core 401 lead-in wires on installation substrate second bond pad 460, RF passive laminate 428 is electrically connected to tube core 401, this installation substrate second bond pad 460 is coupled to RF passive laminate 428 (Fig. 4).
1040, this method is included in and forms the through hole that penetrates wafer in the wafer.In exemplary embodiments, before further handling, in the structure shown in Fig. 1 D, form the through hole 142 that penetrates wafer, carry out method flow 1020 subsequently.
1050, this method comprises carries out scribing to wafer.In exemplary embodiments, form the through hole 142 that penetrates wafer 1040, carry out scribing at 1050 pairs of wafers subsequently.In an embodiment, this method ends at 1050.
1060, this method comprises provides the installation substrate.In exemplary embodiments, this method comprises the installation substrate 248 that is provided is provided chip 201.In exemplary embodiments, this method comprises the installation substrate 248 that is provided is provided chip 201.In exemplary embodiments, this method comprises method 1062, wherein the RF passive-device layer is included in to install in the substrate.Therefore, this method proceeds to 1060 from 1010, proceeds to 1062 then.In an embodiment, this method ends at 1062.
Figure 11 is the part excision view that illustrates according to the computing system 1100 of embodiment.One or more the foregoing descriptions of RF passive-device layer can be used in the computing system, for example be used in the computing system 1100 of Figure 11.Be called the embodiment configuration with independent arbitrary RF passive-device layer embodiment or with the combination of any other embodiment hereinafter.
For example, computing system 1100 comprises at least one processor (not shown), data-storage system 1112, at least one input unit and at least one output device such as monitor 1116 such as keyboard 1114 that is encapsulated in the IC Chip Packaging 1110.Computing system 1100 comprises the processor of process data signal, and for example can comprise the microprocessor that can obtain from Intel Corporation.For example, except keyboard 1114, computing system 1100 can also comprise another user input apparatus such as mouse 1118.This computing system 1100 can comprise a kind of structure, the given RF passive-device layer embodiment after handling shown in Fig. 1 G and 2-9.
For the purpose of this disclosure, embodiment can comprise any system that utilizes the microelectronic component system according to the computing system 1100 of the assembly of institute's claimed subject matter, and for example it can comprise at least one the RF passive-device layer embodiment that is coupled to such as the data storage of dynamic random access memory (DRAM), polymer memory, flash memory and phase transition storage.In this embodiment, by embodiment being coupled to processor it is coupled to these functional any combinations.In an embodiment, yet, the embodiment configuration that the disclosure is set forth be coupled to these functional any.For an exemplary embodiment, data storage comprises the embedded DRAM cache memory on the tube core.In addition, in an embodiment, the embodiment that is coupled to the processor (not shown) is configured to have the part of system of the embodiment configuration of the data storage that is coupled to the DRAM cache memory.In addition, in an embodiment, data storage 1112 is coupled in the embodiment configuration.
In an embodiment, this computing system 1100 can also comprise the tube core that comprises digital signal processor (DSP), microcontroller, application-specific integrated circuit (ASIC) (ASIC) or microprocessor.In this embodiment, by processor is coupled in the embodiment configuration it is coupled to these functional any combinations.For exemplary embodiment, DSP is the part of chipset, and this chipset can comprise independent processor and as the DSP of the part that is independent of chipset on the plate 1120.In this embodiment, DSP is coupled in the embodiment configuration, and can has the independent embodiment configuration of the processor that is coupled in the IC Chip Packaging 1110.In addition, in an embodiment, embodiment configuration is coupled to IC Chip Packaging 1110 is installed in DSP on the same plate 1120.Can recognize now, can as set forth ground at computing system 1100, make up the embodiment configuration in conjunction with by the described embodiment configuration of each embodiment of RF passive-device layer and equivalent thereof in the disclosure.
Can recognize now, the described embodiment of the disclosure can be applied to device and equipment except that traditional computer.For example, tube core can encapsulate and place such as the mancarried device of wireless communication device or such as the hand-held device of personal digital assistant etc. with embodiment configuration.Another example is and to place the tube core of means of transportation with the embodiment configuration packages, and means of transportation for example is automobile, train, boats and ships, airborne vehicle or space craft.
Figure 12 is the schematic diagram according to the electronic system 1200 of embodiment.Illustrated electronic system 1200 can comprise computing system shown in Figure 11 1100, but this electronic system is more general description.This electronic system 1200 comprises at least one electronic building brick 1210, for example the IC tube core shown in Fig. 2-9.In an embodiment, this electronic system 1200 is a computer system, and this computer system comprises the system bus 1220 of each assembly of electric coupling electronic system 1200.According to each embodiment, system bus 1220 is the combination in any of single bus or each bus.Electronic system 1200 is included as the voltage source 1230 of integrated circuit 1210 power supplies.In certain embodiments, voltage source 1230 provides electric current by system bus 1220 for integrated circuit 1210.
According to embodiment, integrated circuit 1210 is electrically coupled to system bus 1220, and comprises any circuit or combination of circuits.In an embodiment, integrated circuit 1210 comprises and can be the processor 1212 of any kind.As used herein, processor 1212 expressions are such as but not limited to the circuit of any kind of microprocessor, microcontroller, graphic process unit, digital signal processor or another kind of processor.The circuit of the other types that can comprise in the integrated circuit 1210 is custom circuit or ASIC, for example is used for the telecommunication circuit 1214 such as wireless device, portable computer, twoway radio and the similar electronic system of mobile phone, beeper.In an embodiment, processor 1210 comprises such as memory 1216 on the tube core of SRAM.In an embodiment, processor 1210 comprises such as memory 1216 on the tube core of eDRAM.
In an embodiment, electronic system 1200 also comprises external memory storage 1240, external memory storage can comprise the driver of the one or more memory elements, one or more hard disk drive 1244 and/or the one or more manipulation removable medias 1246 that are suitable for application-specific again, this memory element for example is the main storage 1242 of RAM form, and this removable media for example is floppy disk, CD (CD), digital video disc (DVD), flash storage key and other removable medias well known in the art.
In an embodiment, electronic system 1200 also comprises display unit 1250 and audio frequency output 1260.In an embodiment, electronic system 1200 comprises controller 1270, for example keyboard, mouse, tracking ball, game console, microphone, speech recognition equipment or in electronic system 1200 any other device of input information.
As shown here, integrated circuit 1210 can be embodied as a lot of different embodiment, comprise Electronic Packaging, electronic system, computer system, one or more make the method for integrated circuits and one or more make the method for electronic building bricks, this electronic building brick comprises the integrated circuit that each embodiment herein sets forth and contains the layer of RF passive device and this area is thought their equivalent.Element, material, geometry, size and operating sequence can change to adapt to specific encapsulation requirement.
Provide summary to meet the regulation of 37C.F.R. § 1.72 (b), its requirement provides summary, so that the reader can understand disclosed essence of technology and main points rapidly.Submit to summary should be understood that, should not use it for scope or the implication explaining or limit claim.
In above detailed description, for disclosed smoothness, in single embodiment with various characteristics combination together.Disclosed this method should not be understood that to reflect following motivation: the embodiments of the invention of being advocated need more many feature than what every claim was clearly enumerated.On the contrary, as the following claims reflect, subject matter is embodied in all features feature still less than single disclosed embodiment.Therefore following claim is incorporated among the embodiment, every claim self is represented independently preferred embodiment.
Those skilled in the art will readily appreciate that, describe in order to explain essence of the present invention and illustrated parts and the details in method stage, material and arrangement aspect can make various other and change, and do not break away from the principle and scope of the present invention expressed as claims.

Claims (21)

1. chip stage integrated radio frequency passive device comprises:
Tube core, it comprises active surface and back surface;
Dielectric layer, it is arranged on the described back surface;
At least one radio frequency (RF) passive device, it is arranged under the described dielectric layer; And
Electrical connection between described active surface and described at least one RF passive device.
2. device according to claim 1, wherein said electrical connection comprise that the tube core that penetrates that penetrates described tube core interconnects.
3. device according to claim 1, wherein said dielectric layer is selected from oxide, nitrogen oxide, carbide, sulfide, oxysulfide, boride, nitrogen boride, organic substance and combination thereof.
4. device according to claim 1, wherein said RF passive device is set in the RF passive-device layer, and contains the inductor that is selected from spiral inductor, spiral inductor and combination thereof.
5. device according to claim 1, wherein said RF passive device is set in the RF passive-device layer, and contains the capacitor that is selected from two-electrode thin-film capacitor, interdigited capacitor and combination thereof.
6. device according to claim 1, wherein said RF passive device is set in the RF passive-device layer, and contains the resistor that is selected from metal resistor, diode and combination thereof.
7. device according to claim 1, wherein said RF passive device is set in the RF passive-device layer, and contains in inductor, capacitor and the resistor at least two kinds.
8. device according to claim 1, wherein said electrically connecting as penetrates tube core interconnection, and wherein said tube core has die edge and die center, and wherein saidly penetrates the tube core interconnection and be configured to apart from described die edge than nearer apart from described die center.
9. device according to claim 1, wherein said electrically connecting as penetrates tube core interconnection, and wherein said tube core has die edge and die center, and wherein saidly penetrates the tube core interconnection and be configured to apart from described die center than nearer apart from described die edge.
10. device according to claim 1 also comprises the installation substrate that is arranged on described die backside surface below, and at least one RF passive-device layer wherein is set within described installation substrate.
11. device according to claim 1 also comprises the installation substrate, and wherein by the configuration of selecting from lead-in wire bonding and flip-chip described tube core is set on the described installation substrate.
12. the manufacture method of a chip stage integrated radio frequency passive device comprises:
Form dielectric layer on wafer, described wafer comprises active surface and back surface, and wherein said formation step is included in the described dielectric layer of formation on the described wafer backside surface; And
The layer that contains radio frequency (RF) passive device is set on described dielectric layer.
13. method according to claim 12 also comprises:
In described wafer, form the through hole that penetrates tube core; And
The active surface of described wafer is connected to the layer of the described RF of containing passive device by the described through hole that penetrates tube core.
14. method according to claim 12 also comprises:
Described wafer is carried out scribing to obtain at least one tube core;
Described tube core is coupled to the installation substrate, and wherein said installation substrate holds described tube core at the layer place of the described RF of containing passive device.
15. method according to claim 12 also comprises:
Described wafer is carried out scribing to obtain at least one tube core; And
Described tube core is coupled to the installation substrate, and wherein said installation substrate comprises the layer of the described RF of containing passive device, and wherein described dielectric layer is arranged between the layer of active surface of described tube core and the described RF of containing passive device.
16. method according to claim 12 also comprises:
Described wafer is carried out scribing to obtain at least one tube core; And
Described tube core is coupled to the layer of the described RF of containing passive device by the method selected from following method: the through hole that utilizes intercommunicated mistake to penetrate tube core is coupled, being coupled and making up by it by the lead-in wire bonding is coupled.
17. method according to claim 12 also comprises:
Described wafer is carried out scribing to obtain at least one tube core, and wherein said tube core comprises die edge and die center; And
The through hole that uses interconnection and penetrate tube core is coupled to the layer of the described RF of containing passive device with described tube core, and the wherein said through hole that penetrates tube core is configured to apart from described die center than nearer apart from described die edge.
18. a system that comprises chip stage integrated radio frequency passive device comprises:
Tube core, it comprises active surface and back surface;
Dielectric layer, it is arranged on the described back surface;
At least one radio frequency (RF) passive device, it is arranged under the described dielectric layer; And
Electrical connection between described active surface and described at least one RF passive device; And
Be coupled to the dynamic random access memory of described tube core.
19. system according to claim 18, wherein said tube core is set to be installed on the substrate, and wherein said RF passive device is set in the described installation substrate.
20. system according to claim 18, wherein said system is set in one of computer, Wireless Telecom Equipment, personal digital assistant, automobile, train, airborne vehicle, boats and ships and space craft.
21. system according to claim 18, wherein said tube core is selected from data storage device, microcontroller, application-specific integrated circuit (ASIC) and microprocessor.
CN2006800523879A 2006-03-06 2006-03-06 Chip stage integrated radio frequency passive device, manufacturing method thereof and system comprising the same Expired - Fee Related CN101336477B (en)

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