CN101334764B - Interface device and voltage processing method based on the interface device - Google Patents
Interface device and voltage processing method based on the interface device Download PDFInfo
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- CN101334764B CN101334764B CN2008101171401A CN200810117140A CN101334764B CN 101334764 B CN101334764 B CN 101334764B CN 2008101171401 A CN2008101171401 A CN 2008101171401A CN 200810117140 A CN200810117140 A CN 200810117140A CN 101334764 B CN101334764 B CN 101334764B
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Abstract
The invention discloses an interface apparatus comprising an interface module, a power supply providing power for the interface module and a low dropout regulator (LDO) which is provided with an input pin connected with the power supply and an output pin connected with the interface module and is used for firstly delaying the voltage sent out from the power supply and then sending the delayed voltage to the interface module. The invention simultaneously discloses a voltage processing method based on the interface apparatus. The adoption of the apparatus and method of the invention can avoid the damage to the interface module caused by an over output voltage from the power supply in the moment the interface module is connected with the power supply.
Description
Technical field
The present invention relates to the voltage treatment technology, particularly a kind of preventing because transient voltage is too high to the hurtful interface arrangement of equipment and based on the voltage processing method of this interface arrangement.
Background technology
In the prior art; when interface module is connected to moment of power supply by interface, through regular meeting the too high problem of electric power output voltage appears, if the magnitude of voltage of this output surpasses the maximum voltage value that interface module can bear; then can cause interface module to be compromised, thereby can not normally use.With described interface module is that USB (universal serial bus) (USB, Universal Serial Bus) chip is an example:
The USB integrated circuit (IC, Integrated circuit) that the PXA310 core board adopts is the USB3318 chip of History of United States of America grace uncommon (SMSC).The characteristics of this chip are to use USB 2.0 transceiver macroelement interfaces+low pin count interface (ULPI, USB 2.0Transceiver Macrocell Interface+Low PinInterface), support that (OTG On-the-Go), supports USB 2.0 version (High Speed) at a high speed to plug and play.The chip that present industry has identical function also has the ISR1504C chip of grace intelligence Pu semiconductor (NXP) etc.Find that in the use of PXA310 core board plug usb data line (Cable) is easy to cause the USB3318 chip breakdown, concrete reason is analyzed as follows:
Fig. 1 is the circuit diagram of existing USB3318 chip.As shown in Figure 1, this USB3318 chip comprises 25 pins (PIN) altogether, and that wherein related to the present invention is 2PIN, 3PIN and 4PIN, i.e. VBUS pin, VBAT pin and VD3P3 pin.One end of VBUS pin connects the VBUS power supply, and the other end connects some elements (not shown) of USB3318 chip internal.The VBAT pin is the input pin of USB3318 chip, and an end connects the VBUS power supply, and the other end connects the low pressure difference linear voltage regulator (LDO, Low Dropout Regulator) (not shown) of USB3318 chip internal.The VD3P3 pin is the output pin of USB3318 chip, and an end connects the LDO of USB3318 chip internal, that is to say that LDO is connected between VBAT and the VD3P3 pin, as shown in Figure 2; Simultaneously, the other end of VD3P3 pin is by shunt capacitance C
BYPGround connection, shunt capacitance V
BYPFunction mainly be to be used to carry out some little filtering.
System Performance Evaluation Corporation (SPEC according to USB3318; System Performance EvaluationCorporation) as can be known; the absolute maximum voltage value that two pins of VBUS and VBAT can bear is 6V; but; in actual applications; when the moment that the USB3318 chip initially inserts USB interface, the voltage that the VBUS power supply provides can be higher than 6V usually, promptly produces surge voltage.In this case, will cause the USB3318 chip breakdown, make this chip cisco unity malfunction.Illustrate: the voltage of VD3P3 pin output is that the LDO by the USB3318 chip internal produces, and under the normal condition, this magnitude of voltage is 3.3V, but,, will puncture LDO if the VBAT pin voltage is too high, cause LDO to damage, at this moment, the VD3P3 pin will not have voltage output.As shown in Figure 3, Fig. 3 obtains by oscilloscope measurement for existing VBAT pin surge voltage synoptic diagram.Moment after the USB3318 chip inserts USB interface, owing to the surge reason, the voltage of VBAT pin reaches 6.81V, and in the duration more than the 6V is about 3us probably, magnitude of voltage has exceeded the absolute maximum voltage value that the VBAT pin can bear, so cause the LDO of USB3318 chip internal breakdown.Similarly situation also can appear on the VBUS pin.
At the problems referred to above, traditional solution is to add electric capacity and resistance at the VBUS power end, as shown in Figure 1, between VBUS power supply and VBUS pin, be connected a resistance R 57, while is series connection one capacitor C 70 on the VBUS power supply, and the concrete value of the appearance value of the resistance of resistance R 57 and capacitor C 70 can be provided with according to actual needs or rule of thumb.Such as, the resistance of resistance R 57 is made as 820 Ω among Fig. 1, and the appearance value of capacitor C 70 is made as 4.7uF.Utilize the prevention function of current of resistance R 57 and the voltage function of releiving of capacitor C 70 to reach the purpose that prevents to produce surge voltage.In addition, as shown in Figure 1, be connected with a resistance R 38 between VBAT pin and the VBUS power supply, its resistance is 0 Ω, that is to say, this resistance R 38 just plays without hindrance connection effect, but the benefit that is provided with like this is to be convenient to follow-up debugging.
In addition, can also improve on the basis of circuit shown in Figure 1, as shown in Figure 4, Fig. 4 is the circuit diagram that prevents to produce surge voltage after improving on the basis of Fig. 1.Compared to Figure 1, further increased a voltage stabilizing diode D7 at the VBUS power end in the circuit shown in Figure 4, the end ground connection of this voltage stabilizing diode D7, the other end links to each other with resistance R 57 and VBUS pin, its role is to voltage is stabilized in below the 5.1V, breakdown to prevent the USB3318 chip.In addition, in the circuit shown in Figure 4, in order better to prevent to produce surge voltage, the power supply that will link to each other with the VBAT pin has changed system power supply V_SYS into by the VBUS power supply, is used to provide the system voltage of 4.5V.
Though above-mentioned Fig. 1 and circuit shown in Figure 4 can reach the purpose that prevents to produce surge voltage to a certain extent,, in actual applications, also can there be a series of problem, such as:
1) can play the effect that stops electric current though add resistance, the existence meeting current sinking of resistance, this is a waste to system power dissipation.
2) adding of electric capacity is for the voltage of releiving, if but the appearance value is less, just may not have the effect of the voltage of releiving, if the appearance value is bigger, may cause the problem of surge current again.Usually, during steady operation, the VBUS power supply can provide the electric current less than 500mA, if greater than this value, then the surge current problem can occur, and its harm effect and surge voltage are similar.
3) suitable even the appearance value is selected, also can there be the possibility that surge voltage occurs, because no matter be resistance or electric capacity, its value all is that certain scope of application is arranged.Such as, the resistance of Set For Current and appearance value may be able to suppress the following surge voltage of 6.81V shown in Figure 3, but it is shown in Figure 3 only for illustrating, in actual applications, the occurrence of surge voltage also may be multiple situations such as 7.8V or 9V, so for these situations, the possible corresponding effect that just can not recur of set resistance and electric capacity.That is to say, at the VBUS power end resistance and this mode of electric capacity are set and have just reduced and produce the probability of surge voltage, but can not tackle the problem at its root.
4) though voltage stabilizing diode can play pressure stabilization function, its response time is slower, and surge voltage appears at the moment that the USB3318 chip initially inserts USB interface usually, so voltage stabilizing diode may not have effect at all.
5) in the mode shown in Figure 4, be the system voltage of 4.5V though the VBAT pin connects, found through experiments that the USB3318 chip initially inserts the moment of USB interface, system voltage also unexpected rising can occur, is higher than 6V.
Above-mentioned is that example describes with the USB chip only, in actual applications, other interface module, such as power management chip (PMU), at it with after power supply is connected, the too high problem of electric power output voltage also may occur,, also can cause damage the PMU chip if the magnitude of voltage of output exceeds the maximum voltage value that the PMU chip self can bear.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of interface arrangement, the infringement that can avoid moment that interface module is connected with power supply fully the docking port module causes because electric power output voltage is too high.
Another object of the present invention is to provide a kind of voltage processing method, the infringement that can avoid moment that interface module is connected with power supply fully the docking port module causes because electric power output voltage is too high based on above-mentioned interface arrangement.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of interface arrangement comprises: general-purpose serial bus USB chip and the VBUS power supply of powering for described USB chip, and this device also comprises: low pressure difference linear voltage regulator LDO;
The input pin of described LDO links to each other with described VBUS power supply, and output pin links to each other with the VBUS and the VBAT pin of described USB chip;
Described LDO is used for and will exports to described VBUS and VBAT pin behind the voltage delay by described VBUS power supply input;
Further be connected with the power supply of a fixed voltage value on the described VBAT pin, be connected with a resistance that is in the state of not pasting between the power supply of described fixed voltage value and the described VBAT pin.
A kind of voltage processing method based on above-mentioned interface arrangement, this method comprises:
Described LDO receives from described VBUS power source voltage, exports to described VBUS and VBAT pin after described voltage is postponed;
This method further comprises:
The power supply that on described VBAT pin, connects a fixed voltage value, and a resistance that is in the state of not pasting is set between the power supply of described fixed voltage value and described VBAT pin;
When the output voltage of described LDO output pin during greater than the voltage that requires, the described resistance that is in the state of not pasting is set to connection status, is that described VBAT pin is powered by the power supply of described fixed voltage value.
As seen, adopt technical scheme of the present invention, between power supply and interface module, be connected a LDO, utilize the output delay characteristic of LDO, avoid interface module be connected with power supply after time of occurring of too high voltages, thereby the infringement of having avoided the docking port module to be caused.
Description of drawings
Fig. 1 is the circuit diagram of existing USB3318 chip.
Fig. 2 is existing USB3318 chip internal connected mode synoptic diagram.
Fig. 3 is existing VBAT pin surge voltage synoptic diagram.
Fig. 4 is the circuit diagram that prevents to produce surge voltage after improving on the basis of Fig. 1.
Fig. 5 is the output delay characteristic synoptic diagram of existing LDO.
Fig. 6 is the composition structural representation of interface arrangement embodiment of the present invention.
Fig. 7～9 are three kinds of extended mode synoptic diagram of interface arrangement shown in Figure 6.
Figure 10 is the composition structural representation of interface arrangement preferred embodiment of the present invention.
Figure 11 is the corresponding practical circuit diagram of device shown in Figure 10.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
For solving problems of the prior art, a kind of brand-new voltage processing scheme is proposed among the present invention.In the prior art, LDO uses mainly as power supply chip, such as, in USB3318 chip shown in Figure 1, after LDO is used for voltage transitions with VBAT pin input and is 3.3V voltage, export to the VD3P3 pin.But LDO itself also possesses a kind of output delay characteristic, and as shown in Figure 5, Fig. 5 is existing LDO output delay characteristic synoptic diagram.As can be seen, LDO is not to export immediately after receiving input voltage, but certain response time is arranged, etc. the output procedure that just slowly begins self after the stabilized input voltage, until output voltage stabilization in some values.As can be seen from Figure 5, this section response time is about 20us probably.Scheme of the present invention is exactly to utilize this output delay characteristic of LDO, reaches the infringement problem that equipment caused because transient voltage is too high of preventing.
Specific implementation as shown in Figure 6.Fig. 6 is the composition structural representation of interface arrangement embodiment of the present invention, between interface module and power supply, be connected a LDO, the input pin of this LDO links to each other with power supply, and output pin links to each other with interface module, is used for exporting to interface module behind the voltage delay by the power supply input.In addition, as shown in Figure 7, can also between the output pin of LDO and interface module, be connected a resistance and be 0 ohm resistance; like this; when the voltage of LDO output pin output during greater than the voltage that requires, promptly can disconnect this 0 Ohmage, protect with the docking port module.In addition, as shown in Figure 8, can also on interface module, connect a bypass electric capacity, be used for the voltage of input interface module is carried out filtering.Have again, as shown in Figure 9, the power supply that can also on interface module, connect a fixed voltage value, such as magnitude of voltage is the power supply of 3V, be connected one between this power supply and the interface module and be in the resistance that does not paste (TBD) state, when the output voltage of LDO output pin during greater than the voltage that requires, can be set to connection status by this resistance that is in the state of not pasting, be that interface module is powered by the power supply of fixed voltage value.
As can be seen, above-mentioned Fig. 7,8 and 9 shown devices are further expanding of doing respectively on the basis of device shown in Figure 6.In actual applications, when needs are expanded device shown in Figure 6, can only adopt a kind of extended mode among Fig. 7,8 and 9, also can adopt the combination of wherein any two kinds of extended modes, can also adopt whole three kinds of extended modes simultaneously, decide on actual needs.
In addition, the interface module described in above-mentioned Fig. 6,7,8 and 9 can comprise various hardware data interface chips such as Ethernet interface chip and serial port chip, as USB chip etc.
Promptly be the USB chip below with the interface module, power supply is described in further detail scheme of the present invention for the VBUS power supply is an example:
Known in this field, surge voltage appears at the USB chip usually and initially inserts 3～10us after the USB interface in this time period, in conjunction with the output delay characteristic of LDO as can be known, if with the input of surge voltage as LDO, at 3～10us in this time period, LDO does not also begin to carry out voltage output so; And when about process 20us, when LDO began to export, input voltage was stable, had promptly avoided the time of occurrence of surge voltage fully.
Based on above-mentioned thought, Figure 10 is the composition structural representation of interface arrangement preferred embodiment of the present invention.As shown in figure 10, this device comprises: USB chip, VBUS power supply, and LDO.The input pin of LDO links to each other with the VBUS power supply, and output pin links to each other with the VBUS and the VBAT pin of USB chip; LDO is used for and will exports to VBUS and VBAT pin behind the voltage delay by the input of VBUS power supply.Wherein, the output pin of LDO directly links to each other with the VBUS pin; Be connected with a resistance between the output pin of LDO and the VBAT pin and be 0 ohm resistance R, so that follow-up debugging.
Figure 11 is the corresponding practical circuit diagram of device shown in Figure 10, supposes that the USB chip shown in Figure 10 is the USB3318 chip.As shown in figure 11, between USB3318 and VBUS power supply, be connected a LDO.This LDO comprises 5 pins, is respectively input (VIN) pin, ground connection (GND) pin, enables (EN) pin, output (VOUT) pin and does not connect (NC) pin.Wherein, the VIN pin links to each other with the VBUS power supply; The VOUT pin links to each other with the VBUS and the VBAT pin of USB3318 chip.Further; can also between VOUT pin and VBAT pin, be connected the resistance R 42 that a resistance is 0 Ω; conveniently to carry out follow-up debugging; such as; still can not prevent the generation of surge voltage if find scheme of the present invention; so then the connection at resistance R 42 places can be disconnected, to realize protection the VBAT pin.In addition, as shown in figure 11, can also on the VBAT pin, connect a bypass capacitor C 80, the shunt capacitance C that the effect of this shunt capacitance C80 is connected with the VD3P3 pin
BYPEffect identical, its appearance value can be provided with as required, as 0.1uF etc.Have again, can also on the VBAT pin, connect the power supply VCC_3V that a magnitude of voltage is 3V (certainly, also can be set to other magnitude of voltage as required), be connected with a resistance R 38 that is in the state of not pasting between this power supply VCC_3V and the VBAT pin.That is mentioned here does not paste, and is meant that the connection at resistance R 38 places is in off-state, and in other words, power supply VCC_3V does not play any effect in circuit shown in Figure 11 in fact.But why to design in this manner, it is follow-up experiment for convenience, such as, still can not prevent the generation of surge voltage if find scheme of the present invention, whether resistance R 38 can be set to connection status so, testing then directly provides voltage feasible by power supply VCC_3V for the VBAT pin.
Need to prove, in actual applications, insert the moment of USB interface except the USB chip, under other situation, artificial shake when from USB interface, extracting the USB chip, perhaps under USB chip and state that USB interface is connected, the USB chip that causes for a certain reason such as rocks at the appearance that the situation that may cause the moment break-make all may cause surge voltage, for these situations, scheme of the present invention will be suitable equally.And above-mentioned is that example describes with the USB chip only, and for other various hardware data interface chips, such as Ethernet interface chip and serial port chip etc., scheme of the present invention will be suitable equally also, and specific implementation repeats no more.
Based on said apparatus, the present invention provides a kind of voltage processing method simultaneously, comprising: be connected a LDO between power supply and interface module, the input pin of this LDO links to each other with power supply, and output pin links to each other with interface module; LDO receives from power source voltage, and exports to interface module after this voltage postponed.In addition, can also on the basis of this method, expand, such as: being connected a resistance between the output pin of LDO and the interface module is 0 ohm resistance, like this, when the voltage of LDO output pin output during greater than the voltage that requires, promptly can disconnect this 0 Ohmage, protect with the docking port module; Perhaps, on interface module, be connected with a bypass electric capacity, be used for the voltage of input interface module is carried out filtering; Have again, the power supply that can also on interface module, connect a fixed voltage value, be connected a resistance that is in the state of not pasting between the power supply of this fixed voltage value and the interface module, when the output voltage of LDO output pin during greater than the voltage that requires, can be set to connection status by this resistance that is in the state of not pasting, be that interface module is powered by the power supply of fixed voltage value.In actual applications, can only adopt a kind of extended mode wherein, also can adopt the combination of wherein any two kinds of extended modes, can also adopt whole three kinds of extended modes simultaneously, decide on actual needs.
In a word, adopt technical scheme of the present invention, utilize the output delay characteristic of LDO, avoided the time of occurrence of too high voltages after interface module is connected with power supply, thus the infringement of having avoided the docking port module to be caused.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. interface arrangement comprises: general-purpose serial bus USB chip and the VBUS power supply of powering for described USB chip is characterized in that this device also comprises: low pressure difference linear voltage regulator LDO;
The input pin of described LDO links to each other with described VBUS power supply, and output pin links to each other with the VBUS and the VBAT pin of described USB chip;
Described LDO is used for and will exports to described VBUS and VBAT pin behind the voltage delay by described VBUS power supply input;
Further be connected with the power supply of a fixed voltage value on the described VBAT pin, be connected with a resistance that is in the state of not pasting between the power supply of described fixed voltage value and the described VBAT pin.
2. device according to claim 1 is characterized in that, further is connected with a resistance between the output pin of described LDO and the described VBAT pin and is 0 ohm resistance.
3. device according to claim 1 and 2 is characterized in that, further is connected with a bypass electric capacity on the described VBAT pin.
4. device according to claim 1 is characterized in that, described fixed voltage value is 3 volts.
5. the voltage processing method based on the described interface arrangement of claim 1 is characterized in that, this method comprises:
Described LDO receives from described VBUS power source voltage, exports to described VBUS and VBAT pin after described voltage is postponed;
This method further comprises:
The power supply that on described VBAT pin, connects a fixed voltage value, and a resistance that is in the state of not pasting is set between the power supply of described fixed voltage value and described VBAT pin;
When the output voltage of described LDO output pin during greater than the voltage that requires, the described resistance that is in the state of not pasting is set to connection status, is that described VBAT pin is powered by the power supply of described fixed voltage value.
6. method according to claim 5 is characterized in that, this method further comprises:
Between described LDO output pin and described VBAT pin, be connected a resistance and be 0 ohm resistance; When the output voltage of described LDO output pin during, disconnect described 0 Ohmage greater than the voltage that requires.
7. according to claim 5 or 6 described methods, it is characterized in that this method further comprises:
On described VBAT pin, connect and connect a bypass electric capacity, the voltage of importing described VBAT pin is carried out filtering by described shunt capacitance.
8. method according to claim 5 is characterized in that, described fixed voltage value is 3 volts.
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| CN2008101171401A CN101334764B (en) | 2008-07-24 | 2008-07-24 | Interface device and voltage processing method based on the interface device |
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Denomination of invention: Interface device and voltage processing method based on the interface device Effective date of registration: 20130205 Granted publication date: 20100616 Pledgee: China Development Bank Co Pledgor: Beijing InnoFidei Technology Co. Ltd.|Beijing smartwell xunlian Polytron Technologies Inc|Anhui smartwell Communication Technology Co. Ltd. Registration number: 2013990000087 |
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Date of cancellation: 20140416 Granted publication date: 20100616 Pledgee: China Development Bank Co Pledgor: Beijing InnoFidei Technology Co. Ltd.|Beijing smartwell xunlian Polytron Technologies Inc|Anhui smartwell Communication Technology Co. Ltd. Registration number: 2013990000087 |
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Effective date of registration: 20151008 Address after: 100080, Beijing, Zhongguancun Haidian District Street 11, 100 million world wealth center, block A, 12 Patentee after: BEIJING BOXIN SHITONG TECHNOLOGY CO., LTD. Address before: 100084, No. 803, building A, Tsinghua Science and Technology Park, No. 8, Zhongguancun East Road, building 1, Haidian District, Beijing Patentee before: Beijing Chuangyi Vision Technology Co., Ltd. |
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