CN101330092A - Phase change memory device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a phase change memory device, comprising: a substrate; a plurality of bottom electrodes isolated from each other, located on the substrate; an insulating layer, spanning over a portion of the surface of any two adjacent bottom electrodes; a pair of phase change material gap walls, located on a pair of side walls of the insulating layer, wherein the pair of phase change material gap walls are respectively located on any two adjacent bottom electrodes; and a top electrode, located on the insulating layer and covering the pair of phase change material gap walls.

Description

Phase change memory device and manufacturing method thereof

technical field

The invention relates to a phase-change memory device, in particular to a phase-change memory device with high memory density.

Background technique

Phase change memory (phase change memory, PCM) is an important candidate element for stand-alone nonvolatile memory in the era below 64MB, which uses heating electrodes to change the crystalline state (crystalline or nonvolatile) of phase change memory materials. Crystalline (amorphous)) in order to achieve the purpose of storing data. How the element structure of the phase change memory can produce the best electrothermal characteristics of the element will be an important research and development direction to determine whether the phase change memory can replace the flash memory (flash memory) and become the mainstream. However, how to use the same memory semiconductor manufacturing technology to produce a non-volatile memory with higher memory density is an important development direction.

As shown in Figure 1a, the patent (US 6,501,111) of INTEL Corporation of the United States uses a cup-shaped heating electrode (Cup-Shaped Bottom Electrode) 206 as the main body to achieve a three-dimensional phase change memory device (three-dimensional PCM, 3D-PCM) 212. The contact area between the phase change material 207 and the bottom electrode has been reduced to the width of the cup-shaped heating electrode 206 and the contact area of the phase change material 207 to increase memory density. However, the above-mentioned three-dimensional phase change memory architecture encounters a bottleneck in the miniaturization of the unit memory area, and is not suitable for the semiconductor photolithography process with a macro resolution of less than 0.1 μm. As shown in Figure 1b, the patent (EP 1339111) of Italian STM company uses a phase change material coating to fill in a nanometer-sized contact hole 57 or a miniature trench (minitrench) 58 called by STM company to reduce the size of the phase change material and the cup shape. The contact area 58 of the electrode 22 is heated to meet the requirement of increasing memory density. However, there may be a problem that the hole size is too small to fill the bottom or the gap (Seam) that cannot be filled when the top of the sidewall film on both sides is joined.

Therefore, there is a need for a phase change memory device to meet the demand for increasing memory density.

Contents of the invention

The present invention provides a phase-change memory device, comprising: a substrate; a plurality of mutually isolated bottom electrodes located on the above-mentioned substrate; an insulating layer spanning part of the surface of any two adjacent bottom electrodes; A pair of phase-change material spacers are located on a pair of side walls of the above-mentioned insulating layer, wherein the above-mentioned pair of phase-change material spacers are respectively located on any two adjacent bottom electrodes above; a top electrode is located on the above-mentioned insulating layer , and cover the pair of phase change material spacers.

The present invention also provides a method for manufacturing a phase-change memory device, including: providing a substrate with a plurality of bottom electrodes thereon, each separated by a first insulating layer; forming a phase-change material structure on the first insulating layer , and straddle the partial surfaces of any two adjacent bottom electrodes, wherein the phase change material structure includes a pair of phase change material spacers, and each of the above pair of phase change material spacers is electrically connected to the adjacent Any two bottom electrodes; a top electrode is formed on the phase change material structure and electrically connected to the pair of phase change material spacers.

Description of drawings

Figures 1a and 1b are known phase change memory devices;

Figures 2a, 3a, 4a, 5a, 6a, 7a, 8a and 9a are process top views of a phase change memory device according to a preferred embodiment of the present invention;

Fig. 2b, 3b, 4b, 5b, 6b, 7b and 9b are respectively along the A-A' tangent process sectional view of Fig. 2a, 3a, 4a, 5a, 6a, 7a and 9a;

Fig. 8b is a process sectional view along the line B-B' of Fig. 8a.

Description of main component symbols

206～cup heating electrode;

207～Phase change materials;

212～three-dimensional phase change memory device;

22～cup-shaped heating electrode;

57～contact hole;

58～miniature grooves;

500～substrate;

502～the first insulating layer;

504～opening;

506～bottom electrode;

507～side wall;

508～the first direction;

510～the second direction;

512, 512a, 512b～second insulating layer;

514, 514a, 514b ~ phase change material spacer;

516, 516a～the third insulating layer;

518～Phase change material structure;

519～photoresist layer;

520～the fourth insulating layer;

522～top electrode;

530, 540～contact area;

550~phase change memory device.

Detailed ways

The phase change memory device and its manufacturing method of the preferred embodiment of the present invention will be described in more detail below using process cross-sectional diagrams. Figures 2a, 3a, 4a, 5a, 6a, 7a, 8a and 9a are process top views of a phase change memory device according to a preferred embodiment of the present invention. Figures 2b, 3b, 4b, 5b, 6b, 7b and 9b are process sectional views along the line A-A' of Figures 2a, 3a, 4a, 5a, 6a, 7a and 9a, respectively. Fig. 8b is a process sectional view along the line B-B' of Fig. 8a. In various embodiments of the present invention, the same symbols represent the same or similar elements.

Please refer to FIG. 2a, which shows a process top view of a phase-change memory device according to a preferred embodiment of the present invention; please refer to FIG. 2b, which shows a process cross-sectional view of a phase-change memory device according to a preferred embodiment of the present invention. Firstly, a substrate 500 is provided, and the substrate 500 is a silicon substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor (bulk semiconductor), strained semiconductor (strained semiconductor), compound semiconductor (compound semiconductor), silicon on insulating layer (silicon on insulator, SOI), or Other common semiconductor substrates. The substrate 500 may also be a substrate including electronic components such as transistors, diodes, bipolar junction transistors (BJTs), resistors, capacitors, and inductors.

Next, a first insulating layer 502 is formed on the substrate 500 . The first insulating layer 502 can be formed by chemical vapor deposition (chemical vapor deposition, CVD) and other film deposition methods, and can include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ) or a combination thereof. Then, cover the first insulating layer 502 with a patterned photoresist (not shown in the figure), define the formation position of the opening 504, and then perform an anisotropic etching step to remove the parts not covered by the photoresist. The first insulating layer 502 is removed until the substrate 500 is exposed, and then the patterned photoresist is removed to form an opening 504 . Next, a conductive layer (not shown) is formed on the entire surface and filled into the opening 504 . Can use such as physical vapor deposition (physical vapor deposition, PVD), sputtering (sputtering), low pressure chemical vapor deposition (low pressure CVD, LPCVD) and atomic layer chemical vapor deposition (atomic layer CVD, ALD) or electroless coating The conductive layer is formed by means of electroless plating or the like. Then, a planarization process such as chemical mechanical polishing (CMP) is performed to remove excess conductive layer to form a plurality of bottom electrodes 506 separated by the first insulating layer 502 . As shown in FIG. 2 a , in a preferred embodiment of the present invention, the top view of the bottom electrode 506 may be a square. Bottom electrode 506 may include metals, alloys, metal compounds, semiconductor materials, or combinations thereof. Bottom electrode 506 may also include base metals and their alloys (such as aluminum or copper), refractory metals and their alloys (such as cobalt, tantalum, nickel, titanium, tungsten, titanium tungsten), transition metal nitrides, refractory metal nitrides ( Such as cobalt nitride, tantalum nitride, nickel nitride, titanium nitride, tungsten nitride), metal nitride silicide (such as cobalt silicide, tantalum silicide, nickel silicide, titanium silicide, tungsten silicide), metal Silicides (such as cobalt silicide, tantalum silicide, nickel silicide, titanium silicide, tungsten silicide), polycrystalline or amorphous semiconductor materials, conductive oxide materials (such as yttrium barium copper oxide (YBCO), cuprous oxide (Cu ₂ O ), indium tin oxide (ITO)), or combinations thereof.

Referring to FIGS. 3 a and 3 b , a second insulating layer 512 is formed on the first insulating layer 502 along a first direction 508 . An insulating layer such as silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) can be formed entirely on the first insulating layer 502 and the bottom electrode 506 . Next, use a patterned photoresist (not shown) to cover the insulating layer, define the formation position of the second insulating layer 512, and then perform an anisotropic etching step to remove the parts not covered by the photoresist. insulation layer. Then, the patterned photoresist is removed to form the strip-shaped second insulating layer 512 . In a preferred embodiment of the present invention, the two sidewalls of the second insulating layer 512 respectively straddle the partial surfaces of any two adjacent bottom electrodes 506 .

Referring to FIGS. 4 a and 4 b , a pair of phase change material spacers 514 are formed on a pair of sidewalls 507 of the second insulating layer. In a preferred embodiment of the present invention, a phase change material layer (phase change film, PC film) can be conformably formed to cover the first insulating layer 502 , the bottom electrode 506 and the second insulating layer 512 . For example, physical vapor deposition (physical vapor deposition, PVD), thermal evaporation (thermal evaporation), pulsed laser deposition (pulsed laser deposition) or metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD) can be used. Form the above-mentioned phase change material layer in a manner. Then, an anisotropic etching step is performed to remove part of the phase change material layer located on the top surfaces of the first insulating layer 502, the bottom electrode 506 and the second insulating layer 512, so as to form phase change material spacers 514 . The phase change material spacers 514 may include binary, ternary or quaternary chalcogenides, such as gallium antimonide (GaSb), germanium telluride (GeTe), germanium-antimony-telluride (Ge-Sb-Te , GST), silver-indium-antimony-tellurium alloy (Ag-In-Sb-Te) or a combination thereof.

Please refer to FIGS. 5 a and 5 b , which illustrate how the third insulating layer 516 is formed. In a preferred embodiment of the present invention, the third insulating layer 516 can be formed entirely and cover the second insulating layer 512 and the phase change material spacers 514 . Next, a planarization process such as chemical mechanical polishing (CMP) is performed to remove part of the third insulating layer 516 until the phase change material spacer 514 is exposed, so as to form the second insulating layer 512 a and the phase change material spacer 514 a. The third insulating layer 516 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or a combination thereof.

Please refer to FIGS. 6 a and 6 b , which illustrate how the patterned photoresist layer 519 is formed. A photoresist layer can be fully covered, and then, a patterned photoresist layer 519 is formed along the second direction 510 by using a photolithography process, and covers part of the second insulating layer 512a, the third insulating layer 516 and Phase change material spacers 514a.

Please refer to FIGS. 7 a and 7 b , which illustrate the formation of the phase change material structure 518 according to a preferred embodiment of the present invention. The portion of the second insulating layer 512 a , the third insulating layer 516 and the phase change material spacers 514 a not covered by the patterned photoresist layer 519 can be removed by anisotropic etching. Finally, the patterned photoresist layer 519 is removed to form the third insulating layer 516a and a plurality of disconnected phase change material structures 518, wherein the phase change material structures 518 include the second insulating layer 512b and the phase change material Spacer wall 514b. As shown in Figures 7a and 7b, the second insulating layer 512b of the phase change material structure 518 is across the partial surface of any two adjacent bottom electrodes 506, and each phase change material gap of the phase change material structure 518 The wall 514b is respectively located on any two adjacent bottom electrodes 506, wherein the contact area 530 between the phase change material spacer 514b and the bottom electrode 506 is smaller than the area of the bottom electrode 506, and the phase change material spacer 514b and the bottom electrode 506 The contact area 530 can be controlled by the film thickness of the phase change material spacer 514b and the width of the patterned photoresist layer 519. Compared with the heating electrode formed by the photolithography process in the known technology, the contact area can be minimized , to control more precise effects.

Please refer to FIGS. 8 a and 8 b , which illustrate the formation of the fourth insulating layer 520 . In a preferred embodiment of the present invention, the fourth insulating layer 520 can be formed entirely and cover the phase change material structure 518 . Next, a planarization process such as chemical mechanical polishing (CMP) is performed to remove part of the fourth insulating layer 520 until the phase change material structure 518 is exposed. The fourth insulating layer 520 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or a combination thereof. In a preferred embodiment of the present invention, the first insulating layer 502, the second insulating layer 512b, the third insulating layer 516a and the fourth insulating layer 520 may comprise the same material. As shown in Figures 8a and 8b, the phase change material structures 518 are isolated from each other. If viewed along the first direction 508, each phase change material structure 518 is isolated by the fourth insulating layer 520; if viewed along the second direction 510, each phase change material spacer 514b is isolated by the second insulating layer 512b or The third insulating layer 516a is isolated. Therefore, when the state of the phase change material spacer 514b of one of the phase change material structures 518 changes, it will not affect another adjacent phase change material spacer 514b, causing misjudgment of stored data.

Referring to FIGS. 9 a and 9 b , a top electrode 522 is formed on the phase change material structure 518 and electrically connected to the phase change material spacer 514 b. For example, physical vapor deposition (physical vapor deposition, PVD), sputtering (sputtering), low pressure chemical vapor deposition (low pressure CVD, LPCVD) and atomic layer chemical vapor deposition (atomic layer CVD, ALD) or electroless A conductive layer is formed comprehensively by means of electroless plating or the like. Next, use a patterned photoresist (not shown) to cover the conductive layer to define the formation position of the top electrode 522, and then perform an anisotropic etching step to remove the conductive layer not covered by the photoresist. layer. Then, the patterned photoresist is removed to form the top electrode 522 . The contact area 540 of the phase change material spacer 514b and the top electrode 522 is smaller than the area of the top electrode 522, and the contact area 540 of the phase change material spacer 514b and the top electrode 522 can be determined by the film thickness of the phase change material spacer 514b and the patterned light. The control of the width of the resist layer 519 can achieve the effect of minimizing the contact area and controlling more precisely, compared with the heating electrode formed by the photolithography process in the known technology. The top electrode 522 may include metals, alloys, metal compounds, semiconductor materials, phase change materials, or combinations thereof. The top electrode 522 may also include base metals and their alloys (such as aluminum or copper), refractory metals and their alloys (such as cobalt, tantalum, nickel, titanium, tungsten, titanium tungsten), transition metal nitrides, refractory metal nitrides ( Such as cobalt nitride, tantalum nitride, nickel nitride, titanium nitride, tungsten nitride), metal nitride silicide (such as cobalt silicide, tantalum silicide, nickel silicide, titanium silicide, tungsten silicide), metal Silicides (such as cobalt silicide, tantalum silicide, nickel silicide, titanium silicide, tungsten silicide), polycrystalline or amorphous semiconductor materials, conductive oxide materials (such as yttrium barium copper oxide (YBCO), cuprous oxide (Cu ₂ O ), indium tin oxide (ITO)), or combinations thereof. After the above process, the phase change memory device 550 of the preferred embodiment of the present invention is formed.

In a preferred embodiment of the present invention, each top electrode 522 is electrically connected to two phase change material spacers 514b, and each phase change material spacer 514b is electrically connected to any two adjacent bottom electrodes 506 Above, each bottom electrode 506 and top electrode 522 form a phase change memory bit (bit), so each phase change memory device 550 has two bits (bit).

The main components of the phase change memory device 550 in the preferred embodiment of the present invention include a substrate 500 ; a plurality of bottom electrodes 506 isolated from each other are located on the substrate 500 . A phase change material structure 518 straddling the partial surfaces of any two adjacent bottom electrodes 506, wherein the phase change material structure 518 includes a second insulating layer 512b, straddling any two adjacent bottom electrodes 506 On part of the surface of the bottom electrode 506; a pair of phase change material spacers 514b are located on the pair of side walls 507 of the second insulating layer 512b, wherein the pair of phase change material spacers 514b are respectively located on any of the above-mentioned adjacent on the two bottom electrodes 506 . A top electrode 522 is located on the phase change material structure 518 and covers the pair of phase change material spacers 514b.

The phase change memory device of the preferred embodiment of the present invention has the following advantages: (1) The contact area between the phase change material spacer and the heating electrode can be determined by the film thickness of the phase change material spacer and the patterned photoresist that defines the phase change material structure. The width control of the etchant layer, compared with the heating electrode formed by the photolithography process in the known technology, can achieve the effect of minimizing the contact area and controlling more accurately, and can greatly reduce the area of the memory to achieve high memory efficiency. Density requirements. (2) Adjacent phase-change material structures are isolated by insulating layers, and will not affect each other to cause misjudgment of stored data. (3) The phase change material spacer is directly in contact with the bottom electrode and the top electrode, replacing the heating electrode in the known phase change memory device, so as to achieve the effect of self-heating. (4) The reset current I _reset of the phase-change memory (the current required to make the phase-change material change into an amorphous state (amorphous)) and the write current I _set (the current required to make the phase-change material change into a crystalline state (crystalline) ) can be controlled by the film thickness of the phase change material spacer and the width of the patterned photoresist layer defining the phase change material structure, so as to meet different requirements. (5) The process of the phase change memory device of the present invention is compatible with the conventional complementary metal-oxide-silicon transistor (CMOS transistor) process, and no special process needs to be developed.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (17)

1. A phase change memory device, comprising: Substrate; a plurality of bottom electrodes isolated from each other on the substrate; an insulating layer spanning part of the surfaces of any two adjacent bottom electrodes; A pair of phase change material spacers are located on a pair of sidewalls of the insulating layer, wherein the pair of phase change material spacers are respectively located on any two adjacent bottom electrodes; and The top electrode is located on the insulating layer and covers the pair of phase change material spacers. 2. The phase change memory device as claimed in claim 1, wherein the top view of the bottom electrode is a square. 3. The phase change memory device as claimed in claim 1, wherein the bottom electrode comprises metal, alloy, metal compound, semiconductor material or a combination thereof. 4. The phase change memory device as claimed in claim 1, wherein the top electrode comprises metal, alloy, metal compound, semiconductor material or a combination thereof. 5. The phase change memory device as claimed in claim 1, wherein the insulating layer comprises silicon oxide, silicon nitride or a combination thereof. 6. The phase change memory device as claimed in claim 1, wherein a contact area between the phase change material spacer and the bottom electrode is smaller than an area of the bottom electrode. 7. The phase change memory device as claimed in claim 6, wherein a contact area between the phase change material spacer and the top electrode is smaller than an area of the top electrode. 8. A method of manufacturing a phase change memory device, comprising the following steps: providing a substrate with a plurality of bottom electrodes on it, respectively separated by a first insulating layer; A phase-change material structure is formed on the first insulating layer, and straddles the partial surfaces of any two adjacent bottom electrodes, wherein the phase-change material structure includes a pair of phase-change material spacers, and the pair of phase-change materials The material spacers are respectively electrically connected to any two adjacent bottom electrodes; and A top electrode is formed on the phase change material structure and electrically connected to the pair of phase change material spacers. 9. The method of manufacturing a phase change memory device according to claim 8, forming the phase change material structure further comprises: forming a second insulating layer along a first direction on the first insulating layer, wherein the two sidewalls of the second insulating layer respectively span part of the surfaces of any two adjacent bottom electrodes; conformally forming a phase change material layer covering the first insulating layer and the second insulating layer; An anisotropic etching step is performed to remove the phase change material layer located on the top surfaces of the first insulating layer and the second insulating layer, so as to form the pair of phase change material spacers on the pair of sidewalls of the second insulating layer ; forming a third insulating layer comprehensively and covering the second insulating layer and the pair of phase change material spacers; performing a planarization process, removing part of the third insulating layer until exposing the pair of phase change material spacers; forming a patterned photoresist layer along the second direction, and covering part of the second insulating layer, the third insulating layer and the pair of phase change material spacers; removing portions of the second insulating layer, the third insulating layer, and the pair of phase change material spacers not covered by the patterned photoresist layer; and The patterned photoresist layer is removed. 10. The method of manufacturing a phase change memory device according to claim 8, further comprising: before forming the top electrode: forming a fourth insulating layer comprehensively and covering the phase change material structure; and A planarization process is performed to remove part of the fourth insulating layer until the phase change material structure is exposed. 11. The method of manufacturing a phase change memory device as claimed in claim 8, wherein the bottom electrode is a square in a top view. 12. The method of manufacturing a phase change memory device as claimed in claim 10, wherein the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer comprise the same material. 13. The manufacturing method of a phase change memory device as claimed in claim 10, wherein the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer comprise silicon oxide, silicon nitride or combination. 14. The method of manufacturing a phase change memory device as claimed in claim 8, wherein the bottom electrode comprises metal, alloy, metal compound, semiconductor material or a combination thereof. 15. The method of manufacturing a phase change memory device as claimed in claim 8, wherein the top electrode comprises metal, alloy, metal compound, semiconductor material or a combination thereof. 16. The method of manufacturing a phase change memory device as claimed in claim 8, wherein a contact area between the phase change material spacer and the bottom electrode is smaller than the area of the bottom electrode. 17. The method of manufacturing a phase change memory device as claimed in claim 8, wherein a contact area between the phase change material spacer and the top electrode is smaller than that of the top electrode.

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