CN101329915A - Method of programming a storage device - Google Patents

Abstract

A method of programming a memory device is provided. The method includes: performing a program voltage applying operation; performing a verifying operation, wherein a plurality of verifying operations are continuously performed after the program voltage applying operation.

Description

Method of programming a memory device

This application claims Korean Patent Application No. 10-2007-0060052 filed with the Korean Intellectual Property Office on June 19, 2007 and Korean Patent Application No. 10-2008-0045520 filed with the Korean Intellectual Property Office on May 16, 2008 Priority of the application, the disclosure of which is hereby incorporated by reference in its entirety.

technical field

Exemplary embodiments relate to a method of programming a flash memory device, for example, to a method of programming a flash memory device that more effectively reduces threshold voltage dispersion (dispersion) in a programmed state. method.

Background technique

Floating gate flash memory is generally used as a large-capacity nonvolatile memory. To operate, floating gate flash memory stores charge in a floating gate formed of polysilicon.

The memory cell of the floating gate flash memory can be divided into a single-level cell (SLC) that records two recording states of "1" and "0" and a recording state of four or more (for example, "11", " 10", "01" and "00") for multi-level cells (MLC).

MLC technology is used to manufacture high-capacity NAND and NOR flash memory.

In the MLC operation, the shifts of the threshold voltages Vth of the cells respectively corresponding to the recording states must be relatively low to identify the recording states respectively.

A flash memory device may use an incremental step pulse programming (ISPP) method of uniformly increasing a programming voltage V _pgm and repeatedly applying the increased programming voltage to reduce the threshold voltage distribution among cells.

As is known, in the ISPP method, programming voltage pulses are applied with gradually increasing amplitudes [Delta]V _pgm . The process of applying verification voltage pulses to verify the threshold voltage of the memory cell is repeated so that the threshold voltage of the memory cell reaches a desired or predetermined value. A plurality of memory cells constituting a flash memory may have an initial threshold voltage shift. Therefore, an ISPP method has been proposed to bring a plurality of memory cells to a desired or predetermined threshold voltage in consideration of an initial threshold voltage shift of memory cells.

However, the coupling between cells (eg, coupling between floating gates) increases as the size of the cells of a flash memory using floating gates decreases. Therefore, it is more difficult to control the shift of the threshold voltage.

In order to reduce coupling between cells, charge trap flash (CTF) memory has been developed, which uses an insulating layer that traps charges (for example, a Si ₃ N ₄ layer configured to store charges) instead of a floating gate.

However, in a CTF memory using an insulating layer to trap charges, after programming is performed, the charges trapped in the charge trap layer migrate. Therefore, the threshold voltage value varies with time after programming is performed.

If programming is performed using the ISPP method, the variation of the threshold voltage value with time makes the control of the shift of the threshold voltage value more difficult.

As described above, if the threshold value varies with time, an error occurs in an operation of performing programming and verifying a programmed state after a desired or predetermined time elapses.

The shift of the threshold voltage value of the programmed state in the ISPP method increases due to a verify error.

For example, if the threshold voltage changes over time, the threshold voltage may reach the target value after more time has elapsed. However, even in this case, an error that the verification result is that the memory cell has not reached the target threshold voltage may occur. If the memory cell is verified not to have reached the target threshold voltage, then a program voltage increased by ΔV _pgm is applied to program the memory cell. Therefore, over program of threshold voltage increase occurs. Therefore, the shift of the threshold voltage in the programmed state increases.

Contents of the invention

Exemplary embodiments provide a method of programming a memory device, the method including: performing a program voltage applying operation; and performing a verify operation, wherein a plurality of verify operations are consecutively performed after the program voltage applying operation.

According to an exemplary embodiment, a pair of operations including one voltage applying operation and a plurality of verifying operations may be repeatedly performed while gradually increasing the magnitude of the program voltage until the memory cell reaches a set threshold voltage.

According to an exemplary embodiment, the magnitudes of the verification voltages used when consecutively performing a plurality of verification operations may be the same.

According to an exemplary embodiment, the magnitude of the verification voltage used when consecutively performing a plurality of verification operations may be continuously reduced.

According to an exemplary embodiment, the verification voltage may gradually decrease by the same magnitude.

According to an exemplary embodiment, the verification voltage may be gradually decreased by about 0.05V to 0.35V.

According to example embodiments, the memory cell may be one of a floating gate type memory cell and a charge trap type memory cell.

According to an exemplary embodiment, a plurality of verification operations may be performed at regular intervals.

According to an exemplary embodiment, the time interval may be in a range between approximately 1 μs and 100 μs.

According to an exemplary embodiment, the method may further include: performing a first program operation including a verify operation using a first verify voltage; performing a verify operation including using a second verify voltage greater than the first verify voltage The second program operation, wherein, after the program voltage is applied to the memory cell, each time the program voltage application operation is performed, a plurality of verification operations are continuously performed, wherein, in the first program operation, repeated execution includes one time of the program voltage A pair of operations of applying operation and one verifying operation, until the verifying operation using the first verifying voltage, in the second programming operation, a pair of operations including one program voltage applying operation and a plurality of verifying operations is repeatedly performed , until the verification operation using the second verification voltage is passed.

According to an exemplary embodiment, the first verification voltage may be lower than the second verification voltage by about 0.2V to 1.0V.

According to example embodiments, the second program operation may be performed on the memory cells passed the verify operation using the first verify voltage.

According to an exemplary embodiment, a first program operation may be performed on memory cells in an erased state so that the memory cells in the erased state are programmed into an intermediate program state, and a second program operation may be performed on the memory cells in the intermediate program state to The memory cells in the intermediate programmed state are programmed to the final programmed state.

According to example embodiments, memory cells after a final programmed state may include three or more layers.

According to an exemplary embodiment, a first program operation may be performed on memory cells in an erased state so that the memory cells in the erased state are programmed into an intermediate program state, and a second program operation may be performed on the memory cells in the intermediate program state to The memory cells in the intermediate programming state are programmed to the final programming state to increase the minimum threshold voltage of the intermediate programming state and reduce the threshold voltage distribution range.

According to an exemplary embodiment, a memory cell may be a 4-level cell, an erased state may be a '11' state, and a final programmed state may be at least one of a '01' state, a '00' state, and a '10' state.

According to exemplary embodiments, in each of the first program operation and the second program operation, a pair of operations including a program voltage applying operation and a verifying operation may be repeatedly performed while gradually increasing a program voltage.

According to example embodiments, the program voltage increment in each step in the second program operation may be lower than the program voltage increment in each step in the first program operation.

According to an exemplary embodiment, the method may further include performing a third program operation including a verify operation using a verify voltage lower than the first verify voltage, wherein repeatedly performing the program on the memory cells in the erased state includes one time of programming. A pair of operations of a voltage applying operation and a verification operation until a memory cell in an erased state is programmed to an intermediate programming state by a verification operation using a verification voltage lower than the first verification voltage, wherein the second A programming operation and a second programming operation are successively applied to the memory cells in the intermediate programming state, so that the memory cells in the intermediate programming state are programmed into the final programming state, to increase the minimum threshold voltage of the programming state and reduce the threshold voltage distribution range .

According to an exemplary embodiment, in each of the third program operation, the second program operation, and the first program operation, a program voltage application operation and a verification operation may be repeatedly performed while gradually increasing the program voltage. pair operation.

According to an exemplary embodiment, the program voltage increment in each step in the second program operation is lower than the program voltage increment in each step in the first program operation.

According to an exemplary embodiment, the memory cell may be a 4-level cell, the erase state may be a '11' state, and the intermediate program state may be at least one of a '01' state, a '00' state, and a '10' state.

According to an exemplary embodiment, a memory cell in an erased state may be applied with a first programming operation such that the memory cell in an erased state is programmed into an intermediate programming state as a dummy state, and a memory cell in an erased state may be applied with a second programming operation. A program operation is performed to program memory cells in an erased state to a first program state, and a second program operation may be applied to memory cells in a dummy state to program memory cells in a dummy state to a second or third program state.

According to an exemplary embodiment, the memory cell may be a 4-layer unit, the erase state may be a "11" state, and the first to third programming states may be at least one of a "01" state, a "00" state, and a "10" state. One, and different from each other.

According to an exemplary embodiment, in each of the first program operation and the second program operation, a pair of operations including a program voltage applying operation and a verifying operation may be repeatedly performed while gradually increasing the magnitude of the program voltage. .

Description of drawings

The above and/or other aspects and advantages will become clearer and easier to understand through the following detailed description of exemplary embodiments in conjunction with the accompanying drawings, wherein:

1 is a schematic cross-sectional view of a charge trap flash (CTF) memory device performing a program operation using a program method according to an exemplary embodiment;

2 is a circuit diagram of a NAND type flash memory as an example of a flash memory employing a programming method of an exemplary embodiment;

3 is a flowchart of a programming operation of a programming method according to an exemplary embodiment;

4 and 5 illustrate example waveforms of voltage pulses applied in the programming method of FIG. 3 according to exemplary embodiments;

6 shows example waveforms of voltage pulses applied to a selected word line (WL) in the case of performing programming using a general ISPP method;

7 is an example graph illustrating changes in threshold voltage during programming of a CTF memory cell with respect to the example waveforms of FIG. 6;

8A and 8B are example graphs illustrating programming schemes and threshold voltage shifts of memory cells during programming using conventional programming methods;

9A and 9B are example graphs illustrating programming schemes and threshold voltage shifts of memory cells during programming using the programming method of an example embodiment;

FIG. 10 is a flowchart of a programming operation of a programming method according to another exemplary embodiment;

11 and 12 show example waveforms of voltage pulses applied to selected WLs in the case of programming using the programming method of FIG. 10 according to an exemplary embodiment;

13A and 13B are schematic diagrams for explaining a multi-level cell (MLC) programming method according to an exemplary embodiment;

14A and 14B are schematic diagrams for explaining an MLC programming method according to another exemplary embodiment;

FIG. 15 is a circuit diagram showing a part of a NAND string in a block having multiple NAND strings.

Detailed ways

Exemplary embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to example embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

It should be understood that when an element is referred to as being "on," "connected" or "coupled" to another element, the element may be directly on, connected or coupled to the other element. another component, or there may be intermediate components. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be referred to as These terms are limited. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

Spatially relative terms (e.g., "below," "beneath," "underneath," "over," "above," etc.) are used herein to easily describe The relationship of one component or feature to another component or feature shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The terminology used herein is for describing particular embodiments only and is not intended to be limiting of example embodiments. Singular forms used herein also include plural forms unless the context clearly dictates otherwise. It should also be understood that when the term "comprising" is used in this specification, it means the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude one or more other features, integers, steps, Operations, elements and/or components exist or are added.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which exemplary embodiments belong. It should also be understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted to have a meaning consistent with the meaning of the term in the context of the relevant art, and should not be idealized or overly explain formally.

Exemplary embodiments will now be described, which are illustrated in the drawings, wherein like reference numerals refer to like parts throughout.

FIG. 1 is a schematic cross-sectional view of a charge trap flash (CTF) memory device in which a program operation may be performed using a program method of an exemplary embodiment. A CTF storage device may constitute a storage unit of a CTF memory.

Referring to FIG. 1 , a CTF memory device 10 may include a substrate 11 and/or a gate structure 20 formed on the substrate 11 .

A first doped region 13 and a second doped region 15 doped with desired or predetermined conductive dopants may be formed on the substrate 11 . One of the first doped region 13 and the second doped region 15 may serve as the drain D, and the other of the first doped region 13 and the second doped region 15 may serve as the source S.

The gate structure 20 may include a channel insulating layer 21 formed on the substrate 11 , a charge trap layer 23 formed on the channel insulating layer 21 , and/or a blocking insulating layer 25 formed on the charge trap layer 23 . A control gate 27 may be formed on the blocking insulating layer 25 . Reference numeral 19 of FIG. 1 denotes spacers that may be formed on sidewalls of the blocking insulating layer 25 , the charge trap layer 23 and/or the channel layer 21 .

The channel insulating layer 21 may be a layer for tunneling charges and/or may be formed on the substrate 11 to contact the first doped region 13 and the second doped region 15 . The channel insulating layer 21 may be formed of a tunnel oxide layer (eg, SiO ₂ ), various high-k oxides, or a combination of the tunnel oxide layer and various high-k oxides.

Alternatively, the channel insulating layer 21 may be formed of a silicon nitride (eg, Si ₃ N ₄ ) layer. For example, a silicon nitride layer can be formed so that the density of impurities is relatively low (eg, the density of impurities in silicon nitride is comparable to that of a silicon oxide layer) and the interference characteristics with silicon are better.

The channel insulating layer 21 may be formed as a double layer including a silicon nitride layer and an oxide layer.

The channel insulating layer 21 may be formed of oxide or nitride in a single-layer structure, or may be formed of materials having different energy band gaps in a multi-layer structure.

The charge trap layer 23 may be a region that traps charges to store information. The charge trap layer 23 may be formed to include one of polysilicon, nitride, high-k dielectric, and nanodots.

For example, the charge trap layer 23 may be formed of a nitride such as Si ₃ N ₄ , or a high-k oxide such as HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfSiON, HfON, or HfAlO.

The charge trapping layer 23 may include a plurality of nanodots discontinuously arranged as charge trapping locations. For example, nanodots can be nanocrystals.

The blocking insulating layer 25 may prevent charges from migrating upward toward the control gate 27 through the position where the charge trap layer 23 is formed. The blocking insulating layer 25 may be formed of an oxide layer.

The blocking insulating layer 25 may be formed of SiO ₂ or a high-k material having a higher dielectric constant than the channel insulating layer 21 (for example, Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ , or ZrO ₂ ). . The blocking insulating layer 25 may be formed in a multilayer structure. For example, the blocking insulating layer 25 may include two or more layers, for example, an insulating layer formed of a general insulating material (eg, SiO ₂ ) and a material having a higher dielectric constant than the channel insulating layer 21. high-k dielectric layer.

The control gate 27 may be formed of a metal layer. For example, the control gate 27 may be formed of aluminum (Al). Alternatively, the control gate 27 may be formed of a metal (eg, Ru or TaN), or a silicide material (eg, NiSi), or the like. Metal and silicide materials are commonly used to form control gates of semiconductor memory devices.

Programming may be performed to inject electrons into the above-described CTF memory device and trap electrons at trapping positions of the charge trap layer 23 so that the CTF memory device has a threshold voltage of a programmed state. Erasing may be performed to inject holes into the CTF memory device to recombine the holes with electrons to erase the electrons so that the CTF memory device has a threshold voltage of an erased state.

Accordingly, a memory cell of a flash memory device may have two states, eg, a programmed state and an erased state. The on state may be called an erase state, and the off state may be called a program state. In the on state, the threshold voltage of the flash memory cell may be lowered to use the voltage applied to the control gate to flow current into the drain connected to the bit line during read. In the OFF state, the threshold voltage of the flash memory cell can be increased to inhibit current flow into the drain using the voltage applied to the control gate during read.

The programming method of the exemplary embodiments may be applied to programming a CTF memory using the above-described CTF memory device as a memory cell.

The programming method of the exemplary embodiments may be applied to programming a floating gate type flash memory using a floating gate type flash memory device including a floating gate and a control gate as a memory cell. A floating gate type flash memory device is well known, and thus a detailed description and description of the floating gate type flash memory device will be omitted here.

FIG. 2 is a circuit diagram of a NAND type flash memory as an example of a flash memory employing a programming method of an exemplary embodiment. Referring to FIG. 2, a flash memory may include a plurality of cell strings. However, only two cell strings 30 and 31 are shown exemplarily in FIG. 2 .

Each of the cell strings 30 and 31 may include a plurality of memory cell arrays sharing source and drain electrodes with adjacent memory cells. The memory cells of each of the cell strings 30 and 31 may have a structure as shown in FIG. 1 . Each of the memory cells may be one of the above-mentioned CTF memory cells and floating gate flash memory cells.

Each of the cell strings 30 and 31 may include a ground selection transistor (GST), a plurality of memory cells, and/or a string selection transistor (SST) connected in series with each other. One end of each of the cell strings 30 and 31 may be connected to a bit line BL, and the other end of each of the cell strings 30 and 31 may be connected to a common source line (CSL). GTS can be connected to CSL and SST can be connected to bit line BL.

A word line (WL) can be connected to the control gates of a plurality of memory cells, intersecting cell strings 30 and 31, a string select line (SSL) can be connected to the gates of SSTs, and/or a ground select line (GSL) can be connected to Gate of GST.

Data programmed in memory cells may vary according to the voltage of the bit line BL. If the voltage of the bit line BL is the power supply voltage Vcc, in the memory cell, programming of data may be inhibited. If the voltage of the bit line is the ground voltage 0V, data can be programmed in the memory cell. FIG. 2 shows an operation state in which a ground voltage 0V is applied to the bit line BLn _-1 and a power supply voltage VCC is applied to the bit line _BLn .

In a program operation, a program voltage V _pgm may be applied to a selected WL, eg, WL WL29 . The pass voltage Vpass may be applied to unselected WLs, eg, WLs WL31 , WL30 , WL28 . . . WL0 . A voltage gradually increasing in increments of 0.5V from a base voltage of about 16V may be applied as a programming voltage V _pgm and/or a voltage of about 9V may be applied as a pass voltage V _pass .

Memory cells corresponding to the bit line BLn-1 supplied with the ground voltage 0V can be programmed on the selected WL WL29. In FIG. 2, memory cell A is programmed.

A method of programming a flash memory device according to an exemplary embodiment is shown in FIG. 3 , and FIGS. 4 and 5 show example waveforms of voltage pulses applied to selected WLs during programming. FIG. 4 illustrates a verification voltage V _ref having a constant magnitude and being applied three times between programming voltages having gradually increasing magnitudes, according to an exemplary embodiment. FIG. 5 shows verify voltages having gradually decreasing amplitudes and being applied three times between gradually increasing programming voltages.

A program method according to example embodiments may include applying a program voltage V _pgm to selected WLs (eg, WL WL29 ), programming memory cells and/or verifying programmed memory cells.

According to an exemplary embodiment, the program method may be performed using an ISPP method of programming by gradually increasing the magnitude of a program voltage as shown in FIGS. 4 and 5 .

The program voltage applying operation and the verifying operation may be repeatedly performed as the magnitude of the program voltage gradually increases until a programmed memory cell (eg, memory cell A of FIG. 2 ) reaches a set threshold voltage.

A verify operation of a program method according to an exemplary embodiment may be performed as follows. In a verify operation, a verify voltage may be applied to programmed memory cells by applying a program voltage V _pgm to verify programmed memory cells. If it is determined that the programmed memory cell has not reached the set threshold voltage according to the result of the verify operation, the verify voltage is applied again to verify the programmed memory cell again. Reaching the set threshold voltage means that the threshold voltage is equal to or exceeds the set threshold voltage.

As described above, the programming method of the exemplary embodiments may include a verify operation performed by applying a verify voltage pulse a plurality of times in succession after applying the program voltage pulse.

The maximum number of verification operations performed every time the program voltage applying operation is performed may be n (where n is a number equal to or greater than 2) times. If it is determined that the programmed memory cell has reached the set threshold voltage during the verification operations up to n times, the programming of the memory cell ends. If it is determined that the programmed memory cell has not reached the set threshold voltage through n times of verify operations, the program voltage increased by ΔV _pgm may be applied again to repeat the program and verify operations.

A pair of operations including a program voltage applying operation and a plurality of verifying operations may be repeated with a program voltage gradually increased until a selected memory cell reaches a set threshold voltage.

In FIGS. 4 and 5 , an exemplary basic program voltage of 16V is gradually increased by 0.5V to perform a program operation.

If the ISPP method is applied, the possibility that the memory cell can reach the set threshold voltage by one program voltage application operation is relatively small. Accordingly, a process comprising applying a program voltage to program a memory cell and applying a verify voltage to the programmed memory cell at least twice consecutively to verify the programmed memory cell may be performed in a programming scheme for each memory cell. At least one or more times.

A programming process of a programming method according to an exemplary embodiment will now be described in more detail with reference to FIG. 3 .

In operation S10, a programming mode may start. At operation S20, data may be input to select a specific WL, for example, WL WL29.

In operation S30, a program voltage V _pgm may be applied to the selected WL. Memory cell A corresponding to the bit line connected to the selected WL and to which the ground voltage is applied may be programmed.

A verify voltage may be applied to selected WLs to verify programmed memory cells A.

For example, a first verification voltage may be applied to the programmed memory cell A to verify the programmed memory cell A in operation S40. In operation S50, it may be determined whether the programmed memory cell A has reached a set threshold voltage.

If it is determined in operation S50 that the programmed memory cell A has reached the set threshold voltage and is thus programmed to a desired or predetermined level, then in operation S110, programming of the memory cell A may end. If it is determined in operation S50 that the programmed memory cell A has not reached the set threshold voltage, a second verification voltage may be applied to verify the programmed memory cell A again in operation S60. In operation S70, it may be determined whether the programmed memory cell A has reached a set threshold voltage.

If it is determined in operation S70 that the programmed memory cell A has reached the set threshold voltage, then in operation S110, programming of the programmed memory cell A may end.

If it is determined in operation S70 that the programmed memory cell A has not reached the set threshold voltage, the verify voltage may be applied again to verify the programmed memory cell A again.

If no verify operation determines that the programmed memory cell A has reached the set threshold voltage, the process is performed up to a verify operation using the nth verify voltage. In operation S80, an nth verify voltage is applied to verify the programmed memory cell A again. In operation S90, it is determined whether the programmed memory cell A has reached a set threshold voltage.

If it is determined in operation S90 that the programmed memory cell A has not reached the set threshold voltage, in operation S100 the program voltage V _pgm may be increased by ΔV _pgm . In operation S30, an increased program voltage V _pgm may be applied to the selected WL to program memory cell A again.

In FIG. 3, if the verify operation is set to be performed only twice every time the program voltage applying operation is performed, the verify process may be performed only up to the verify operation using the second verify voltage. In a case where the verifying operation is set to be performed only twice every time the program voltage applying operation is performed, the nth verifying voltage may be equal to the second verifying voltage. If it is determined that the memory cell A has not reached the set threshold voltage according to the result of the verify operation using the second verify voltage, the increased program voltage V _pgm may be applied to program the memory cell A again.

As described above, if it is determined that memory cell A has reached the set threshold voltage by sequentially applying verify voltages, programming of memory cell A may end. If it is determined that the memory cell A has not reached the set threshold voltage, reapplying the verification voltage to verify the memory cell A again may be performed up to n (where n is a number equal to or greater than 2) times.

For example, before increasing the program voltage by ΔV _pgm in order to perform another program operation, a plurality of verify operations may be continuously performed by continuously applying the first through nth verify voltages at desired or predetermined time intervals. The desired or predetermined interval between successive verify operations may range between approximately 1 μs and 100 μs.

If the verify operation using the nth verify voltage determines that the programmed memory cell A has not reached the set threshold voltage, the program voltage V _pgm may be increased by ΔV _pgm and reapplied to the selected WL to again Cell A is programmed. The verification operation described above may be performed after programming of memory cell A. Referring to FIG.

If it is determined during any of the n verification operations that the programmed memory cell A has reached the set threshold voltage, programming of the memory cell A may end in operation S110.

As described above, in the program method according to example embodiments, a verify voltage may be continuously applied to programmed memory cells to perform a verify operation a plurality of times.

For comparison with exemplary embodiments, FIG. 6 shows example waveforms of voltage pulses applied to selected WLs in the case of performing programming using a general ISPP method. Referring to FIG. 6, after the program voltage is applied to program the memory cells, the verify voltage _Vver is applied to verify the memory cells. If it is determined that the memory cell has not reached the desired or predetermined threshold voltage, the programming voltage is increased by the desired or predetermined magnitude and reapplied to reprogram and reverify the memory cell. As described above, in the general ISPP method, in the case of gradually increasing a program voltage, a verify operation is performed every time a program voltage application operation is performed until a memory cell is programmed to reach a set threshold voltage.

According to the programming method of the exemplary embodiment, in the case of gradually increasing the programming voltage, every time the programming voltage applying operation is performed, at least two or more verifying operations may be continuously performed until the memory cell reaches a set threshold voltage.

According to an exemplary embodiment, every time a program application operation is performed, the verify voltage pulse may be continuously applied two or three times to continuously perform the verify operation two, three or more times.

In FIGS. 4 and 5 , every time the program voltage application operation is performed once, the verification voltage is continuously applied three times to continuously perform the verification operation three times.

As described above, according to the program method of the exemplary embodiment, every time a program voltage applying operation is performed, a verify operation may be continuously performed two or more times. The magnitude of the verification voltage applied during multiple consecutive executions of the verification operation may be equal to a constant magnitude, such as shown in FIG. 4 , or may decrease continuously as shown in FIG. 5 .

As shown in FIG. 4, if the verify voltage is continuously applied with the same magnitude to perform the verify operation multiple times continuously through the verify repeated twice or more, there is a threshold value that increases with time after the program voltage pulse is applied. voltage and will pass the verification memory cells do not need to be reprogrammed. Therefore, memory cells may not be overprogrammed. Accordingly, the offset of the programming threshold voltage can be adjusted to be narrower.

As shown in FIG. 5, if the verification operation is continuously performed multiple times, the verification voltage may gradually decrease by the same magnitude. For example, the verification voltage may be gradually reduced by a desired or predetermined (eg, the same) magnitude within a range between approximately 0.05V and 0.35V, such as within a range between approximately 0.1V and 0.2V. For example, the difference between the first and nth verify voltages may be less than an increase in the threshold voltage during one program operation.

If the magnitude of the verify voltage is gradually reduced as described above, memory cells whose threshold voltages are lower than an optimal (or set) threshold voltage of optimally programmed memory cells may pass the verify operation.

For example, if the first verification voltage among the first to nth verification voltages which are sequentially and continuously applied and gradually decreased is set equal to the set threshold voltage, the second to nth verification voltages may be less than Set the threshold voltage, where n is a number equal to or greater than 2.

If the memory cell is determined to pass the verification during the verification operation using the second to n th verification voltages, the memory cell may have a threshold voltage less than the set threshold voltage.

For example, if the set threshold voltage is 3V and the verify operation is set to be performed twice consecutively using gradually decreasing verify voltages, the programmed memory cells may have a threshold greater than the range between about 2.65V and 2.95V The voltage passes the calibration operation.

Therefore, if the verification voltage is gradually reduced, the threshold voltage of the memory cell may be relatively slightly sacrificed. However, if programming is performed using the ISPP method of gradually increasing the program voltage by 0.5V, the threshold voltage may be more significantly increased, for example, by about 0.2V to 0.3V per program operation, and reaches about 0.5V at the maximum. Therefore, the increase in the shift of the threshold voltage caused by overprogramming can be further improved.

Therefore, if the first to n verification voltages are continuously applied to continuously perform a verification operation a plurality of times, a shift of a program threshold voltage may be adjusted narrower, and memory cells may not be overprogrammed.

If the verification voltage is continuously applied with the same magnitude as shown in FIG. excellent threshold voltage). In case the verify voltage is continuously applied with the same magnitude, the difference between the set threshold voltage and the desired or predetermined threshold voltage may be smaller than the increase of the threshold voltage during one program operation.

For example, the set threshold voltage may be about 0.05V to 0.35V lower than the desired or predetermined threshold voltage, or eg about 0.1V to 0.2V lower. If the desired or predetermined threshold voltage is approximately 3V, the set threshold voltage may be any value within the range between approximately 2.65V and 2.95V.

Even if the threshold voltage is set in a range between about 2.65V and 2.95V, the threshold voltage of the memory cell may be slightly lost. However, memory cells may not be overprogrammed by performing a program operation again, and a shift of a program threshold voltage may be adjusted to be narrower.

A programming scheme and a shift in threshold voltage of a memory cell using a programming method according to an exemplary embodiment are now compared with a programming scheme and a shift in threshold voltage of a memory cell using a conventional programming method using a general ISPP method.

7 is an example graph illustrating changes in threshold voltage during programming of a charge trap flash (CTF) memory cell with respect to the example waveform of the voltage pulse of FIG. 6 . 8A and 8B are example graphs respectively illustrating a programming scheme and a shift of a threshold voltage of a memory cell using a conventional programming method. 9A and 9B are example graphs respectively illustrating a programming scheme and a shift of a threshold voltage of a memory cell using a programming method of an exemplary embodiment.

Referring to FIGS. 6 and 7, if programming is performed using the general ISPP method, one program voltage applying operation and one verifying operation are alternately repeated while gradually increasing the program voltage from 16V in increments of 0.5V.

During the programming described above, CTF memory cells may also have an instantaneous threshold voltage that increases over time after application of a programming pulse. For example, if programming is performed using a program pulse of 17V, it may be determined that the threshold voltage is lower than the verification voltage V _ref . However, the threshold voltage may increase over time and exceed the verification voltage V _ref .

Accordingly, a verify operation may determine that programming has failed, as shown in FIG. 8A. Therefore, the program pulse is applied again. As a result, memory cells may be overprogrammed. Therefore, as shown in FIG. 8B , the shift of the threshold voltage of the memory cell increases compared to the case where the threshold voltage does not vary with time.

If programming is performed using a general ISPP method, fully programmed memory cells may be determined to fail programming due to a transient threshold voltage during verification. Therefore, there is a possibility that fully programmed memory cells are additionally programmed. As a result, the possibility that the threshold voltage is more shifted increases.

If the program method of the exemplary embodiment is used, during a verify operation using a pulse of the first verify voltage V _ref1 as shown in FIG. 9A , it may be determined that a memory cell program fails. However, if the verify operation is repeated using the pulse of the second verify voltage V _ref2 lower than the pulse of the first verify voltage V _ref1 after a desired or predetermined time elapses, the memory cell may be determined as a program pass . Therefore, another program operation does not need to be performed. Therefore, the shift of the threshold voltage of the memory cell can be largely reduced. For example, as shown in FIG. 9B, the shift in the threshold voltage of a memory cell may be more similar to the shift in threshold voltage that does not change over time.

In FIG. 9A , the verify operation is repeated using a second verify voltage V _ref2 lower than the first verify voltage V _ref1 . However, the verify operation may be repeated using the second verify voltage V _ref2 equal to the first verify voltage V _ref1 . Even in the case where the second verification voltage V _ref2 is equal to the first verification voltage V _ref1 , the shift of the threshold voltage of the memory cell can be largely reduced. For example, a shift in the threshold voltage of a memory cell may be more similar to a shift in threshold voltage that does not change over time.

It has been described that as long as the threshold voltage does not reach the set threshold voltage, the verification voltage pulse is continuously applied at least two times or more after one programming to perform verification. If, as shown in FIG. 10, the program voltage applying operation and verifying operation are repeated with the program voltage gradually increased, only when the threshold voltage of the memory cell is equal to or greater than a desired or predetermined value, it can be selectively used the processing.

For example, using the ISPP method, a programmed threshold voltage of a memory cell may not reach a set threshold voltage during initial programming. If the programmed threshold voltage of the memory cell has not reached the set threshold voltage, the program voltage increased by one level may be applied to re-perform the program operation without at least two consecutive performances of the verify operation. In this case, no overprogramming takes place. Only when the threshold voltage of the memory cell is equal to or greater than an expected or predetermined value, the verify operation may be performed consecutively at least two times or more. Therefore, the overall programming time can be effectively reduced.

FIG. 10 is a flowchart of a program operation of a program method according to another exemplary embodiment of the present invention. 11 and 12 illustrate exemplary waveforms of voltage pulses applied to selected WLs during programming using the programming method of FIG. 10 according to exemplary embodiments. Comparing FIGS. 10 to 12 with FIGS. 3 to 5 , the programming method in FIG. 10 is different from the programming method in FIG. 3 in that a verification operation can be performed every time a programming voltage application operation is performed until the memory cell reaches A threshold voltage equal to or greater than a desired or predetermined value. However, during programming after the threshold voltage of the memory cell is equal to or greater than a desired or predetermined value, the programming method of FIG. 10 is substantially the same as that of FIG. 3 .

Referring to FIG. 10 , a programming method according to another exemplary embodiment may include operations of applying a programming voltage to program memory cells and verifying the programmed memory cells. The verify operation may be continuously performed multiple times after the program voltage is applied.

The programming method of another exemplary embodiment may include a first programming operation 200 and a second programming operation 300 . The first program operation 200 may include a verify operation using a relatively low verify voltage, the second program operation 300 may include a verify operation using a verify voltage higher than the low verify voltage, and the second program Operation 300 may be performed after the first programming operation 200 .

The first program operation 200 may be performed until the verify operation using the low verify voltage passes. The second program operation 300 may be performed on memory cells that have passed a verify operation using a low verify voltage.

In the first program operation 200, one program voltage applying operation and one verifying operation may be repeatedly performed in pairs.

In the second program operation 300, the verify operation may be continuously performed multiple times. The second program operation 300 may correspond to the program method of the exemplary embodiment shown with reference to FIG. 3 . A higher verify voltage than the low verify voltage may be used in the second program operation 300 .

As shown in FIGS. 11 and 12 , the program method of another exemplary embodiment may be performed using an ISP method in which programming is performed while a program voltage is gradually increased.

For example, in the first program operation 200, one program voltage applying operation and one verifying operation may be repeatedly performed in pairs with the program voltage gradually increased until the memory cell to be programmed passes through the memory cell using the low verify voltage. Verify operation.

The second program operation 300 may be performed on memory cells that have passed a verify operation using a low verify voltage. For example, in a case where a program voltage is gradually increased, one program voltage applying operation and a plurality of consecutive verify operations using a high verify voltage may be repeatedly performed in pairs.

A difference between the low verify voltage and the high verify voltage may be approximately equal to or greater than an increase in threshold voltage generated by at least one program voltage applying operation. The low verify voltage may be approximately 0.2V to 1.0V lower than the high verify voltage.

For example, the high verify voltage used in the second program operation 300 may be about 3V. Where the high verify voltage is about 3V, the low verify voltage can be anywhere in the range between about 2.0V and 2.8V, about 0.2V to 1.0V lower than the high verify voltage. The high verify voltage used in the second program operation 300 may be gradually reduced from 3V if the magnitude of the applied high verify voltage is gradually reduced during performing a plurality of consecutive verify operations.

FIG. 11 illustrates exemplary waveforms of voltages used in a programming method of another exemplary embodiment. In the first program operation 200 , one program voltage application operation and one verify operation using a low verify voltage are repeatedly performed in pairs while the program voltage is gradually increased. In the second program operation 300 , one program voltage applying operation and a plurality of consecutive verify operations using high verify voltages having the same magnitude are repeatedly performed in pairs while the program voltage is gradually increased.

FIG. 12 illustrates exemplary waveforms of voltages used in the programming method illustrated in FIG. 10 according to another embodiment. In the first program operation 200 , one program voltage application operation and one verify operation using a low verify voltage are repeatedly performed in pairs while the program voltage is gradually increased. In the second program operation 300 , one program voltage application operation and a plurality of consecutive verify operations using gradually lowered high verify voltages are repeatedly performed in pairs with the program voltage gradually increased.

In FIGS. 11 and 12 , the basic program voltage is 16V, and the program voltage is gradually increased in increments of 0.5V to perform a program operation. In the first program operation 200, one program voltage applying operation and one verifying operation are repeated twice in pairs. In the second program operation 300, the verify operation is continuously performed three times every time the program voltage applying operation is performed. In FIG. 11, LV _ref represents a low verify voltage, and HV _ref represents a high verify voltage with the same magnitude. In FIG. 12 , LV _ref represents a low verify voltage, and HV _ref1 , HV _ref2 , and HV _ref3 represent gradually decreasing high verify voltages. The lowest high verification voltage among the high verification voltages, for example HV _ref3 may be higher than the low verification voltage LV _ref .

A process of performing programming using a programming method of another exemplary embodiment will now be described in more detail with reference to FIG. 10 .

In operation S210, a programming mode may start. In operation S220, data may be input to select a specific WL, for example, WL WL29. A first programming operation 200 may be performed.

The first program operation 200 may include operation S230, wherein in operation S230, a program voltage V _pgm may be applied to the selected WL to program the selected WL. Memory cell A corresponding to a bit line supplied with a ground voltage and connected to a selected WL may be programmed.

A program voltage application operation may be performed on the memory cell A once. In operation S240, a low verify voltage may be applied to the selected WL to verify the programmed memory cell A. Referring to FIG. In operation S250, it is determined whether the programmed memory cell A has passed the verify operation using the low verify voltage.

If in operation S250, the programmed memory cell A is determined to have a threshold voltage not equal to or greater than an expected or predetermined value, and thus the programmed memory cell A fails the verify operation using the low verify voltage, then In operation S260, the program voltage V _pgm may be increased by ΔV _pgm . An increased program voltage may be applied to the selected WL to reprogram memory cell A in operation S230. In operation S240, a low verify voltage may be applied to verify memory cell A. Referring to FIG. In operation S250, it is determined whether the memory cell A has passed the verify operation using the low verify voltage.

The process of programming memory cell A with the program voltage gradually increased and verifying memory cell A with a low verify voltage is repeatedly performed until the threshold voltage of memory cell A is equal to or greater than a desired or predetermined value, thus , by using a low threshold voltage for the verify operation.

In the first program operation 200, a verify operation is performed on the memory cell A by using a low verify voltage every time a program voltage applying operation is performed.

If the programmed memory cell A is determined to have passed the verify operation using the low verify voltage in operation S250, the second program operation 300 may be performed. A process corresponding to the program method of the exemplary embodiment described with reference to FIG. 3 may be performed in the second program operation S300.

For example, in operation S330, a program voltage V _pgm may be applied to a selected WL, eg, WL WL29, to reprogram memory cell A that has passed a verify operation using a low verify voltage. If the ISPP method is used, the program voltage applied first in the second program operation 300 may be a voltage increased by ΔV _pgm compared to the program voltage last applied in the first program operation 200 .

After programming memory cell A, a high verify voltage may be applied to selected WLs to verify programmed memory cell A as described below.

In operation S340, a first high verify voltage may be applied to the programmed memory cell A to verify the programmed memory cell A. Referring to FIG. In operation S350, it is determined whether the programmed memory cell A has reached the set threshold voltage and has been programmed, that is, it is determined whether the programmed memory cell has passed the verify operation.

If in operation S350, memory cell A is determined to have reached the set threshold voltage and thus memory cell A is programmed to a desired or predetermined layer, then in operation S410, programming of memory cell A may end. If the programmed memory cell A is determined not to reach the set threshold voltage in operation S350, a second high verify voltage may be applied to re-verify the programmed memory cell A in operation S360. In operation S370, it is determined whether the programmed memory cell A has reached the set threshold voltage.

If in operation S370, it is determined that the memory cell A has reached the set threshold voltage according to the result of the verify operation using the second high verify voltage, then in operation S410, programming of the memory cell A may end.

If it is determined that the memory cell A has not reached the set threshold voltage according to the result of the verify operation using the second high verify voltage in operation S370, the programmed memory cell A may be re-verified.

If, in any verify operation, it is determined that the memory cell A does not reach the set threshold voltage, operations of verifying the memory cell A up to a verify operation using the nth highest verify voltage may be performed. In operation S380, the nth high verify voltage may be applied to re-verify the programmed memory cell A. Referring to FIG. In operation S390, it is determined whether the programmed memory cell A has reached the set threshold voltage.

If it is determined that the programmed memory cell A has not reached the set threshold voltage according to the result of the verify operation using the nth highest verify voltage in operation S390, the program voltage V _pgm may be increased by ΔV _pgm in operation S400. A program voltage increased by ΔV _pgm may be applied to the selected WL to reprogram memory cell A in operation S330.

If the verify operation using the high verify voltage is set to be performed at least twice every time the program voltage applying operation is performed, the program method of FIG. 10 may be performed up to the verify operation using the second high verify voltage. In case the verification operation is performed only twice, the nth highest verification voltage may be equal to the second highest verification voltage. If it is determined that the memory cell A does not reach the set threshold voltage according to the result of the verify operation using the second verify voltage, the program voltage increased by ΔV _pgm may be applied to reprogram the memory cell A.

As described above, if it is determined that memory cell A has reached a set threshold voltage according to a result of a verify operation performed by sequentially applying high verify voltages, programming of memory cell A may end. If it is determined that memory cell A does not reach the set threshold voltage, reapplying a high verify voltage to verify memory cell A may be performed up to n (where n is a number equal to or greater than '2') times.

For example, before the program voltage is increased by ΔV _pgm to perform another program operation, the verify operation may be continuously performed multiple times by sequentially applying the first to nth verify voltages at desired or predetermined intervals. The desired or predetermined interval may range between approximately 1 μs and 100 μs.

If the programmed memory cell A does not reach the set threshold voltage as a result of the verify operation using the nth verify voltage, the program voltage V _pgm may be increased by ΔV _pgm and applied to the selected WL to repeat as described above Second programming operation 300 .

If it is determined that the memory cell A has reached the set threshold voltage during any of the n verification operations, the operation of programming the memory cell A may end in operation S410.

In the programming method of another exemplary embodiment, the first to nth high verification voltages may have the same magnitude as shown in FIG. 11 or may have gradually decreased magnitudes as shown in FIG. 12 .

The second programming operation 300 of the programming method of the exemplary embodiment may substantially correspond to the programming method of the exemplary embodiment previously described with reference to FIGS. 3 to 5 , 7 , 9A, and 9B. Therefore, the programming technique using the second programming operation 300 , the programming scheme of the memory cells using the second programming operation 300 , and the shift of the threshold voltage will not be described repeatedly here.

The program method according to the exemplary embodiment has been described as gradually increasing the program voltage in increments of 0.5V from 16V using the ISPP method to repeatedly perform the program voltage applying operation and the verifying operation. However, exemplary embodiments are not limited thereto. For example, the starting programming voltage may have another value than 16V, and/or the gradual increase in programming voltage may be another value, eg, 0.3V instead of 0.5V.

A program method according to an exemplary embodiment in which a plurality of verification operations are performed after one program voltage applying operation may be applied to perform programming of a multi-level cell (MLC). That is, the following program operations may be applied to the MLC: performing a first program operation of a verify operation using a low verify voltage every time a program voltage applying operation is performed, performing a plurality of times every time a program voltage applying operation is performed. A second program operation of a verify operation using a high verify voltage, or a program operation in which a plurality of verify operations are performed every time a program voltage application operation is performed has been described with reference to FIGS. FIG. 12 describes a first program operation and a second program operation.

A case will be exemplarily described in which an MLC program method of performing a plurality of verification operations after performing a program voltage application operation once according to an exemplary embodiment is applied to a 4-layer cell. An MLC to which a programming method according to an exemplary embodiment is applied may be any one of a floating gate type memory cell, a charge trap type memory cell, and a memory cell of a NAND or NOR type flash memory.

A 4-level cell in a memory may have a "00" state, a "01" state, or a "10" state as a programmed state, and may have a "11" state as an erased state. The "11" state may be considered the first programming state. In this case, the '01' state, the '00' state, and the '10' state may be represented as second, third, and fourth programming states, respectively, in the order of threshold voltage magnitudes. Alternatively, the "11" state may be represented as an erase state, and the "01," "00," and "10" states may be represented as first, second, and third program states, respectively, in order of threshold voltage magnitudes. Here, the order of the '01', '00' and '10' states may be changed in accordance with the magnitude of the threshold voltage. For convenience, the "11" state will be represented as an erase state, and the "01," "00," and "10" states will be represented as program states described below.

The memory cells in the erased state may be programmed to an intermediate programming state by performing a first programming operation on the memory cells in the erased state, and the memory cells in the intermediate programming state may be programmed by performing a second programming operation on the memory cells in the intermediate programming state. To program to a final program state, an MLC program method according to an exemplary embodiment of the present invention is performed. Memory cells after the final programmed state may include three or more layers. 13A and 13B are schematic diagrams explaining an MLC programming method according to an exemplary embodiment of the present invention. 14A and 14B are schematic diagrams explaining an MLC programming method according to another exemplary embodiment of the present invention.

Referring to FIGS. 13A and 13B , a first program operation is applied to memory cells in an erased state so that the memory cells in the erased state are programmed as memory cells in an intermediate state that is a dummy state. Next, the second program operation is applied to the memory cells in the erased state or the memory cells in the dummy state, so that the memory cells in the erased state or the memory cells in the dummy state are programmed to store the memory cells in the predetermined program state as the final program state. unit.

In the first program operation based on the first program operation described with reference to FIGS. 10 to 12 , in the case where the magnitude of the program voltage is gradually increased, a calibration operation including one program voltage application operation and one use of a low verify voltage is repeatedly performed. A pair of operations that verify the operation until the verification using the low verification voltage is passed. In the second program operation based on the program operation described with reference to FIGS. 3 to 5 or the second program operation described with reference to FIGS. 10 to 12 , in the case where the magnitude of the program voltage is gradually increased, repeatedly performing a program including a program voltage once A pair of apply operation and multiple consecutive verify operations using a high verify voltage until the verify using a high verify voltage is passed. As described above, the magnitude of the high verification voltage used when performing a plurality of consecutive verification operations may be the same or may gradually decrease. As mentioned above, the high verify voltage may be higher than the low verify voltage by a predetermined magnitude.

A program state obtained by applying the second program operation to memory cells in a dummy state may have a higher minimum threshold voltage than a program state obtained by applying the second program operation to memory cells in an erased state.

If the memory cell is a 4-level cell, the erased state may be a '11' state, and the programmed state may be at least one of '00', '01' and '10' states.

For example, if a first program operation is applied to a memory cell of an '11' state which is an erased state, eg a least significant bit (LSB) may be programmed and thus an X0 state of a dummy state may be obtained. Here, the dummy state refers to a state that has not been used as a program state, and the dummy state is an intermediate state obtained by using a second program operation to obtain a program state.

The "X0" state may correspond to the "00" state which is the second programmed state in the memory cell (4-level cell). That is, as will be described, the "00" state can be obtained by shifting the minimum threshold voltage of the "X0" state, and reducing the threshold voltage distribution range. Since the "X0" state is obtained by performing a verify operation every time a program voltage applying operation is performed, the "X0" state has a wider threshold voltage distribution than a desired formed program state. Since the "X0" state is not used as the final programming state, this wide threshold voltage distribution does not cause any problems.

Since the wide threshold voltage distribution of the "X0" state does not cause any problems, the programming voltage increment ΔV' _pgm can be a relatively large value to reduce programming when the memory cells of the "11" state are programmed to the "X0" state time.

In order to program the "11" state into the "01" state, the "00" state, and the "10" state, the memory cells of the "11" state are first programmed to obtain the "X0" state as described above, and then, as shown in FIG. 13B shows programming the most significant bit (MSB) of the memory cell in the "11" state and the memory cell in the "X0" state as a dummy state.

Thus, memory cells can be programmed from the "11" state to the "01" state, and from the "X0" state to the "00" state and the "10" state.

The memory cell can be programmed from the "11" state to the "01" state and from the "X0" state to the "00" state by using the second program operation in which the verify operation is performed a plurality of times every time the program voltage application operation is performed. and "10" status.

Since a plurality of verify operations prevents overprogramming, the "00" state obtained by applying a second program operation in which a plurality of verify operations are performed every time a program voltage applying operation is performed may have a more stable state than the "X0" state which is a dummy state. narrow threshold voltage distribution. In addition, since a high verify voltage is used, the minimum threshold voltage of the "00" state can be higher than that of the "X0" state, which is a dummy state using a low verify voltage, and the threshold voltage distribution range of the "00" state is Can be compressed to have a narrower threshold voltage distribution range than the "X0" state which is a dummy state.

According to the MLC programming method according to the exemplary embodiment, for the operation of programming the memory cell from the "11" state as the erased state to the "X0" state as the dummy state and from the "X0" state to the "00" state, The program operation explained with reference to FIGS. 10 to 12 may be used.

Also, for the operation of programming from the '11' state which is the erased state to the 'X0' state which is the dummy state, the first program operation explained with reference to FIGS. 10 to 12 may be used. In addition, for the operation of programming memory cells from the "11" state which is the erased state and the "X0" state which is the dummy state to the "01" state and the "10" state, the method explained with reference to FIGS. 3 to 5 may be used. program operation or the second program operation explained with reference to FIGS. 10 to 12 .

By preventing overprogramming, each of the "01" state obtained from the "11" state and the "10" state obtained from the "X0" state is obtained by applying a program operation that performs a plurality of verify operations every time a program voltage application operation is performed. The threshold voltage distribution range of one can be compressed narrower than that of the "11" state or the "X0" state.

In order to further reduce the threshold voltage distribution range, the programming voltage increment ΔV _pgm when using the second programming operation to program the memory cell from the “11” state to the “01” state and from the “X0” state to the “00” state can be compared with The program voltage increment ΔV' _pgm when programming the memory cell from the "11" state to the "X0" state which is a dummy state using the first program operation is low.

As described above, since the first program operation uses a program voltage pulse and a single verify pulse as a low verify voltage, the "X0" state has a relatively wide distribution of threshold voltages.

However, since the second program operation uses a program voltage pulse and a plurality of verify pulses as high verify voltages, overprogramming is prevented, and the threshold voltage distribution of the '00' state is narrower than that of the 'X0' state. When the high verification voltage is greater than the low verification voltage, the minimum threshold voltage of the "00" state is moved to be higher than the minimum threshold voltage of the "X0" state, and the threshold voltage distribution range of the "00" state is wider than that of the "X0" state The voltage range is narrow.

In addition, since overprogramming is prevented, the threshold value of each of the "01" state obtained from the "11" state by using the second program operation and the "10" state obtained from the "X0" state by using the second program operation The voltage distribution range is narrower than that of the "11" state or the "X0" state.

Therefore, the program method according to an exemplary embodiment that performs a plurality of verification operations after one program voltage application operation may narrow the threshold voltage distribution range of each program state in MLC programming and may prevent overprogramming.

Referring to FIGS. 14A and 14B , a first program operation is applied to memory cells in an erased state, so that the programmed cells in the erased state are programmed to memory cells in a desired programmed state. Next, a second programming operation is applied to the memory cells of the desired programming state, so that the memory cells of the desired programming state are programmed to the memory cells of the final programming state, to increase the minimum threshold voltage of the desired programming state, and decrease Threshold voltage distribution range. A desired program state obtained by performing a first program operation may be an intermediate program state, and a final program state may be obtained by performing a second program operation to increase a minimum threshold voltage and decrease a threshold voltage distribution range.

In the first program operation based on the first program operation described with reference to FIGS. 10 to 12 , in the case where the magnitude of the program voltage is gradually increased, one program voltage application operation and one verification operation using a low verification voltage are included. A pair of operations are repeatedly performed until the verification using the low verification voltage is passed. In the second programming operation based on the programming operation described with reference to FIGS. 3 to 5 and the second programming operation described with reference to FIGS. A pair of an apply operation and a plurality of consecutive verify operations using the high verify voltage until the verify using the high verify voltage passes. The magnitude of the high verification voltage used when performing a plurality of consecutive verification operations may be equal, or may be gradually reduced as described above. As mentioned above, the high verify voltage may be greater than the low verify voltage by a predetermined magnitude.

Referring to FIG. 14A, when the memory cell is a 4-layer cell, the first programming operation is applied to the memory cell of the "11" state, so that the memory cell of the "11" state is first programmed to the "01" state, the "00" state or "10" status. Next, referring to FIG. 14B, a second program operation is applied to the memory cells that were first programmed to the “01” state, the “00” state, or the “10” state, thereby increasing the “01” state, the “00” state, or the “10” state. ” state minimum threshold voltage, and reduce the threshold voltage distribution range of “01” state, “00” state or “10” state.

Therefore, since the MLC programming method including the first program operation and the second program operation performs a verify operation every time a program voltage applying operation is performed when the threshold voltage of the memory cell is far from the set threshold voltage, while the threshold voltage of the memory cell The verification operation is performed every time a program voltage application operation is performed close to the set threshold voltage, so the overall program time can be reduced, overprogramming can be prevented, and the threshold voltage distribution range of each program state can be reduced.

In the MLC programming method according to another exemplary embodiment, the verification operation is performed every time the program voltage applying operation is performed by gradually increasing the program voltage until the program voltage lower than that used in the first program operation is used. The verification operation of the verification voltage with a low verification voltage is passed, and the memory cell in the erased state can be programmed to a predetermined programming state (intermediate programming state) at first, and then by sequentially performing the first programming operation and the second programming operation, Memory cells of a predetermined programming state may be programmed to a final programming state to increase a minimum threshold voltage of the predetermined programming state and reduce a threshold voltage distribution range.

The NAND flash memory is divided into blocks in which memory cells can be erased simultaneously, each block including a plurality of memory cell arrays. For example, a NAND flash memory may be divided into 1024 blocks, and each of the 1024 blocks may include 8512 memory cell arrays. The memory cell array is divided into even arrays and odd arrays, and the even arrays and odd arrays are connected to bit lines. In read and program operations, memory cells connected to the same word line and the same type of bit line (eg, even bit line or odd bit line) can be selected for reading and programming at the same time. Data that is read or programmed simultaneously forms a logical page. For example, if a block includes n word lines, a block can store at least 2n logical pages because each of the n word lines can include even and odd pages.

A memory cell in a block may have from 1 to 4 adjacent memory cells. Among adjacent 4 memory cells, two may be arranged in the same NAND string, and the remaining two may be arranged in adjacent NAND strings. In order to reduce the gate coupling effect between adjacent memory cells, program the first page of a specific memory cell, program the first page of memory cells adjacent to the specific memory cell, and then program the specific The second page of memory cells is programmed. A memory cell for storing 2-bit data stores data in 2 logical pages.

When this NAND flash memory is programmed to a single-level cell using the programming method of FIGS. 10 to 12 or to an MLC using the MLC programming method of FIGS. 13A to 14B, it can be as follows Memory cells in the same NAND string are programmed to reduce gate coupling effects between adjacent memory cells.

FIG. 15 shows a part of one NAND string in a block having a plurality of NAND strings. In FIG. 15, 5 memory cells are arranged in one NAND string. However, each NAND string may include multiple memory cells.

There are two memory cells adjacent to a particular memory cell 400 in the same NAND string.

Memory cells in the same NAND string can be programmed in the following order to reduce gate coupling effects between adjacent memory cells.

A specific memory cell 400 is programmed by using a first programming operation, a memory cell 402 adjacent to the specific memory cell 400 is programmed by using a first programming operation, and then, a specific memory cell 400 is programmed by using a second programming operation . Next, memory cell 406 adjacent to memory cell 402 and opposite to specific memory cell 400 is programmed by using a first programming operation, and then memory cell 402 is programmed by using a second programming operation. Here, when the memory cells are programmed into the MLC, the second program operation may include only the operation of performing a plurality of verification operations every time the program voltage application operation is performed as described with reference to FIGS. 13A to 14B , or may include performing a program An operation of performing one verify operation for a voltage applying operation and an operation of performing a plurality of verify operations every time a program voltage applying operation is performed.

Table 1 shows the order of programming memory cells arranged in the same NAND string.

Table 1

When memory cells are programmed in the above-described order, it is possible to prevent the threshold voltage range of a memory cell, which has been narrow after performing the second program operation, from widening again when programming an adjacent memory cell. Accordingly, a narrow threshold voltage distribution obtained by using at least the first program operation and the subsequent second program operation can be maintained.

As described above, the method of programming a flash memory device according to an exemplary embodiment uses a process of performing a plurality of consecutive verify operations every time a program voltage applying operation is performed. Therefore, flash memory cells may not be overprogrammed due to a verify error that may occur in a general ISPP method. Therefore, the shift of the threshold voltage of the programmed state can be more effectively reduced.

Therefore, if the program method of the exemplary embodiment is used, shifts of threshold voltages of cells respectively corresponding to recording states may be reduced. Therefore, in the multi-level unit operation, the recording state can be recognized individually.

Although exemplary embodiments have been shown and described in the specification and drawings, it should be understood by those skilled in the art that the exemplary embodiments shown and/or described may be modified without departing from the principles and spirit of the invention. Example changes.

Claims (29)

1. A method of programming a storage device, the method comprising: performing a programming voltage application operation; perform a checkout operation, Wherein, a plurality of verification operations are continuously performed after the program voltage applying operation. 2. The method as claimed in claim 1, wherein in the case of gradually increasing the magnitude of the programming voltage, a pair of operations including one voltage applying operation and a plurality of verifying operations are repeatedly performed until the memory cell reaches a set threshold voltage. 3. The method as claimed in claim 1, wherein the verification voltages used when the verification operations are performed consecutively a plurality of times have the same amplitude. 4. The method of claim 1, wherein the magnitude of the verification voltage used when the verification operation is performed consecutively is continuously decreased. 5. The method of claim 4, wherein the verification voltage is gradually reduced by the same magnitude. 6. The method of claim 5, wherein the verification voltage is gradually decreased by 0.05V to 0.35V. 7. The method of claim 4, wherein the verification voltage is gradually decreased by 0.05V to 0.35V. 8. The method of claim 1, wherein the memory cell is one of a floating gate type memory cell and a charge trap type memory cell. 9. The method of claim 1, wherein the verification operation is performed a plurality of times at regular intervals. 10. The method of claim 9, wherein the certain interval is in the range between 1 [mu]s and 100 [mu]s. 11. The method of claim 1, further comprising: performing a first program operation including a verify operation using a first verify voltage; performing a second program operation including a verify operation using a second verify voltage greater than the first verify voltage, wherein after the program voltage is applied to the memory cell, the program voltage applying operation is performed consecutively a plurality of times check operation, Wherein, in the first program operation, a pair of operations including one program voltage application operation and one verify operation are repeatedly performed until the verify operation using the first verify voltage is performed, In the second program operation, a pair of operations including one program voltage applying operation and a plurality of verify operations are repeatedly performed until a verify operation using the second verify voltage is passed. 12. The method of claim 11, wherein the first verification voltage is lower than the second verification voltage by 0.2V to 1.0V. 13. The method of claim 11, wherein the second program operation is performed on the memory cells passed the verify operation using the first verify voltage. 14. The method of claim 13, wherein the first programming operation is performed on the memory cells in the erased state so that the memory cells in the erased state are programmed into an intermediate programming state, and the second programming operation is performed on the memory cells in the intermediate programming state. Two programming operations, so that the memory cells in the intermediate programming state are programmed to the final programming state. 15. The method of claim 14, wherein the memory cells after the final programmed state comprise three or more layers. 16. The method of claim 14, wherein the first programming operation is performed on the memory cells in the erased state so that the memory cells in the erased state are programmed into an intermediate programming state, A second programming operation is performed on the memory cells in the intermediate programming state to program the memory cells in the intermediate programming state to a final programming state to increase the minimum threshold voltage of the intermediate programming state and decrease the threshold voltage distribution range. 17. The method according to claim 16, wherein the memory cell is a 4-level cell, the erased state is the "11" state, and the final programmed state is at least one of the "01" state, the "00" state and the "10" state A sort of. 18. The method of claim 16, wherein, in each of the first program operation and the second program operation, in the case of gradually increasing the program voltage, repeatedly performing the process including the program voltage applying operation and the verifying operation A pair of operations. 19. The method of claim 18, wherein the program voltage increment in each step in the second program operation is lower than the program voltage increment in each step in the first program operation. 20. The method of claim 13, further comprising performing a third program operation comprising a verify operation using a verify voltage lower than the first verify voltage, wherein repeatedly performing on memory cells in an erased state comprises once A pair of operations of a programming voltage applying operation and a verifying operation until a memory cell in an erased state is programmed to an intermediate programmed state by a verifying operation using a verifying voltage lower than the first verifying voltage, Wherein, the first programming operation and the second programming operation are successively applied to the memory cells in the intermediate programming state, so that the memory cells in the intermediate programming state are programmed into the final programming state to increase the minimum threshold voltage of the programming state and decrease the threshold Voltage distribution range. 21. The method of claim 20, wherein, in each of the third program operation, the second program operation, and the first program operation, in the case of gradually increasing the program voltage, repeatedly performing the operation including the program voltage applying A pair of operations and checksum operations. 22. The method of claim 21, wherein the program voltage increment in each step in the second program operation is lower than the program voltage increment in each step in the first program operation. 23. The method of claim 20, wherein the memory cell is a 4-level cell, the erased state is the "11" state, and the final programmed state is at least one of the "01" state, the "00" state and the "10" state A sort of. 24. The method of claim 11, wherein the verification operation is performed a plurality of times at regular intervals. 25. The method of claim 24, wherein the certain interval is in a range between 1 [mu]s and 100 [mu]s. 26. The method of claim 11, wherein the memory cell is one of a floating gate type memory cell and a charge trap type memory cell. 27. The method of claim 14, wherein the memory cells in the erased state are applied with a first program operation such that the memory cells in the erased state are programmed to an intermediate programming state that is a dummy state, the memory cells in the erased state are applied with a second programming operation such that the memory cells in the erased state are programmed to the first programmed state, The memory cells in the dummy state are applied with a second programming operation such that the memory cells in the dummy state are programmed to the second or third programming state. 28. The method according to claim 27, wherein the memory cell is a 4-level cell, the erased state is the "11" state, and the first to third programming states are the "01" state, the "00" state, and the "10" state status and are different from each other. 29. The method of claim 27, wherein, in each of the first program operation and the second program operation, in the case of gradually increasing the magnitude of the program voltage, repeatedly performing the program voltage applying operation and the calibration process. A pair of operations that test operations.

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