CN101316352B - Method and device for implementing multiple pictures of conference television system, video gateway and implementing method thereof - Google Patents
Method and device for implementing multiple pictures of conference television system, video gateway and implementing method thereof Download PDFInfo
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Abstract
The invention discloses a method for realizing multiple pictures of a video conferphone system, which comprises the steps that: a digital signal processor and a video bit stream input and output module are configured according to instructions of the system; when a video bit stream is inputted, the digital signal processor decodes and encodes videos inputted from each path. The invention also discloses a device for realizing the multiple pictures of the video conferphone system, which comprises a storage module, a master CPU, the video bit stream input and output module, a connecting module, a display module and a plurality of digital signal processors. The device is easy for resource collocation and has good extendibility and high design flexibility ratio. In addition, the invention also discloses a video gateway which comprises the storage module, the master CPU, a data input and output module, the connecting module and a plurality of digital signal processors. When in work, the digital signal processors and the data input and output module are configured according to the instructions of the system; when data is inputted, the digital signal processors decode and encode the data of each path, thus being capable of collocating resources flexibly.
Description
Technical Field
The invention relates to a video processing technology, in particular to a method and a device for realizing multiple pictures of a video conference system, a video gateway and a method for realizing the video gateway.
Background
Video conferencing has been widely used in the field of demand-to-mouth as an advanced communication means. These areas of application include government conferences, distance teaching, remote diagnostics, and enterprise conferences across regions, among others. The conference television system enables conference participants far away from a thousand miles to be personally on the scene, the communication is more convenient, visual and accurate, the expenditure is saved for users, and the working efficiency is improved.
The device is generally in a tree topology structure, namely the main control CPU and all digital signal processors are connected on the same high-speed bus, and all the digital signal processors are connected through high-speed interfaces according to the predicted data stream transmission direction, wherein one group of pictures can only be realized through signal processing by one group of digital signal processors interconnected by the high-speed interfaces. When the existing device for realizing multiple pictures of a video conference system runs, a main control CPU firstly distributes a video code stream to each digital signal processor through a high-speed bus according to a system instruction, the interconnected digital signal processors perform signal processing, then the processed video code stream is sent to the main control CPU through the high-speed bus, and finally the main control CPU transmits the video code stream to a display module for displaying.
It can be seen that, in the conventional multi-picture implementing device for a video conference system, since the digital signal processors are connected according to the predicted data stream transmission direction, the number of the digital signal processors, the functions of each digital signal processor and the flow direction of the video code stream among the digital signal processors in the device are relatively fixed, i.e. the number of picture groups that can be displayed by the video conference system and the number of pictures specifically contained in each group of pictures are relatively fixed, so that the conventional multi-picture implementing device for a video conference system is not easy to maintain, has poor expandability and low design flexibility, and in the conventional multi-picture implementing device for a video conference system, the main control CPU and all the digital signal processors are connected to the same high-speed bus, and the video code stream or instruction transmission among the components of the system needs to pass through the high-speed bus, therefore, the processing capability of the high-definition video code stream with larger video code flow is limited, which is not beneficial to the realization of high-definition multi-picture.
In addition, in the prior art, the realization of the video gateway is restricted by the realization device similar to the realization device of the multi-picture of the video conference system, so that the resource allocation is not flexible when the video matching of multiple protocols, multiple rate code streams and multiple image formats is realized.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a method and an apparatus for implementing multiple pictures in a video conference system, which can improve the resolution of the multiple picture quality, facilitate resource allocation, have good expandability and high design flexibility, and provide a video gateway and an implementation method thereof, which can flexibly allocate resources when implementing video matching of multiple protocols, multiple rate code streams and multiple image formats.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method for realizing multiple pictures of a conference television system comprises the following steps:
a. the main control CPU respectively downloads the application programs in the storage module to each digital signal processor and operates the digital signal processors;
b. the main control CPU configures the digital signal processor and the video code stream input and output module according to the system instruction;
c. when a video code stream is input, the digital signal processor decodes and codes each path of input video transmitted by the video code stream input and output module, and then the video code stream input and output module transmits the video code stream to the display module for display.
The step a comprises the following steps: and the main control CPU reads and runs the running program in the storage module.
The application programs in the step a comprise an encoding program and a decoding program.
The system command in step b at least carries the number of groups of multiple pictures and the number of pictures contained in each group.
The step b includes the following steps after the video code stream input and output module is configured: the main control CPU informs the video code stream input and output module to open the video code stream input and output channel.
Step b said configuring the digital signal processor to:
b1, the main control CPU determines the digital signal processor to be applied, and determines the function of each digital signal processor and the flow direction of the video code stream among the digital signal processors; the function refers to being responsible for decoding or encoding;
b2, the master control CPU sends a control command to the digital signal processor to be applied in the step b 1;
b3, the digital signal processor processes correspondingly according to the received control command;
the video code stream input and output module is configured as follows: configuring the input video code stream to be processed by the video code stream input/output module to the input link of the digital signal processor responsible for decoding in step b 1; and c, configuring the video code stream processed by the digital signal processor responsible for encoding in the step b1 to an output link of the video code stream input and output module.
The control command of the step b2 at least carries the function of a digital signal processor; and when the digital signal processor is in charge of decoding, the control command also carries the flow direction of the processed video code stream.
The corresponding processing in the step b3 is as follows: the digital signal processor runs a decoding or encoding program according to the control command; when the digital signal processor is responsible for decoding, the method also comprises the step of setting the flow direction of the processed video code stream.
The step c comprises the following steps:
c1, the video code stream input/output module transmits each path of input video to the corresponding digital signal processor responsible for decoding;
c2, after the digital signal processor responsible for decoding decodes the input video, sending the processed video code stream to the corresponding digital signal processor responsible for encoding;
c3, the digital signal processor responsible for coding synthesizes the multi-path video code stream into a multi-picture mode and codes the multi-picture mode, and sends the processed video code stream to the video code stream input and output module;
c4, the video code stream input and output module transmits the video code stream to the display module for display.
The digital signal processors are connected in a star shape or in a mesh shape through a connecting module, and the connecting module is a high-speed bus exchange chip or a high-speed bus in the mesh shape.
A device for realizing multiple pictures of a conference television system mainly comprises a storage module, a main control CPU, a video code stream input/output module, a connecting module, a display module and a plurality of digital signal processors, wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction;
the video code stream input and output module is used for transmitting video code streams input by different video sources to the digital signal processors responsible for decoding and transmitting the video code streams transmitted by the digital signal processors responsible for encoding to the display module;
the connecting module is used for realizing interconnection between the digital signal processors;
the display module is used for displaying videos according to the video code streams sent by the video code stream input and output module;
the digital signal processor is used for encoding or decoding the input video code stream.
The connection module is realized by a high-speed bus exchange chip or a high-speed bus connected in a mesh manner.
The digital signal processor responsible for decoding is used for decoding the video code stream sent by the video code stream input and output module and sending the processed video code stream to the corresponding digital signal processor responsible for encoding; the digital signal processor responsible for coding is used for coding the multi-path video code stream sent by the digital signal processor responsible for decoding and sending the processed video code stream to the video code stream input and output module.
A method for implementing a video gateway includes:
d. the main control CPU respectively downloads the application programs in the storage module to each digital signal processor and operates the digital signal processors;
e. the main control CPU configures the digital signal processor and the data input and output module according to the system instruction;
f. when data is input, the digital signal processor decodes and codes each path of data transmitted by the data input and output module, and then the data is output by the data input and output module.
The step d comprises the following steps: and the main control CPU reads and runs the running program in the storage module.
The application program in the step d comprises an encoding program and a decoding program.
And e, the system instruction at least carries the path number of the data to be processed and the type of each path of data before and after processing.
Step e, configuring the data input/output module comprises the following steps: the main control CPU informs the data input and output module to open the data input and output channel.
Step e said configuring the digital signal processor to:
e1, the main control CPU determines the digital signal processors to be applied and determines the functions of each digital signal processor and the data flow direction among the digital signal processors; the function refers to being responsible for decoding or encoding;
e2, the master control CPU sends a control command to the digital signal processor to be applied in the step e 1;
e3, the digital signal processor processes correspondingly according to the received control command;
the data input output module is configured to: configuring each path of data to be processed by the data input and output module to the input link of the digital signal processor responsible for decoding in step e 1; and e1, configuring the data processed by the digital signal processor responsible for encoding in the step e1 to the output link of the data input and output module.
The control command of the step e2 at least carries the function of a digital signal processor; when the digital signal processor is responsible for decoding, the control command also carries the flow direction of the processed data.
The corresponding processing in step e3 is: when the digital signal processor is the digital signal processor responsible for decoding, the corresponding decoding program is operated according to the control command, and the flow direction of the processed data is set; and when the digital signal processor is the digital signal processor responsible for coding, operating a corresponding coding program according to the control command.
Step f comprises:
f1, the data input and output module transmits each path of input data to the corresponding digital signal processor responsible for decoding;
f2, after the digital signal processor responsible for decoding decodes the input data, the processed data is sent to the corresponding digital signal processor responsible for encoding;
and f3, the digital signal processor responsible for coding encodes the received data and sends the processed data to the data input and output module for output.
The digital signal processors are connected in a star shape or in a mesh shape through a connecting module, and the connecting module is a high-speed bus exchange chip or a high-speed bus in the mesh shape.
A video gateway mainly comprises a storage module, a main control CPU, a data input/output module, a connection module and a plurality of digital signal processors, wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction;
the data input and output module is used for transmitting data input by different data sources to each digital signal processor responsible for decoding and outputting data sent by the digital signal processor responsible for encoding;
the connecting module is used for realizing interconnection between the digital signal processors;
the digital signal processor is used for encoding or decoding input data.
The connection module is realized by a high-speed bus exchange chip or a high-speed bus connected in a mesh manner.
The digital signal processor responsible for decoding is used for decoding the data sent by the data input and output module and sending the processed data to the corresponding digital signal processor responsible for encoding; and the digital signal processor responsible for coding is used for coding the data sent by the digital signal processor responsible for decoding and sending the processed data to the data input and output module.
The invention provides a method and a device for realizing multiple pictures of a video conference system.A plurality of digital signal processors are connected in a star shape or in a mesh shape through a connecting module, a main control CPU finishes the configuration of the flow direction of video code streams between the digital signal processors and the digital signal processors according to the system instruction after receiving the system instruction, and when the video code streams are input, a video code stream input and output module transmits each path of input video to the corresponding digital signal processor which is responsible for decoding; the digital signal processor responsible for decoding sends the processed video code stream to the corresponding digital signal processor responsible for encoding; the digital signal processor responsible for coding synthesizes the multi-path video code stream into a multi-picture mode and codes the multi-picture mode, and then sends the processed video code stream to the video code stream input and output module; and finally, the video code stream is transmitted to a display module by the video code stream input and output module to be displayed. By adopting the method and the device for realizing the multiple pictures of the conference television system, the interconnection between the digital signal processors can be flexibly realized through the connecting module, so the method and the device are easy for resource allocation, good in expandability and high in design flexibility; in the same way, the video gateway and the implementation method thereof can flexibly realize the interconnection among the digital signal processors through the connecting module, so that resources can be flexibly allocated when the video matching of multiple protocols, multiple rate code streams and multiple image formats is realized.
Drawings
FIG. 1 is a diagram of a multi-screen implementation apparatus of a video conference system according to the present invention;
FIG. 2 is a flow chart of a method for implementing multiple pictures in a video conference system according to the present invention;
fig. 3 is a block diagram of a video gateway.
Detailed Description
The basic idea of the invention for realizing multiple pictures of a conference television system is as follows: the main control CPU completes the configuration of the flow direction of the video code stream between the digital signal processor and the digital signal processor according to the system instruction after receiving the system instruction, and when the video code stream is input, the video code stream input and output module transmits each path of input video to the corresponding digital signal processor which is responsible for decoding; the digital signal processor responsible for decoding sends the processed video code stream to the corresponding digital signal processor responsible for encoding; the digital signal processor responsible for coding synthesizes the multi-path video code stream into a multi-picture mode and codes the multi-picture mode, and then sends the processed video code stream to the video code stream input and output module; and finally, the video code stream is transmitted to a display module by the video code stream input and output module to be displayed. The present invention will be described in further detail with reference to the following embodiments and the accompanying drawings.
Fig. 1 is a structural diagram of a device for implementing multiple pictures of a video conference system, and as shown in fig. 1, the device for implementing multiple pictures of a video conference system mainly comprises a storage module, a main control CPU, a video code stream input/output module, a connection module, a display module and a plurality of digital signal processors. Wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction;
the video code stream input and output module is used for transmitting video code streams input by different video sources to each digital signal processor responsible for decoding and transmitting the video code streams transmitted by the digital signal processor responsible for encoding to the display module for displaying;
the connection module is used for realizing interconnection between the digital signal processors, can be realized by a high-speed bus exchange chip, and can also be realized by a high-speed bus connected in a mesh manner;
the display module is used for displaying videos according to the video code streams sent by the video code stream input and output module;
the digital signal processor is divided into a digital signal processor responsible for decoding and a digital signal processor responsible for encoding, and the digital signal processor responsible for decoding is used for decoding the video code stream sent by the video code stream input and output module and sending the processed video code stream to the corresponding digital signal processor responsible for encoding; the digital signal processor responsible for coding is used for coding the video code stream sent by the digital signal processor responsible for decoding and sending the processed video code stream to the video code stream input and output module.
Fig. 2 is a flowchart of a method for implementing multiple pictures in a video conference system, and as shown in fig. 2, the method for implementing multiple pictures in a video conference system mainly includes the following steps:
step 201: and after the power is on, the main control CPU reads the running program of the storage module and runs the running program.
Step 202: and the main control CPU downloads the application programs in the storage module to each digital signal processor respectively and operates the digital signal processors.
The application programs downloaded to the digital signal processors by the main control CPU are completely the same and all comprise an encoding program and a decoding program. Here, the master CPU numbers each digital signal processor, i.e. writes its corresponding chip number in a register specific to each digital signal processor, and at the same time, the master CPU stores the number information in the storage module.
Step 203: the master control CPU receives system instructions.
Here, the information carried by the system command generally includes the number of groups of multiple pictures and the number of pictures included in each group, and the system command may also specify the image size of the picture.
Step 204: and the main control CPU determines the digital signal processors to be applied according to the system instruction, and determines the functions of each digital signal processor and the flow direction of video code streams among the digital signal processors.
The main control CPU determines a digital signal processor to be applied according to the number of groups of multiple pictures carried by a system instruction and the number of pictures contained in each group; determining the function of each digital signal processor as: determining whether the digital signal processor is responsible for decoding or for encoding; determining the flow direction of the video code stream between the digital signal processors as follows: and the digital signal processor which is responsible for decoding is set to send the decoded video data to the corresponding digital signal processor which executes coding through the connecting module.
For example, the multi-picture implementing device of the video conference system comprises eight digital signal processors which are respectively numbered as digital signal processor 1 to digital signal processor 8, if the system instruction indicates that the video displayed by the video conference system should comprise two groups of pictures, one group comprises three pictures, and the other group comprises two pictures, the main control CPU can select to apply the digital signal processor 1 to the digital signal processor 7, wherein, the digital signal processor 1 and the digital signal processor 2 are responsible for encoding, the digital signal processor 3 to the digital signal processor 7 are responsible for decoding, the digital signal processor 3 to the digital signal processor 5 send the decoded video data to the digital signal processor 1, the digital signal processor 6 to the digital signal processor 7 send the decoded video data to the digital signal processor 2, thus, the output of the digital signal processor 1 corresponds to one group of pictures, the output of the digital signal processor 2 corresponds to another set of pictures. Here, the digital signal processor 8 is always in a wait state.
Here, the connection module may be implemented by a high-speed bus switch chip, or may be implemented by a high-speed bus connected in a mesh manner.
Step 205: the main control CPU sends a control command to the digital signal processor to be applied in step 204, and the digital signal processor performs corresponding processing according to the control command.
Here, the main control CPU sends different control commands or does not send a control command to the digital signal processors according to the tasks of the digital signal processors and the number information of the storage modules, generally, the control command at least carries the functions of the digital signal processors, and the control command sent to the digital signal processors responsible for decoding should also include the flow direction of the processed video code stream, and if the system instruction specifies the image size of the picture, the control command sent to the digital signal processors responsible for encoding should also include the parameter.
If the control command sent by the main control CPU to the digital signal processor 3 indicates that the digital signal processor is responsible for decoding and the processed video code stream is sent to the digital signal processor 1, the digital signal processor 3 runs a decoding program after receiving the control command and sets the digital signal processor 3 to send the decoded video code stream to the digital signal processor 1 through the connection module.
Step 206: the main control CPU configures the video code stream input and output module.
Here, the main control CPU configures the video stream input/output module, that is, configures the input video stream that needs to be processed by the video stream input/output module to the input link of the digital signal processor responsible for decoding in step 204, and configures the video stream processed by the digital signal processor responsible for encoding in step 204 to the output link of the video stream input/output module.
Step 207: the main control CPU informs the video code stream input and output module to open the video code stream input and output channel.
Here, the video stream input/output module opens the video stream input/output channel to indicate that the implementation apparatus for multiple pictures of the video conference system is ready.
Step 208: when video code stream is input, the video code stream input and output module transmits each path of input video to the corresponding digital signal processor which is responsible for decoding.
Step 209: and after the digital signal processor responsible for decoding decodes the input video, the processed video code stream is sent to the corresponding digital signal processor responsible for encoding.
Step 210: and the digital signal processor responsible for coding synthesizes the multi-path video code streams into a multi-picture mode and codes the multi-picture mode, and sends the processed video code streams to the video code stream input and output module.
Step 211: the video code stream input and output module transmits the video code stream to the display module for display.
By adopting the method for realizing the multiple pictures of the conference television system, and under the condition that the device for realizing the multiple pictures of the conference television system comprises eight digital signal processors, if an input video code stream is a high-definition video code stream, the synthesis and the coding of a single group of multiple pictures can maximally realize a 7 picture of 720P or a 6 picture of 1080I, when two groups of multiple pictures are synthesized under the condition of no multicast, 2 pictures and 4 pictures of 720P can be simultaneously realized, or 2 pictures of 720P and 3 pictures of 1080I can be simultaneously realized, and under the condition of applying multicast, the number of groups of the conference and the number of the pictures can be further increased; if the input video code stream is a standard definition D1 video code stream, more than 56 paths of sub-pictures can be realized, namely, a plurality of groups of commonly used 16-picture conferences are supported, and the number of the sub-pictures and the multi-picture mode are richer; for the commonly adopted conference television with the resolution of CIF, the number of conference groups and the number of multi-picture are increased by several times compared with D1, so the invention can improve the multi-picture image quality resolution, is easy for resource allocation, has good expandability and high design flexibility.
The multi-picture implementation scheme of the conference television system is also suitable for the video gateway, so the invention further provides the video gateway.
Fig. 3 is a structural diagram of a video gateway, and as shown in fig. 3, the video gateway provided by the present invention mainly comprises a storage module, a main control CPU, a data input/output module, a connection module, and a plurality of digital signal processors. Wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction;
the data input and output module is used for transmitting input data with different sources to each digital signal processor responsible for decoding and outputting data sent by the digital signal processor responsible for encoding;
the connection module is used for realizing interconnection between the digital signal processors, can be realized by a high-speed bus exchange chip, and can also be realized by a high-speed bus connected in a mesh manner;
the digital signal processor is divided into a digital signal processor responsible for decoding and a digital signal processor responsible for encoding, and the digital signal processor responsible for decoding is used for decoding input data sent by the data input and output module and sending the processed data to the corresponding digital signal processor responsible for encoding; and the digital signal processor responsible for coding is used for coding the data sent by the digital signal processor responsible for decoding and sending the processed data to the data input and output module.
The working process of the video gateway comprises the following steps:
step 401: and the main control CPU reads the application program in the storage module and runs the application program.
Step 402: and the main control CPU downloads the application programs in the storage module to each digital signal processor respectively and operates the digital signal processors.
The application programs downloaded to the digital signal processors by the main control CPU are completely the same and all comprise an encoding program and a decoding program. Since video gateways may involve data conversion for multiple protocols, multiple rates, and multiple image formats, the encoding and decoding procedures typically include multiple different encoding and decoding procedures to correspond to different encoding and decoding requirements.
Here, the master CPU numbers each digital signal processor, i.e. writes its corresponding chip number in a register specific to each digital signal processor, and at the same time, the master CPU stores the number information in the storage module.
Step 403: the master control CPU receives system instructions.
Here, the information carried by the system instruction generally includes the number of ways of data to be processed and the type before and after each way of data is processed.
Step 404: and the main control CPU determines the digital signal processors to be applied according to the system instruction, and determines the functions of each digital signal processor and the flow direction of data among the digital signal processors.
The main control CPU determines a digital signal processor to be applied according to the path number of data to be processed carried by a system instruction; determining the function of each digital signal processor as: determining a decoding program or an encoding program which is responsible for decoding or encoding and needs to be operated by the digital signal processor according to the types of each path of data before and after processing; determining the flow direction of data between the digital signal processors as follows: and the digital signal processor which is responsible for decoding is set to send the decoded data to the corresponding digital signal processor which executes coding through the connecting module.
For example, the video gateway includes eight digital signal processors, which are respectively numbered as digital signal processor 1 to digital signal processor 8, and the system instruction indicates that there are two paths of input data, one path of data is in an a1 image format, and needs to be converted into output data in an a2 image format; the code stream rate of the other path is B1, and it needs to be converted into output data with the code stream rate of B2, the main control CPU may apply the digital signal processor 1 to the digital signal processor 4, wherein the digital signal processor 1 and the digital signal processor 2 are responsible for encoding, the digital signal processor 3 and the digital signal processor 4 are responsible for decoding, the digital signal processor 3 sends the decoded data to the digital signal processor 1, and the digital signal processor 4 sends the decoded data to the digital signal processor 2, so that the output of the digital signal processor 1 corresponds to one path of data, and the output of the digital signal processor 2 corresponds to the other path of data. Here, the digital signal processor 5 to the digital signal processor 8 are always in a standby state. This example is applicable to high definition video gateways above 720P because if the image resolution in the video gateway is lower than 720P (e.g., D1, 4CIF, CIF), the encoding and decoding functions can be implemented with only one digital signal processor without allocating two digital signal processors.
Here, the connection module may be implemented by a high-speed bus switch chip, or may be implemented by a high-speed bus connected in a mesh manner.
Step 405: the main control CPU sends a control command to the digital signal processor, and the digital signal processor performs corresponding processing according to the control command.
Here, the main control CPU sends different control commands or does not send a control command to the digital signal processors according to the tasks of the digital signal processors and the number information of the storage modules, and generally, the control command at least carries the functions of the digital signal processors, that is, a decoding program or an encoding program for instructing the digital signal processors to need to run, and the flow direction of processed data should be included for the control command sent to the digital signal processor responsible for decoding.
If the control command sent to the digital signal processor 3 by the main control CPU instructs the digital signal processor to run the decoding program x and the processed data is sent to the digital signal processor 1, the digital signal processor 3 runs the decoding program x after receiving the control command, and sets the digital signal processor 3 to send the decoded data to the digital signal processor 1 through the connection module.
Step 406: the main control CPU configures the data input and output module.
Here, the main control CPU configures the data input/output module, that is, the input data that needs to be processed by the data input/output module is configured on the input link of the digital signal processor responsible for decoding in step 404, and the data processed by the digital signal processor responsible for encoding in step 404 is configured on the output link of the data input/output module.
Step 407: the main control CPU informs the data input and output module to open the data input and output channel.
Here, the data input output module opens the video data input output channel to indicate that the video gateway is ready.
Step 408: when data is input, the data input and output module transmits each path of input data to the corresponding digital signal processor which is responsible for decoding.
Step 409: and after the digital signal processor responsible for decoding decodes the input data, the processed data is sent to the corresponding digital signal processor responsible for encoding.
Step 410: and the digital signal processor responsible for coding codes the received data and sends the processed data to the data input and output module.
Step 411: the data input and output module outputs data.
By adopting the video gateway provided by the invention, the interconnection between the digital signal processors can be flexibly realized through the high-speed bus exchange chip, so that the video matching efficiency of multiple protocols, multiple rate code streams and multiple image formats can be effectively improved.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (18)
1. A method for realizing multiple pictures of a conference television system is characterized by comprising the following steps:
a. the main control CPU respectively downloads the application programs in the storage module to each digital signal processor and operates the digital signal processors;
b. the main control CPU configures the digital signal processor and the video code stream input and output module according to a system instruction, wherein the system instruction at least carries the number of groups of multiple pictures and the number of pictures respectively contained in each group;
c. when a video code stream is input, the digital signal processor decodes and codes each path of input video transmitted by the video code stream input and output module, and then the video code stream input and output module transmits the video code stream to the display module for display,
step b said configuring the digital signal processor to:
b1, the main control CPU determines the digital signal processor to be applied, and determines the function of each digital signal processor and the flow direction of the video code stream among the digital signal processors; the function refers to being responsible for decoding or encoding;
b2, the master control CPU sends a control command to the digital signal processor to be applied in the step b 1;
b3, the digital signal processor processes correspondingly according to the received control command,
the control command of the step b2 at least carries the function of a digital signal processor; when the digital signal processor is responsible for decoding, the control command also carries the flow direction of the processed video code stream,
the corresponding processing in the step b3 is as follows: the digital signal processor runs a decoding or encoding program according to the control command; when the digital signal processor is responsible for decoding, the method also comprises the steps of setting the flow direction of the processed video code stream,
the video code stream input and output module is configured as follows: configuring the input video code stream to be processed by the video code stream input/output module to the input link of the digital signal processor responsible for decoding in step b 1; and c, configuring the video code stream processed by the digital signal processor responsible for encoding in the step b1 to an output link of the video code stream input and output module.
2. The method of claim 1, wherein step a is preceded by the steps of: and the main control CPU reads and runs the running program in the storage module.
3. The method of claim 1, wherein the application programs of step a comprise an encoding program and a decoding program.
4. The method according to claim 1, wherein the step b of configuring the video stream input/output module comprises the steps of: the main control CPU informs the video code stream input and output module to open the video code stream input and output channel.
5. The method of claim 1, wherein step c comprises:
c1, the video code stream input/output module transmits each path of input video to the corresponding digital signal processor responsible for decoding;
c2, after the digital signal processor responsible for decoding decodes the input video, sending the processed video code stream to the corresponding digital signal processor responsible for encoding;
c3, the digital signal processor responsible for coding synthesizes the multi-path video code stream into a multi-picture mode and codes the multi-picture mode, and sends the processed video code stream to the video code stream input and output module;
c4, the video code stream input and output module transmits the video code stream to the display module for display.
6. The method according to any one of claims 1 to 5, wherein star connection or mesh interconnection is realized between the digital signal processors through a connection module, and the connection module is a high-speed bus switching chip or a high-speed bus of mesh connection.
7. A device for realizing multiple pictures of a conference television system is characterized by mainly comprising a storage module, a main control CPU, a video code stream input and output module, a connecting module, a display module and a plurality of digital signal processors, wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction, wherein the system instruction at least carries the number of groups of multiple pictures and the number of pictures contained in each group;
the video code stream input and output module is used for transmitting video code streams input by different video sources to the digital signal processors responsible for decoding and transmitting the video code streams transmitted by the digital signal processors responsible for encoding to the display module;
the connecting module is used for realizing interconnection between the digital signal processors;
the display module is used for displaying videos according to the video code streams sent by the video code stream input and output module;
the digital signal processor is used for encoding or decoding an input video code stream,
the master CPU configures the digital signal processor to:
the main control CPU determines digital signal processors to be applied and determines the functions of each digital signal processor and the flow direction of video code streams among the digital signal processors; the function refers to being responsible for decoding or encoding;
the main control CPU sends a control command to the digital signal processor to be applied, wherein the control command at least carries the function of the digital signal processor; when the digital signal processor is in charge of decoding, the control command also carries the flow direction of the processed video code stream;
the digital signal processor performs corresponding processing according to the received control command, wherein the corresponding processing comprises the following steps: the digital signal processor runs a decoding or encoding program according to the control command; when the digital signal processor is responsible for decoding, the method also comprises the steps of setting the flow direction of the processed video code stream,
the main control CPU configures a video code stream input and output module as follows: configuring an input video code stream to be processed by a video code stream input and output module to an input link of the digital signal processor responsible for decoding; and configuring the video code stream processed by the digital signal processor in charge of coding to an output link of the video code stream input and output module.
8. The apparatus of claim 7, wherein the connection module is implemented by a high-speed bus switch chip or a mesh-connected high-speed bus.
9. The apparatus according to claim 7, wherein the digital signal processor responsible for decoding is configured to decode a video bitstream sent by the video bitstream input/output module, and send the processed video bitstream to the corresponding digital signal processor responsible for encoding; the digital signal processor responsible for coding is used for coding the multi-path video code stream sent by the digital signal processor responsible for decoding and sending the processed video code stream to the video code stream input and output module.
10. A method for implementing a video gateway is characterized in that the method comprises the following steps:
d. the main control CPU respectively downloads the application programs in the storage module to each digital signal processor and operates the digital signal processors;
e. the main control CPU configures the digital signal processor and the data input and output module according to a system instruction, wherein the system instruction at least carries the path number of data to be processed and the type of each path of data before and after processing;
f. when data is input, the digital signal processor decodes and codes each path of data transmitted by the data input and output module, and then the data is output by the data input and output module,
step e said configuring the digital signal processor to:
e1, the main control CPU determines the digital signal processors to be applied and determines the functions of each digital signal processor and the data flow direction among the digital signal processors; the function refers to being responsible for decoding or encoding;
e2, the master control CPU sends a control command to the digital signal processor to be applied in the step e 1;
e3, the digital signal processor processes correspondingly according to the received control command,
the control command of the step e2 at least carries the function of a digital signal processor; when the digital signal processor is responsible for decoding, the control command also carries the flow direction of the processed data,
the corresponding processing in step e3 is: when the digital signal processor is the digital signal processor responsible for decoding, the corresponding decoding program is operated according to the control command, and the flow direction of the processed data is set; when the digital signal processor is the digital signal processor responsible for coding, the corresponding coding program is operated according to the control command,
the data input output module is configured to: configuring each path of data to be processed by the data input and output module to the input link of the digital signal processor responsible for decoding in step e 1; and e1, configuring the data processed by the digital signal processor responsible for encoding in the step e1 to the output link of the data input and output module.
11. The method of claim 10, wherein step d is preceded by the steps of: and the main control CPU reads and runs the running program in the storage module.
12. The method of claim 10, wherein the application programs of step d comprise an encoding program and a decoding program.
13. The method according to claim 10, wherein the step e of configuring the data input/output module comprises the steps of: the main control CPU informs the data input and output module to open the data input and output channel.
14. The method of claim 10, wherein step f comprises:
f1, the data input and output module transmits each path of input data to the corresponding digital signal processor responsible for decoding; f2, after the digital signal processor responsible for decoding decodes the input data, the processed data is sent to the corresponding digital signal processor responsible for encoding;
and f3, the digital signal processor responsible for coding encodes the received data and sends the processed data to the data input and output module for output.
15. The method according to any one of claims 10 to 14, wherein star connection or mesh interconnection is realized between the digital signal processors through a connection module, and the connection module is a high-speed bus switching chip or a high-speed bus of mesh connection.
16. A video gateway is characterized in that the video gateway mainly comprises a storage module, a main control CPU, a data input and output module, a connection module and a plurality of digital signal processors, wherein,
the storage module is used for storing an operation program of the main control CPU, an application program of the digital signal processor and the number information of the digital signal processor;
the main control CPU is used for acquiring and operating the operating program of the storage module; downloading the application program of the storage module to each digital signal processor respectively; numbering the digital signal processors; configuring a digital signal processor and a video code stream input and output module according to a system instruction, wherein the system instruction at least carries the path number of data to be processed and the type of each path of data before and after processing;
the data input and output module is used for transmitting data input by different data sources to each digital signal processor responsible for decoding and outputting data sent by the digital signal processor responsible for encoding;
the connecting module is used for realizing interconnection between the digital signal processors;
the digital signal processor is used to encode or decode input data,
the master CPU configures the digital signal processor to:
the main control CPU determines digital signal processors to be applied and determines the functions of each digital signal processor and the flow direction of video code streams among the digital signal processors; the function refers to being responsible for decoding or encoding;
the main control CPU sends a control command to the digital signal processor to be applied, wherein the control command at least carries the function of the digital signal processor; when the digital signal processor is in charge of decoding, the control command also carries the flow direction of the processed video code stream;
the digital signal processor performs corresponding processing according to the received control command, wherein the corresponding processing comprises the following steps: the digital signal processor runs a decoding or encoding program according to the control command; when the digital signal processor is responsible for decoding, the method also comprises the steps of setting the flow direction of the processed video code stream,
the main control CPU configures a video code stream input and output module as follows: configuring an input video code stream to be processed by a video code stream input and output module to an input link of the digital signal processor responsible for decoding; and configuring the video code stream processed by the digital signal processor in charge of coding to an output link of the video code stream input and output module.
17. The video gateway of claim 16, wherein the connection module is implemented by a high-speed bus switching chip or a mesh-connected high-speed bus.
18. The video gateway according to claim 16, wherein the decoding-responsible digital signal processor is configured to decode data sent by the data input/output module and send the processed data to the corresponding encoding-responsible digital signal processor; and the digital signal processor responsible for coding is used for coding the data sent by the digital signal processor responsible for decoding and sending the processed data to the data input and output module.
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| CN102263930B (en) * | 2010-05-24 | 2014-02-26 | 杭州华三通信技术有限公司 | Method and device for broadcasting multiple pictures in video conference |
| CN104038394B (en) * | 2014-05-23 | 2018-05-11 | 北京航天发射技术研究所 | High reliability electric-control system |
| CN106941598A (en) * | 2016-01-04 | 2017-07-11 | 中兴通讯股份有限公司 | Many picture bit stream synthetic methods, many picture bit streams synthesis control method and device |
| CN107124575A (en) * | 2017-04-14 | 2017-09-01 | 苏州科达科技股份有限公司 | A kind of media processing method, device and media server |
| CN109246449A (en) * | 2017-07-11 | 2019-01-18 | 中国移动通信集团重庆有限公司 | Video stream distributing method, device, equipment and computer storage medium |
| CN110602460A (en) * | 2019-09-20 | 2019-12-20 | 普联技术有限公司 | Video decoding wall-mounting control method, system and device |
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