CN101316112A - Frequency synthesizer applied to frequency hopping system - Google Patents

Abstract

A frequency synthesizer includes a voltage controlled oscillator, a PLL system, a second frequency divider, a first single sideband mixer, a second single sideband mixer, and a multiplexer. The voltage-controlled oscillator generates an oscillation frequency. The phase-locked loop system comprises a first frequency divider for dividing the frequency by 10 times to the oscillation frequency to generate a first frequency-divided signal. The second frequency divider divides the oscillation frequency by 2 times to generate a second frequency-divided signal, and then divides the frequency by 2 times to obtain a third frequency-divided signal. The first single sideband mixer mixes the second frequency-divided signal with the third frequency-divided signal to generate a first mixed signal. The second single sideband mixer mixes the first mixing signal and the first frequency-divided signal to generate a second mixing signal. The multiplexer selects and outputs the first mixing signal or the second mixing signal.

Description

Frequency Synthesizer Applied in Frequency Hopping System

technical field

The present invention relates to a frequency synthesizer, in particular to a frequency synthesizer used in a frequency hopping system.

Background technique

In many wireless communication systems, a transceiver uses a frequency synthesizer to generate multiple carrier frequencies (or center frequencies) in different frequency bands, thereby transmitting or receiving wireless signals. Taking the new generation of Ultra Wide Band (UWB) technology communication system as an example, it combines multi-band orthogonal frequency division multiplexing (Multi Band OFDM) and frequency hopping technology (Frequency Hopping). According to relevant communication protocol specifications, such as IEEE 802.15.3a formulated by the International Institute of Electrical and Electronics Engineers, the ultra-wideband frequency band is divided into five frequency band modes, of which the first frequency band mode includes 3 sub-frequency bands, and the bandwidth of each sub-frequency band is 528MHz. The center frequencies are 3432MHz, 3960MHz and 4488MHz respectively. In addition, multi-band OFDM uses Time Frequency Interleaving mode (Time Frequency Interleaving) to send and receive OFDM Symbols, that is to say, when sending and receiving each symbol, the system operates in three sub-frequency end. Among them, the length of each symbol is 312.5 nanoseconds (ns), which means that every 312.5 nanoseconds, the system must transmit/receive a symbol of data and complete the frequency hopping action, wherein the frequency hopping action (for example, from the sub-frequency band of 3960MHz to 4488MHz sub-band) specified in 9.5 nanoseconds. Therefore, a frequency synthesizer for this UWB system must cover the center frequencies of the three sub-bands and complete the frequency conversion within 9.5 nanoseconds.

In the traditional frequency synthesizer design, the convergence time of the phase-locked loop frequency change is determined by the phase-locked loop bandwidth; if the convergence time is to be less than 9.5ns, the loop bandwidth must be greater than 100MHz. In order to stabilize the phase-locked loop, the reference frequency used by the phase-locked loop must be more than 10 times the bandwidth of the loop. It can be seen that the traditional frequency synthesizer used in ultra-wideband systems must use a reference frequency above 1 GHz to meet the time specification of frequency hopping, which is not cost-effective and difficult to implement.

In order to solve the problem of frequency hopping convergence time, quite a few research and development units in the world have published solutions. For example: a frequency synthesizer proposed in the International Solid State Circuits Conference (International Solid State Circuits Conference; ISSCC 2005 Sec 11.9 p.216-218) uses three independent phase-locked loop circuits and voltage-controlled oscillators to generate three Carrier signals whose frequencies are 3432MHz, 3960MHz, and 4488MHz respectively. Under this architecture, although the frequency synthesizer does not need to wait for the switching time of the phase-locked loop, but using three sets of phase-locked loops at the same time, the actual power consumption and chip area of the hardware are tripled, which is too expensive.

Another frequency synthesizer architecture proposed by the International Journal of Solid-State Circuits (IEEE Journal of Solid-State Circuits; JSSC 2005Aug.p.1671-1679) uses two independent phase-locked loops and a multiplexer. The working principle is that when the multiplexer selects the carrier signal generated by one of the phase-locked loops, the other set of phase-locked loops performs frequency conversion at the same time; then the multiplexer selects the phase-locked loop that completes the frequency conversion, and the original lock The phase-locked loop performs a new frequency conversion. This pipeline (pipeline) processing can make each frequency synthesizer conversion time from 9.5 nanoseconds to 312.5 nanoseconds. However, since two sets of PLLs consume twice the power consumption and chip area; each set of PLLs and VCOs must be able to cover three sub-bands, resulting in the design complexity of PLLs and VCOs Increase.

The most common way is to use a set of phase-locked loops and voltage-controlled oscillators in conjunction with a single-side-band mixer (Single-Side-Band Mixer, SSB Mixer) to generate three sets of carrier signals, which can theoretically achieve this phase-locked loop The simplest architecture. Please refer to FIG. 1 , which is a schematic diagram of a conventional frequency synthesizer 10 . The frequency synthesizer 10 is used to generate the center frequency of the aforementioned three sub-bands, which includes a voltage-controlled oscillator 11, a phase-locked loop circuit 12, a frequency divider 14, a single-sideband mixer 16 and a multiplexer 18. The voltage-controlled oscillator 11 and the phase-locked loop circuit 12 are used to generate an in-phase quadrature signal (I/Q signal) with a frequency f1, wherein the frequency f1 is 3960 MHz. The frequency divider 14 divides the frequency f1 by a factor of 7.5 to generate an in-phase quadrature signal with a frequency f2, wherein the frequency f2 is 528 MHz. The single-band mixer 16 multiplies the frequencies f1 and f2 to generate another two carriers with frequencies of 3432 MHz and 4488 MHz, and outputs one of the frequencies f3 through a control signal SC1. The multiplexer 18 switches the output frequency f1 (3960 MHz) or f3 (3432 MHz or 4488 MHz) with a control signal SC2. However, the frequency division factor of the frequency divider 14 is 7.5, which is not an integer, which makes it difficult for the frequency divider 14 to generate in-phase and quadrature signals with a phase difference of 90 degrees. The design requires additional complex circuits, and hardware implementation is not easy.

In addition, the image signal (Image Signal) suppression capability is a very important specification when using a single-band mixer; when the image signal is too high, it will cause spur noise at the transmitter and reduce the signal-to-noise ratio at the receiver. When the in-phase and quadrature signals input by the mixer are more ideal (the signal strength is the same, the signal phase difference is 90 degrees), the image signal suppression ability is better. This should be known in the industry, so the reason will not be explained here. However, single-band mixers in high-frequency designs usually cannot obtain ideal in-phase and quadrature signals, so an additional narrow-band filter is required to help filter out the image signals generated after mixing. The difficulty of filtering the image signal can be judged by a Q index (Q index): the Q index is defined here as (the main signal obtained after mixing is divided by (the frequency difference between the main signal and the image signal)). Taking the SSB mixer 16 in FIG. 1 as an example, its Q index is (f1+f2)/(2×f2)=4.25. For a single-band mixer, the higher the Q index, it means that when the image signal appears, it must be connected with a narrow-band filter with a higher Q value (Q factor) to filter out the image signal. Generally speaking, the higher the Q value, the better the filtering capability of the narrow-band filter, but the more difficult it is to design. Therefore, when selecting a phase-locked loop architecture, the mixing frequency that can use a lower Q pointer is also an important point that must be considered in the design.

Please refer to FIG. 2 , which is a schematic diagram of a conventional frequency synthesizer 20 . The frequency synthesizer 20 includes a voltage controlled oscillator 200 , a phase locked loop circuit 210 , frequency dividers 220 and 230 , a multiplexer 240 and SSB mixers 250 and 260 . It can be seen from FIG. 2 that the oscillation frequency of the voltage-controlled oscillator is 4.224 GHz and the two frequencies input to the mixer 250 are respectively 528 MHz and 264 MHz. From this, it can be concluded that the Q index of the mixer 250 is (528+264)/ (2×264)=1.5. When the two frequencies input to the mixer 260 are 4224 MHz and 264 MHz respectively, the Q index of the mixer 260 can be obtained as (4224+264)/(2×264)=8. As a result, the Q index of the mixer 260 is too high, so the difficulty in designing a narrow-band filter is not low. In addition, it can be known from FIG. 2 that a polyphase filter (Poly Phase Filter, PPF) needs to be used inside the VCO 200 to generate in-phase and quadrature signals.

In order to improve the above problems, U.S. Patent Application No. 2006/0183455A1 discloses a frequency synthesizer, which includes a voltage-controlled oscillator, a plurality of frequency dividers, a polyphase filter, a phase-locked loop circuit and a mixer, working The principle is as follows. First, the frequency of 7920MHz is generated by the voltage controlled oscillator, and then the frequency of 3960MHz and 528MHz is generated by the frequency divider. of the three carrier frequencies. Although the calculation result of the Q index of the mixer is 4, which is in line with the design benefits, it is still necessary to use a polyphase filter to generate the in-phase and quadrature signals and to design a voltage-controlled oscillator of nearly 8 GHz.

Therefore, it can be known from the above that when designing a frequency synthesizer applicable to UWB technology, low complexity, low power consumption and area are important issues.

Contents of the invention

The main purpose of the present invention is to provide a frequency synthesizer architecture with high integration, low complexity, low power consumption and area, which can be applied to UWB technology.

A frequency synthesizer disclosed according to the claims of the present invention includes a voltage-controlled oscillator, a phase-locked loop system, a second frequency divider, a first SSB mixer, a second SSB mixer frequency converter and a multiplexer. The voltage-controlled oscillator produces an oscillation frequency of 5.28 GHz according to a voltage control signal. The phase-locked loop system includes a first frequency divider, and the first frequency divider is used for 10-fold frequency division to generate a first frequency-division signal at the oscillation frequency. The phase-locked loop system generates a first frequency-division signal according to the first frequency-division signal. The voltage control signal. The second frequency divider is coupled to the voltage-controlled oscillator, divides the oscillation frequency by 2 to generate a second frequency-divided signal, and then divides the second frequency-divided signal by 2 to generate a third frequency-divided signal . The first SSB mixer is coupled to the second frequency divider and used for mixing the second frequency-divided signal and the third frequency-divided signal to generate a first frequency-divided signal. The second SSB mixer is coupled to the first SSB mixer and the first frequency divider of the PLL system, and is used for mixing the first mixed frequency signal and the first divided frequency frequency signal to generate a second mixed frequency signal. The second single sideband mixer selects to add or subtract frequencies of the first frequency mixing signal and the first frequency division signal according to a first selection control signal to determine the frequency of the second frequency mixing signal. The multiplexer is coupled to the output of the first SSB mixer and the second SSB mixer, and selects to output the first mixed frequency signal or the second mixed frequency signal according to a second selection control signal .

Description of drawings

FIG. 1 is a schematic diagram of a conventional frequency synthesizer.

FIG. 2 is a schematic diagram of a conventional frequency synthesizer.

FIG. 3 is a schematic diagram of a frequency synthesizer used in a frequency hopping system according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the internal structure of the PLL system in FIG. 3 .

FIG. 5 is a schematic diagram of the internal structure of the first frequency divider in FIG. 3 .

FIG. 6 is a schematic diagram of the internal structure of the second frequency divider in FIG. 3 .

Description of reference symbols

10, 20, 300 Frequency Synthesizers

f1, f2, f3, fdd Frequency

18. 370 Multiplexer

240 Selection unit

11, 200, 310 Voltage controlled oscillator

320 Phase-locked loop system

330 First divider

340 Second crossover

350 The first single sideband mixer

360 second SSB mixer

VCTRL Voltage control signal

BS0 Sub-band first selection signal

BS1 Sub-band second selection signal

foc Oscillation frequency

fd1 first frequency division signal

fd2 Second frequency division signal

fd3 The third frequency division signal

fm1 first mixing signal

fm2 second mixing signal

SC1, SC2 control signal

IN1, IN2 input terminals

16, 250, 260 mixer

12, 210, 400 Phase-locked loop circuit

fo1, fo2, fo3 output frequency

OP1, OP2, OP3, OP4 output terminals

14, 220, 230, 410 frequency divider

FD1, FD2, FD3, FD4 frequency division unit

Detailed ways

Please refer to FIG. 3 , which is a schematic diagram of a frequency synthesizer 300 used in a frequency hopping system according to an embodiment of the present invention. To facilitate the explanation of the concept of the present invention, it is assumed that the frequency synthesizer 300 is applied to the aforementioned first frequency band mode of the ultra-wideband communication system (UWB) to generate center frequencies of approximately 3432 MHz, 3960 MHz and 4488 MHz. The frequency synthesizer 300 includes a voltage controlled oscillator 310 , a phase locked loop system 320 , a second frequency divider 340 , a first SSB mixer 350 and a second SSB mixer 360 . The voltage controlled oscillator 310 is used to generate an oscillation frequency foc with a frequency of about 5280 MHz according to a voltage control signal VCTRL. The phase-locked loop system 320 includes a first frequency divider 330, and the phase-locked loop system 320 is used to divide the oscillation frequency foc by 10 times through the first frequency divider 330 to generate a first frequency-divided signal fd1, After dividing the frequency of the first frequency division signal fd1, the frequency obtained after frequency division is compared with an internal reference frequency, and finally a voltage control signal VCTRL is generated to stabilize the oscillation frequency foc of the voltage controlled oscillator 310 at 5280MHz. The second frequency divider 340 is coupled to the voltage-controlled oscillator 310 and divides the oscillation frequency foc by 2 times and 4 times respectively to generate a second frequency-divided signal fd2 and a third frequency-divided signal fd3 . Through even multiple frequency division, the first frequency divider 330 can easily produce the first frequency division signal fd1 comprising inphase/quadrature signals (Inphase/Quadrature signals, I/Q signals), while the second frequency divider 340 produces the first frequency division signal fd1 comprising inphase The second frequency-division signal fd2 and the third frequency-division signal fd3 of the quadrature signal, wherein the in-phase quadrature signal frequency of the first frequency-division signal fd1 is 528MHz, and the in-phase quadrature signal frequency of the second frequency-division signal fd2 is 2640MHz, The frequency of the in-phase and quadrature signals of the third frequency division signal fd3 is 1320 MHz. The first SSB mixer 350 is coupled to the second frequency divider 340, and is used for mixing the second frequency-divided signal fd2 and the third frequency-divided signal fd3 to generate a first mixed frequency signal with a frequency of about 3960 MHz fm1. The second SSB mixer 360 is coupled to the first mixer 330 and the first SSB mixer 350 of the PLL system 320, and is used for mixing the first The frequency mixing signal fm1 is mixed with the first frequency-divided signal fd1 to generate a second frequency mixing signal fm2. The second single-sideband mixer 360 selects and adds or subtracts the frequencies of the first mixed frequency signal fm1 and the first frequency-divided signal fd1 according to the sub-band first selection signal BS0 to determine the frequency of the second mixed frequency signal fm2 4488 or 3432MHz. The multiplexer 370 is used for selecting and outputting the first mixed frequency signal fm1 or the second mixed frequency signal fm2 according to a second sub-band selection signal BS1 . It can be known from the above that the frequency synthesizer 300 can output the output frequencies fo1, fo2 and fo3 with frequencies of about 3432 MHz, 3960 MHz and 4488 MHz, which are the center frequencies of the three sub-bands in the first frequency band mode. For example, when the frequency synthesizer 300 intends to output the output frequency fo1 (3432 MHz), the sub-band first selection signal BS0 controls the second single sideband mixer 360 to subtract the first mixing signal fm1 and the first frequency division signal The frequency of fd1 is then selected by the multiplexer according to the sub-band second selection signal BS1 to output the second mixed frequency signal fm2. In the first SSB mixer 350 and the second SSB mixer 360 , the detailed operating principle of frequency addition and subtraction should be known in the industry, so it will not be repeated here.

Please continue to refer to FIG. 4 , which is a schematic diagram of the internal structure of the PLL system 320 in FIG. 3 . The PLL system 320 includes an output terminal OP1 , an output terminal OP2 , an input terminal IN1 , a PLL circuit 400 , a first frequency divider 330 and a third frequency divider 410 . The output terminal OP1 is used to output the control voltage signal VCTRL to the voltage controlled oscillator 310 . The output terminal OP2 is used to output the first frequency-divided signal fd1 to the second SSB mixer 360 . The input terminal IN1 is used to receive the oscillation frequency foc from the voltage controlled oscillator 310 . The third frequency divider 410 is used to divide the first frequency-divided signal fd1 generated by the first frequency divider 330 by 8 times to generate a feedback frequency fb. The phase-locked loop circuit 400 is used to generate a voltage control signal VCTRL according to the feedback frequency fb and an internal reference frequency fref, so that the voltage-controlled oscillator 310 works stably at 5280 MHz. The reference frequency fref is usually generated by a crystal oscillator inside the phase-locked loop circuit 400, which is 66 MHz in this embodiment, and the phase-locked loop circuit 400 generates a corresponding voltage control signal by comparing the phases of the feedback frequency fb and the reference frequency fref VCTRL is used to control the voltage-controlled oscillator 310, which should be familiar in the industry, and its detailed working principle will not be repeated here.

Please refer to FIG. 5 , which is a schematic diagram of the internal structure of the first frequency divider 330 according to the PLL system 320 in FIG. 3 . The first frequency divider 330 is used for dividing the oscillating frequency foc by 10 times, and includes frequency dividing units FD1 and FD2 . The frequency division unit FD1 is used to divide the oscillation frequency foc by 5 times to generate a frequency fdd, and the frequency division unit FD2 is used to divide the frequency fdd by 2 times to generate an in-phase quadrature (I/Q) And its frequency is the first frequency-divided signal fd1 of 528 MHz. Next, please refer to FIG. 6 , which is a schematic diagram of the internal structure of the second frequency divider 340 in FIG. 3 . The second frequency divider 340 includes an input terminal IN2, output terminals OP3 and OP4, and frequency division units FD3 and FD4. The input terminal IN2 is used to receive the oscillation frequency foc from the voltage-controlled oscillator 310; the output terminal OP3 and the output terminal OP4 are respectively used to output the second frequency-divided signal fd2 and the third frequency-divided signal fd3 to the first SSB mixer 350 . The frequency division unit FD3 is used to divide the oscillation frequency foc by 2 to generate the second frequency division signal fd2 with the in-phase quadrature and the frequency of 2640MHz, and then the frequency division unit FD4 performs 2 frequency division on the second frequency division signal fd2 Multiplied and divided to generate a third frequency-divided signal fd3 of in-phase and quadrature with a frequency of 1320MHz.

According to the foregoing, it can be known that the Q index of the first SSB mixer 350 is (2640+1320)/(2×1320)=1.5, and the Q index of the second SSB mixer 360 is ( 3960+528)/(2×528)=4. Therefore, the frequency synthesizer 300 can use a narrow-band filter with a low Q index to filter out image frequency components, and there is no need to design a difficult filter. In addition, the frequency synthesizer 300 does not need to use a polyphase filter (PPF) to generate the in-phase and quadrature signals of each frequency-divided signal, and the first frequency divider 330 and the second frequency divider 340 perform an even number on the oscillation frequency foc Multiplied to get. Due to the even multiple frequency division design, the first frequency divider 330 and the second frequency divider 340 can generate in-phase and quadrature signals with a duty cycle of 50%, a phase difference of 90 degrees, and the same frequency without complex circuits.

Please note that in the first frequency divider 330 and the second frequency divider 340 , the number of frequency dividers and the frequency division multiplier can be modified according to different system requirements. The number of voltage-controlled oscillators, frequency dividers and frequency division multipliers used above are all designed for the first frequency band mode of the UWB communication system, and are not intended to limit the scope of the present invention.

In summary, the frequency synthesizer of the embodiment of the present invention adopts a structure of a set of voltage-controlled oscillators, a phase-locked loop circuit, and two sets of SSB mixers. The power consumption of a single voltage-controlled oscillator and phase-locked loop circuit will not be too large, and by properly arranging and setting the frequency divider, the SSB mixer does not need to design a difficult narrow-band filter to filter out Image frequency components also reduce the overall design complexity. Therefore, the frequency synthesizer of the present invention has the advantages of high integration, low complexity, low power consumption and area.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (19)

1. A frequency synthesizer for a frequency hopping system, comprising: A voltage-controlled oscillator, used to generate an oscillation frequency according to a voltage control signal; A phase-locked loop system, including a first frequency divider, the phase-locked loop system is used to divide the oscillation frequency by even multiples through the first frequency divider to generate a first frequency-divided signal, and according to The first frequency division signal generates the voltage control signal; A second frequency divider, coupled to the voltage-controlled oscillator, is used to divide the oscillation frequency by an even multiple to generate a second frequency-divided signal and a third frequency-divided signal; a first single-sideband mixer, coupled to the second frequency divider, for mixing the second frequency-divided signal and the third frequency-divided signal to generate a first frequency-divided signal; and A second SSB mixer, coupled to the phase-locked loop system and the first SSB mixer, is used to mix the first mixed frequency signal with the first sub-band first selection signal according to a sub-band first selection signal a frequency-divided signal to generate a second mixed signal; and A multiplexer, coupled to the first SSB mixer and the second SSB mixer, is used to select and output the first mixed frequency signal or the second frequency subband according to a sub-band second selection signal Two mixing signals. 2. The frequency synthesizer as claimed in claim 1, wherein the PLL system further comprises: a first output terminal, coupled to the voltage-controlled oscillator, for outputting the voltage control signal; a second output terminal, coupled to the first frequency division unit and the second SSB mixer, for outputting the first frequency division signal to the second SSB mixer; an input terminal, coupled to the voltage controlled oscillator and the first frequency divider, for receiving the oscillation frequency to the first frequency divider; A third frequency divider, coupled to the first frequency divider, used to divide the first frequency-divided signal to generate a feedback frequency; and A phase-locked loop circuit, coupled to the third frequency divider and the first output terminal, is used to generate the voltage control signal according to the feedback frequency and a reference frequency. 3. The frequency synthesizer as claimed in claim 2, wherein the third frequency divider divides the first frequency-divided signal by 8 times to generate the feedback frequency with a frequency of about 66 MHz. 4. The frequency synthesizer as claimed in claim 1, wherein the first frequency divider divides the oscillation frequency by 10 times. 5. The frequency synthesizer as claimed in claim 1, wherein the first frequency divider comprises: A first frequency division unit, used to divide the oscillation frequency by 5 times to generate a first intermediate frequency; and A second frequency division unit is used for dividing the first intermediate frequency by 2 to generate the first frequency division signal. 6. The frequency synthesizer as claimed in claim 1, wherein the second frequency divider divides the oscillation frequency by 2 to generate the second frequency-divided signal. 7. The frequency synthesizer as claimed in claim 1, wherein the second frequency divider divides the oscillation frequency by 4 to generate the third frequency-divided signal. 8. The frequency synthesizer as claimed in claim 1, wherein the second frequency divider comprises: an input terminal coupled to the voltage-controlled oscillator for receiving the oscillation frequency; a first output terminal, coupled to the first single-sideband mixer, for outputting the second frequency-divided signal; a second output terminal, coupled to the first SSB mixer, for outputting the third frequency-divided signal; A first frequency division unit, used to divide the oscillation frequency by 2 to generate the second frequency division signal; and A second frequency division unit, coupled to the first frequency divider and the second output end, is used for dividing the second frequency division signal by 2 to generate the third frequency division signal. 9. The frequency synthesizer as claimed in claim 1, wherein the second SSB mixer selects to add or subtract the first mixed frequency signal and the first frequency division signal according to the sub-band first selection signal to determine the frequency of the second mixing signal. 10. The frequency synthesizer as claimed in claim 1, wherein the oscillation frequency is 5280 megahertz. 11. The frequency synthesizer as claimed in claim 1, wherein the first frequency-divided signal comprises a first in-phase signal and a first quadrature signal. 12. The frequency synthesizer of claim 11, wherein frequencies of the first in-phase signal and the first quadrature signal are both approximately 528 megahertz. 13. The frequency synthesizer as claimed in claim 1, wherein the second frequency-divided signal comprises a second in-phase signal and a second quadrature signal. 14. The frequency synthesizer as claimed in claim 13, wherein the frequencies of the second in-phase signal and the second quadrature signal are both 2640 MHz. 15. The frequency synthesizer as claimed in claim 1, wherein the third frequency-divided signal comprises a third in-phase signal and a third quadrature signal. 16. The frequency synthesizer as claimed in claim 15, wherein frequencies of the third in-phase signal and the third quadrature signal are both 1320 MHz. 17. The frequency synthesizer as claimed in claim 1, wherein the frequency of the first mixing signal is 3960 MHz. 18. The frequency synthesizer as claimed in claim 1, wherein the frequency of the second mixing signal is 3432 or 4488 megahertz. 19. The frequency synthesizer as claimed in claim 1, wherein the PLL system divides the first frequency-divided signal to generate a first frequency, and compares the first frequency with an internal reference frequency to generate the voltage control signal.

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