CN101312385B - Information encoding and decoding method and apparatus - Google Patents
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Abstract
The invention relates to the communication field, and discloses a method and a device for encoding-decoding information, which increases the encoding gain without changing the frame structure. In the method and the device of the invention, when in generation of check information blocks, partial bits in check synchronous heads of the check information blocks are utilized to carry partial check information, and then according to the bits carrying the partial check information, residual bits in the check synchronous heads are generated. Forward error correction (FEC) coding is carried out to significant bits in synchronous heads of information data and line code blocks after line coding to obtain the check information, and the significant bits are the bits of the type instructing the information data in the same line code block.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to information encoding and decoding techniques.
Background
With the continuous development of communication technology, users have higher and higher requirements for various service qualities such as communication capacity and speed. Since the access network is one of the most technically challenging areas in the entire telecommunication network, various access technologies emerge endlessly in order to meet the increasing requirements of users on bandwidth and realize high speed, broadband and intelligence of the access network. Among them, Passive Optical Network (PON) technology is considered to be the most promising technology.
PON technology is a point-to-multipoint fiber access technology. The PON comprises an Optical line terminal, an Optical Network Unit (ONU), and an Optical Distribution Network (ODN). The Ethernet Passive Optical Network (EPON) technology is a better access technology. The method is mainly characterized by simple maintenance, lower cost, higher transmission bandwidth and high cost performance. In particular, EPON technology can provide bandwidths of 1GHz (gigahertz) and even up to 10GHz, which makes it possible to simultaneously transmit voice, data and video traffic.
Because the EPON is a technology that employs passive optical transmission, components with amplification and relay functions are not used. The transmission distance and the number of branches of an EPON network depend on the power budget and various transmission losses. As the transmission distance or the number of branch ratios increases, the Signal to noise ratio (SNR) of the transmission data gradually decreases, thereby causing more bit errors. In order to solve the problem, a Forward Error Correction (FEC) technology is introduced into the EPON system to improve the interference rejection of the system, so as to increase the power budget of the system.
The basic working principle of FEC in an EPON system is: the method comprises the steps that FEC check code words are added behind Ethernet frames transmitted by a transmitting end, the check code words and the Ethernet frame data to be checked are mutually associated (restrained) by a certain determined rule, the receiving end checks the relation between the Ethernet frame data and the check code words according to the determined rule, and once errors occur in transmission, the relation is destroyed, so that the error correction function of the Ethernet frame data is realized. FEC techniques strive to correct as many errors as possible with as few check bytes as possible, and find an optimal balance between overhead (overhead due to the added check bytes) and the coding gain achieved.
In an EPON system, in order for the transmitted data to be in a format that can be received by the receiver, prior to the FEC technique, a line coding technique is used, which must also ensure that the transmitted data is switched (i.e., shifted between 0 and 1) enough to ensure that the receiver can recover the clock. The line encoder also provides a way to align the data to words while the lines can maintain a good dc balance.
In standards related to EPON systems, a 64b/66b or other line coding scheme with higher coding efficiency has been used in a Physical Coding Sublayer (PCS). The line coding uses a scrambling mode with non-scrambling synchronization characters and control characters.
The 64b/66b line coding mechanism is based on 64 bit information, and adds 2 bit synchronous character (also called synchronous head). These 2-bit sync characters are normally only possible with either "01" or "10". Wherein, the synchronization character of "01" indicates that 64 bits are all data; a sync character of "10" indicates that 64 bits of information contain data and control information. A sync character of "00" or "11" indicates that an error occurred in the transmission process. At the same time, the use of such synchronization characters ensures that the transmitted data is transformed at least once every 66 bits, which facilitates block synchronization. The 64-bit information is scrambled by a self-synchronizing scrambling mechanism, so that the transmitted information is ensured to be switched sufficiently to facilitate clock recovery of a receiving end to the maximum extent.
Currently, one FEC coding scheme for the PCS layer in a 10G EPON system is shown in fig. 1. The left half of fig. 1 is information data to be verified, and the right half is verification information associated with the information data. Specifically, ethernet data entering the PCS layer is first subjected to 64b/66b line coding to form a line coding block in 66 bits (as shown in the left half of fig. 1). And when the number of the line coding blocks reaches the data length required by the FEC coding, performing the FEC coding. And after FEC coding, check information with the length of multiple 64 bits is obtained. The parity information is formed into a plurality of parity chunks in units of 64 bits. Then, a 2-bit parity synchronization header "00" is added to the first parity block, and a 2-bit parity synchronization header "11" is added to the remaining parity blocks, so that the parity blocks in units of 64 bits form a parity information block in units of 66 bits (as shown in the right half of fig. 1), that is, the parity information block includes a parity synchronization header and a parity block. The information data and the check information after being coded by the FEC system are both multiples of 66 bits.
Since the information data is line coded, every 66 bits of line code block contains 2 bits of sync header, and these 2 bits are always different. Whereas the 2 bits of the check sync header in the check information block are always the same. Therefore, the information can be used for realizing the synchronization of the check information block and the line coding block at the receiving end at the same time, thereby facilitating the FEC decoding and the line decoding.
However, the inventors of the present invention found that, in the above-mentioned prior art, the parity information block is synchronized by adding a 2-bit parity synchronization header (i.e., "11" or "00") to the parity block in units of 64 bits, but the improvement of the performance of the FEC coding is not facilitated. This is because, although the number of bits in the check information block is 66 bits in total, the number of bits used for checking the information data is still only 64 bits, and the increased 2 bits are only used to achieve synchronization of the check information block. That is, with the 2-bit overhead added, the gain obtained is relatively small.
In addition, in the prior art, the line coded data is FEC coded, and the line coded data includes redundant information (i.e. 2-bit synchronization header of the line coding block), that is, the FEC codes the line coded redundant information as the FEC coded data part, which reduces the performance of the FEC coding.
Disclosure of Invention
The embodiment of the invention provides an information coding and decoding method and device, which can improve coding gain under the condition that a system does not change a frame structure.
To solve the above technical problem, an embodiment of the present invention provides an information encoding method, including:
when generating the check information block, filling partial check information in the preset X bits in the check synchronization head of the check information block, and generating the residual Y bits in the check synchronization head according to the check information of the X bits;
wherein X and Y are positive integers.
The embodiment of the invention also provides an information decoding method, which comprises the following steps:
and acquiring partial check information from predetermined X bits in a check synchronous head of a check information block, and decoding a line coding block corresponding to the check information block according to the partial check information and check information carried outside the check synchronous head in the check information block, wherein X is a positive integer.
An embodiment of the present invention further provides an information encoding apparatus, including:
the filling module is used for filling partial check information into a predetermined X bit in a check synchronization head of the check information block;
the generating module is used for generating the residual Y bits in the check synchronization head according to the check information of the X bits;
wherein X and Y are positive integers.
An embodiment of the present invention further provides an information decoding apparatus, including:
the acquisition module is used for acquiring the check information from the check information block, wherein part of the check information is acquired from X bits preset in a check synchronization head of the check information block, and X is a positive integer;
and the decoding module is used for decoding the line coding block corresponding to the check information block according to the check information acquired by the acquisition module.
Compared with the prior art, the implementation mode of the invention has the main differences and the effects that:
when generating the check information block, using partial bits in the check synchronization head of the check information block to carry partial check information, and then generating the rest bits in the check synchronization head according to the bits carrying the partial check information. Therefore, under the condition of not changing the frame structure and increasing the complexity, the information used for synchronization in the check information block in the prior art is utilized, the coding gain is improved, and the power budget of the system is increased.
Drawings
Fig. 1 is a diagram illustrating an information encoding method for a PCS layer in a 10G EPON system in the prior art;
FIG. 2 is a flow chart of an information encoding method according to a first embodiment of the present invention;
FIG. 3 is a diagram illustrating an information encoding method according to a first embodiment of the present invention;
FIG. 4 is a flowchart of an information decoding method according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating an information decoding method according to a second embodiment of the present invention;
fig. 6 is a schematic diagram of a line coded block sync header in which information to be checked contains 2 bits according to the first embodiment of the present invention;
fig. 7 is a schematic diagram of information to be checked in an information encoding method according to a third embodiment of the present invention, which does not include secondary bits in a synchronization header of a line coding block;
FIG. 8 is a schematic diagram of secondary bits generated by a 64b/66b line encoder not participating in FEC encoding in accordance with a third embodiment of the present invention;
FIG. 9 is a flowchart of an information encoding method according to a third embodiment of the present invention;
FIG. 10 is a diagram illustrating an information encoding method according to a third embodiment of the present invention;
FIG. 11 is a diagram illustrating an information decoding method according to a fourth embodiment of the present invention;
fig. 12 is a schematic configuration diagram of an information encoding apparatus according to a fifth embodiment of the present invention;
FIG. 13 is a schematic configuration diagram of an information encoding apparatus according to a sixth embodiment of the present invention;
fig. 14 is a schematic structural diagram of an information decoding apparatus according to a seventh embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A first embodiment of the present invention relates to an information encoding method, which is applied to encode a line coding block in an EPON system, and a generated check synchronization header of a check information block is 2 bits, and a specific flow is shown in fig. 2.
In step 210, the transmitting end transmits information data from the reconciliation sublayer to the PCS layer in the form of ethernet data frames (ethernet packets) through the ethernet media independent interface, and then the 64b/66b line encoder line-encodes the information data according to the type of the transmitted information data, which is classified into pure data and data with control information.
Specifically, after data is transmitted from the ethernet media independent interface to the PCS layer, the received information data is divided into K pieces of information in units of 64 bits by a 64-bit information module. Each small block of information is then line coded by a 64b/66b line encoder, i.e. each small block of information is preceded by a 2-bit synchronization header, one bit of which carries information indicating the type of data in the information block, as shown in fig. 3.
Then, step 220 is entered, and the 64b/66b line coded line code block is sent to the scrambler for scrambling, so as to ensure enough switching of the transmitted information to the maximum extent, thereby facilitating the clock recovery of the receiving end. That is, each line code block after 64b/66b line coding is scrambled again (the 2-bit sync header added before each line code block does not participate in the scrambling), and the information data in the scrambled line code block is SiAnd (i ═ 0, 1, … K) indicates that each scrambled line code block contains a 2-bit sync header and 64-bit information data, as shown in fig. 3.
Then, step 230 is entered, and the scrambled line code block is transmitted to the code word buffering/sorting module. And the code word caching/sorting module caches the received data, sorts the received data to form an FEC encoding frame after the data received by the code word caching/sorting module reaches the length required by the FEC encoder, and transmits the FEC encoding frame to the FEC encoder. As shown in fig. 3, the line coding blocks are buffered, and when the data length of the buffered line coding blocks meets the length required by the FEC encoder, the buffered line coding blocks are sent to the FEC encoder, and the data length (i.e. one FEC coding frame) sent to the FEC encoder is 66 × K bits.
Then, proceeding to step 240, the FEC encoder FEC-encodes the received information to generate corresponding check information, the length of the generated check information is multiple of 65, such as 65 × M bits, as shown in fig. 3, PiWhat is carried in the block (i ═ 1, 2.. M) is the generated check information.
Specifically, the FEC encoder performs FEC encoding on the received FEC encoded frame, that is, performs FEC encoding on the scrambled line encoded block, and generates corresponding check information. A constraint relation exists between the check information and the line coding block, and the anti-interference capability of the line coding block is enhanced due to the constraint relation.
Then, step 250 is performed, the FEC code word after FEC coding is transmitted to a check word synchronization header generator, and the check word synchronization header generator generates a check information block including a check block and a check synchronization header. Specifically, as shown in FIG. 3, for each PiAdding 1 bit information to the block, the value of this bit information and this PiThe value of the 1 st bit of the block is the same, and the added bit is the same as the PiThe 1 st bit of the block together constitutes a parity sync header for verifying the information block. For example, PiThe 1 st bit of the block is "1", then a bit of "1" may be added before (or after) the bit, and two bits with "11" together constitute the parity sync header of the parity information block. Thus, a check information block is formed in units of 66 bits, the first 2 bits of the check information block with the length of 66 bits are a check synchronization header, and the second bit to the last bit of the check information block with the length of 66 bits are check information, that is, the second bit in the check information block is used for both synchronization of the check information block and checking of information data. The check synchronization header in each check information block is used for distinguishing the information data and the check information in the FEC coding code word, i.e. for distinguishing SiBlock and PiAnd (5) blocking.
If the concept of checking the first 2 bits of the information block as the sync header and the last 64 bits as the check block is used, the embodiment can be understood as the concept of checking the P with the length of 65 bits i64 bits in the block are filled in the parity block, the remaining 1 bit is filled in the parity sync header, and the value of another bit in the parity sync header is set to a value equal to the bit.
Since one bit of the 2-bit parity sync header carries the parity information, 65 bits of each parity information block can carry the parity information. Compared with the prior art, the embodiment utilizes the bits for synchronization in the check synchronization head in the check information block under the condition of not increasing the system complexity and changing the system frame structure, and allows more check bits in the FEC coding to protect the information data, thereby improving the coding gain of the FEC and further increasing the power budget of the EPON system.
Furthermore, the check synchronization header has the property of having equal bit values by setting the value of another bit in the check synchronization header to a value equal to the bit carrying the check information in the check synchronization header. Since the synchronization header of the line coding block generated by the line coding is "01" or "10", and the verification synchronization header generated in the present embodiment may be only "00" or "11", it is convenient for the receiving end to synchronize the line coding block and the verification information block by using the characteristics of the difference of the line coding block synchronization header and the equality of the verification synchronization header. For example, the receiving end can directly determine whether the block is a line coding block or a check information block by whether the synchronization header is "00" (or "11"), or "10" (or "01"), thereby performing block synchronization.
Then, step 260 is performed, the line coding block portion and the check information block portion in the FEC code word are sent to a framing module to perform data reassembly and framing, and are transmitted to the physical media attachment sublayer in the form of a frame for transmission. As shown in fig. 3, the line coding block and the check information block are recombined and framed, and then transmitted to the physical medium attachment sublayer for transmission after being subjected to rate reconciliation.
It should be noted that in the present embodiment, the information data is scrambled after the line coding is completed and before the FEC coding is performed on the line coding block, but in practical applications, the information data may be scrambled before the line coding is performed, and then the scrambled information data is subjected to the line coding. In addition, in practical application, the adopted line code may also be a 32b/34b code (or other n/(n +2) coding mode), the length of the generated check information is 33 bits (or n +1 bits), and the specific implementation mode is similar to this embodiment and is not described herein again.
A second embodiment of the present invention relates to an information decoding method, and this embodiment corresponds to the information encoding method of the first embodiment, and the specific flow is as shown in fig. 4.
In step 410, the physical media attachment sublayer performs frame synchronization on information received from the physical media dependent sublayer. Specifically, the physical media additional sub-layer transmits the received information to the FEC frame and line coding block synchronization module, and completes the synchronization of the line coding block and the check information block by using the mutual difference of the line coding synchronization header and the equal characteristic of the check synchronization header.
Next, step 420 is entered, and after the synchronization between the line coding block and the check information block is completed, the first bit in each check information block is removed. Because one bit in the check synchronization header of the check information block carries part of the check information, and the 2-bit check synchronization header is '00' or '11' and has the characteristic of the same bit value, the check information carried in the check information block can be obtained by removing one bit in the check synchronization header, thereby facilitating the subsequent FEC decoding.
Then, step 430 is performed, the synchronized line coding block and the check information block from which one bit in the check synchronization header has been removed are sent to an FEC code word sorting module for sorting FEC frames, and when data in the FEC code word sorting module forms one FEC frame, the FEC frame is sent to an FEC decoder, as shown in fig. 5.
Then, proceeding to step 440, the FEC decoder decodes the received FEC frame, and encodes the synchronization header and the 64-bit information data (i.e. S) in the line code block during the decoding processiBlock) is recovered while redundant check information, i.e., P, is recoverediThe blocks are removed as shown in fig. 5.
Specifically, the FEC decoder performs FEC decoding on the line coding block corresponding to the check information block according to the acquired check information carried in the check synchronization header and the check information carried in the check information block except for the check synchronization header. The FEC decoder performs FEC decoding on the line coding block corresponding to the check information block by the following method: and FEC decoding is carried out on the information data in the line coding block and the synchronous head of the line coding block.
Next, step 450 is entered, and the FEC decoded information is segmented, that is, the FEC decoded information is divided into K segments (i.e. into K line code blocks), each segment containing 64 bits of line coded information data and 2 bits of synchronization header of the line code block, as shown in fig. 5.
Then, step 460 is entered to descramble the information divided into K segments, that is, to descramble the information data in K line code blocks.
Then, step 470 is entered to perform 64b/66b line decoding on the K line encoded blocks after descrambling. Specifically, 64b/66b line decoding is performed on the information data in each descrambled line coding block and the synchronization header in the line coding block, and the information after 64b/66b line decoding is transmitted to the reconciliation sublayer through the ethernet media independent interface, as shown in fig. 5.
It should be noted that, in the first embodiment, since the information data is scrambled after the line coding is completed and before the line coding block is FEC coded, the information data in the K line coding blocks needs to be descrambled between FEC decoding and 64b/66b line decoding in the present embodiment. In the first embodiment, if the information data is scrambled before the line coding and then the scrambled information data is line coded, it is necessary to descramble the information data after the 64b/66b line decoding is completed in the present embodiment.
A third embodiment of the present invention relates to an information encoding method, which is substantially the same as the first embodiment, and is different from the first embodiment in that, in the first embodiment, check information is obtained by FEC encoding of information data and a sync header in a line encoding block after line encoding, as shown in fig. 6; in the present embodiment, the check information is obtained by FEC encoding the information data in the line coding block after line coding and the important bits in the synchronization header, which are bits indicating the type of the information data in the same line coding block as shown in fig. 7.
Specifically, since one bit of the synchronization header of the line coding block of 2 bits generated after 64b/66b line coding of 64 bits of information data is used for indicating the type of information data in the line coding block in addition to block synchronization, the bit can be regarded as a significant bit and another bit as a secondary bit, and since the synchronization header of 2 bits in the line coding block has different characteristics (i.e., "01" or "10"), that is, the secondary bit can be obtained by inverting the significant bit. Therefore, the 64-bit information data and the important bit can be used as input data bits of an FEC encoder to be sent to a code word buffering/sorting module, and when the data bits in the code word buffering/sorting module form an FEC encoded data frame, the data bits are sent to the FEC encoder together for FEC encoding; while the secondary bits in the line coding block sync header do not participate in the FEC coding, as shown in fig. 8. The scheme can ensure that the check information blocks with the same size protect less important information bits, thereby improving the performance of FEC coding.
The flowchart and schematic diagram of the present embodiment are shown in fig. 9 and 10, respectively. Only one important bit in the synchronization header of the line coding block after the line coding of 64b/66b participates in the FEC coding, so the length of the information participating in the FEC coding is multiple of 65 bits, and the length of the check information generated after the FEC coding is still multiple of 65 bits. The method of generating the check information blocks is the same as the first embodiment, and the second bit in each check information block is used for checking both the synchronization of the check information blocks and the information data.
Therefore, as one bit in the synchronization header of the line coding block does not participate in the FEC coding, the information amount needing to be protected by the FEC coding is effectively reduced, more check bits protect useful information data as little as possible, so that higher coding gain is obtained, and the power budget of the EPON system is increased. Moreover, because the bits for indicating the data type are protected by FEC coding, the greater coding gain can improve the correct probability of judging the data type.
A fourth embodiment of the present invention relates to an information decoding method, and this embodiment corresponds to the information encoding method of the third embodiment. Therefore, the present embodiment is substantially the same as the second embodiment, and the difference is that in the second embodiment, the receiving side performs FEC decoding on the information data in the line coding block and the synchronization header of the line coding block, and after completing the FEC decoding, the information subjected to 64b/66b line decoding is the information data in the line coding block after FEC decoding and the synchronization header in the line coding block; in the present embodiment, the receiving end performs FEC decoding on the information data in the line coding block and the important bits in the synchronization header of the line coding block, where the important bits are bits for indicating the type of the information data in the same line coding block (as shown in fig. 11), and after completing FEC decoding, the information that performs 64b/66b line decoding is the information data in the FEC-decoded line coding block and the important bits in the synchronization header of the line coding block, and the secondary bits in the synchronization header that do not participate in the FEC decoding.
A fifth embodiment of the present invention relates to an information encoding device including: the circuit coding module is used for carrying out circuit coding on the information data to be verified and generating a circuit coding block containing a synchronous head; the check information generating module is used for carrying out FEC encoding on the information data and the synchronous head in the line encoding block to obtain check information; the filling module is used for filling partial check information into a predetermined X bit in a check synchronization head of the check information block; the generating module is used for generating the residual Y bits in the check synchronization head according to the check information of the X bits, wherein X and Y are positive integers; and the sending module is used for sending the check information block and the line coding block corresponding to the check information block. In the embodiment, the bits for synchronization in the check synchronization header in the check information block are utilized, so that the coding gain is improved without changing the frame structure and increasing the complexity, and the power budget of the EPON system is further increased.
The line coding block in this embodiment is a line coding block of an EPON, the size of the check synchronization header is 2 bits, X is 1, Y is 1, and the generating module sets the value of Y bits of 1 bit to a value equal to X bits of 1 bit. The check synchronization head has the characteristic of equal bit value, so that the receiving end can utilize the mutual difference of the line coding synchronization head and the equal characteristic of the check synchronization head to carry out the synchronization of the line coding block and the check information block.
In addition, the present embodiment may further include a scrambling module configured to scramble the information data. The scrambling result of the scrambling module is output to the line coding module; or the scrambling module scrambles the information data output by the line coding module and outputs the scrambling result to the verification information generating module.
Specifically, as shown in fig. 12, data from an upper layer enters a 64b/66b line encoder (i.e., a line encoding module), and the line encoder adds a corresponding sync header according to the type of information to generate a line encoding block including a 2-bit sync header. Then the 64-bit information data in the line coding block is sent to a scrambler (namely a scrambling module) to be scrambled and then sent to a buffer/sequencer, and meanwhile, the synchronization head in the line coding block is also directly sent to the buffer/sequencer. The buffer/sorter stores the data according to a certain rule, and when the stored data reaches the information length 66 × K required by the FEC encoder (i.e., the check information generation module), the buffer/sorter sequentially transfers the set of information to the FEC encoder, and then starts to receive and store a new information block. And after receiving the information group, the FEC encoder performs FEC encoding on the information group according to the selected encoding rule to generate corresponding check information. Then the check information is sent to the check information block buffer/sorter in sequence by taking 65 bits as a unit, and simultaneously the 1 st bit in each unit is repeatedly sent to the check information block buffer/sorter, thus realizing the functions of the filling module and the generating module, and leading the first bit and the second bit in the generated check information block to form a check synchronization head of the check information block. Meanwhile, the FEC encoder transmits the information group to the information data buffer/sorter, and the information data buffer/sorter and the check information block buffer/sorter transmit the data to the transmitting module after waiting for framing and then transmit the data to the physical medium additional sub-layer after receiving the full data.
A sixth embodiment of the present invention relates to an information encoding device, and is substantially the same as the fifth embodiment except that in the fifth embodiment, a check information generating module is configured to FEC-encode information data and a sync header in a line encoding block to obtain check information; in this embodiment, the check information generating module is configured to perform FEC encoding on the information data in the line coding block and an important bit in the synchronization header to obtain the check information, where the important bit is a bit used to indicate a type of the information data in the same line coding block.
Specifically, as shown in fig. 13, data from an upper layer enters a 64b/66b line encoder for encoding, the line encoder adds a corresponding sync header according to the type of information (the sync header may be placed at the head end or the tail end of the information), and then the line encoder transmits the 66-bit information containing the sync header, which has been line encoded, to a corresponding buffer/sorter. Specifically, the 64b/66b line encoder sends 64-bit information data to a scrambler for scrambling, and then sends the scrambled 64-bit information data and important bits in a synchronization header of a line coding block to a first buffer/sequencer for preparation for FEC coding; the secondary bits in the line code block sync header are transmitted to a sync header buffer/sequencer. Each buffer/sequencer stores data according to certain rules. When the data stored in the first buffer/sorter reaches the information length 65 xK required by the FEC encoder, the first buffer/sorter sequentially transfers the set of information to the FEC encoder, and then starts to receive and store a new information block. And after receiving the information group, the FEC encoder performs FEC encoding on the information group according to the selected encoding rule to generate corresponding check information. Then the check information is sent to the check information block buffer/sorter in 65 bit unit in sequence, and the 1 st bit in each unit is also sent to the check information block buffer/sorter repeatedly, so that the first bit and the second bit in the generated check information block form the check synchronization head of the check information block. Meanwhile, the FEC encoder transmits the information group to the information data buffer/sorter, and after the information data buffer/sorter and the check information block buffer/sorter receive full data, the data is transmitted to the transmitting module to wait for framing and then is transmitted to the physical medium additional sub-layer.
In the embodiment, one bit in the synchronization header of the line coding block does not participate in the FEC coding, so that the amount of information which needs to be protected by the FEC coding is effectively reduced, more redundancy (check bits) protect as little useful information data as possible, thereby obtaining a larger coding gain and increasing the power budget of the EPON system. Moreover, because the bits for indicating the data type are protected by FEC coding, the greater coding gain can improve the correct probability of judging the data type.
A seventh embodiment of the present invention relates to an information decoding apparatus corresponding to the information encoding apparatus in the fifth or sixth embodiment, and specifically, as shown in fig. 14, includes a receiving module for receiving a check information block and a line encoding block corresponding to the check information block; the synchronization module is used for synchronizing the received check information block and the line coding block corresponding to the check information block according to the check synchronization head and the synchronization head of the line coding block; the acquisition module is used for acquiring the check information from the synchronized check information block, wherein part of the check information is acquired from X bits preset in a check synchronization head of the check information block, and X is a positive integer; and the decoding module is used for decoding the line coding block corresponding to the check information block according to the check information acquired by the acquisition module.
The decoding module can decode the line coding block corresponding to the check information block by the following modes: FEC decoding is carried out on the information data in the line coding block and the synchronous head of the line coding block; or, performing FEC decoding on the information data in the line coding block and the important bits in the synchronization header of the line coding block, where the important bits are bits used for indicating the type of the information data in the same line coding block.
The information decoding apparatus in this embodiment may further include a line decoding module and a descrambling module. The line decoding module is used for performing line decoding on the information data in the line coding block output by the decoding module and the synchronous head in the line coding block; or, the information data in the line coding block output by the decoding module and the important bit in the synchronization head of the line coding block are decoded together with other bits in the synchronization head which are not input into the decoding module, and the type of the information data is judged according to the important bit in the synchronization head when the line is decoded.
The descrambling module is used for descrambling the information data. Specifically, the descrambling module descrambles the information data output by the line decoding module, or the descrambling module descrambles the information data output by the decoding module and outputs the descrambling result to the line decoding module.
In summary, in the embodiment of the present invention, when generating the parity information block, a part of bits in the parity synchronization header of the parity information block is used to carry partial parity information, and then the remaining bits in the parity synchronization header are generated according to the bits carrying the partial parity information. Therefore, under the condition of not changing the frame structure and increasing the complexity, the information used for synchronization in the check information block in the prior art is utilized, the coding gain is improved, and the power budget of the system is further increased.
The method comprises the steps of enabling 1 bit in a 2-bit check synchronization head to bear check information, setting the value of the other 1 bit in the check synchronization head to be equal to the value of the bit bearing the check information, enabling the check synchronization head to have the characteristic of bit equality, and enabling a receiving end to utilize the characteristics of the difference of the line coding synchronization head and the equality of the check synchronization head to carry out synchronization of a line coding block and a check information block.
And performing FEC encoding on the information data after the line encoding and important bits in the synchronization header of the line encoding block to obtain check information, wherein the important bits are bits used for indicating the type of the information data in the same line encoding block. Because part of bits used for synchronizing the line coding blocks in the synchronization header do not participate in the FEC coding, the information amount needing to be protected through the FEC coding is effectively reduced, more redundancy (check bits) can protect useful information data as little as possible, so that higher coding gain is obtained, and the power budget of an EPON system is increased. Moreover, because the bits for indicating the data type are protected by FEC coding, the greater coding gain can improve the correct probability of judging the data type.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (25)
1. An information encoding method, comprising the steps of:
when generating the check information block, filling partial check information in the preset X bits in the check synchronization head of the check information block, and generating the residual Y bits in the check synchronization head according to the check information of the X bits; wherein X and Y are positive integers.
2. The information encoding method according to claim 1, wherein X ═ Y;
the mode of generating the remaining Y bits in the parity synchronization header according to the parity information of the X bits is as follows:
setting a value of the Y bit to a value corresponding to the X bit.
3. The information encoding method according to claim 2,
the X is 1 and the Y is 1.
4. The information encoding method according to any one of claims 1 to 3, further comprising, before the step of generating the check information block, the steps of:
and performing line coding on the information data to be verified to generate a line coding block containing the information data and the synchronization head.
5. The information encoding method of claim 4, further comprising, after the step of generating the line coding block and before the step of generating the check information block, the steps of:
carrying out forward error correction coding on the information data and the synchronous head in the line coding block to obtain the check information; or,
carrying out forward error correction coding on the information data in the line coding block and the important bits in the synchronous head to obtain the check information; the important bit is a bit used for indicating the type of information data in the same line coding block.
6. The information encoding method of claim 5, wherein before the step of performing line coding or between the step of performing line coding and the step of performing forward error correction coding, further comprising the steps of:
and scrambling the information data.
7. The information encoding method of claim 4, further comprising, after the step of generating the check information block, the steps of:
and transmitting the check information block and the line coding block corresponding to the check information block.
8. The information encoding method according to claim 4, wherein the line coding of the information data to be verified is 64b/66b coding or 32b/34b coding.
9. An information decoding method, comprising the steps of:
and acquiring partial check information from predetermined X bits in a check synchronous head of a check information block, and decoding a line coding block corresponding to the check information block according to the partial check information and check information carried outside the check synchronous head in the check information block, wherein X is a positive integer.
10. The information decoding method according to claim 9, further comprising, before the step of decoding the line coding block corresponding to the check information block, the steps of:
receiving the check information block and a line coding block corresponding to the check information block;
and synchronizing the received check information block and the line coding block corresponding to the check information block according to the check synchronization head and the synchronization head of the line coding block.
11. The information decoding method according to claim 9 or 10, wherein the line coding block corresponding to the check information block is decoded as follows:
carrying out forward error correction decoding on the information data in the line coding block and the synchronous head of the line coding block; or,
carrying out forward error correction decoding on the information data in the line coding block and the important bits in the synchronous head of the line coding block; the important bit is a bit used for indicating the type of information data in the same line coding block.
12. The information decoding method according to claim 11, further comprising, after the step of decoding the line coding block corresponding to the check information block, the steps of:
carrying out line decoding on the information data in the line coding block after the forward error correction decoding and the synchronous head in the line coding block; or,
and carrying out line decoding on the information data in the line coding block after the forward error correction decoding and the important bits in the synchronous head of the line coding block, as well as other bits in the synchronous head which do not participate in the forward error correction decoding, and judging the type of the information data according to the important bits in the synchronous head during the line decoding.
13. The information decoding method according to claim 12, further comprising, after the step of line decoding or between the step of forward error correction decoding and the step of line decoding, the steps of:
descrambling the information data.
14. An information encoding device, comprising:
the filling module is used for filling partial check information into a predetermined X bit in a check synchronization head of the check information block;
a generating module, configured to generate remaining Y bits in the check synchronization header according to the check information of the X bits;
wherein X and Y are positive integers.
15. The information encoding apparatus according to claim 14, wherein X is Y;
the mode of the generating module generating the remaining Y bits in the check synchronization header according to the check information of the X bits is as follows:
setting a value of the Y bit to a value corresponding to the X bit.
16. The information encoding apparatus according to claim 15,
the X is 1 and the Y is 1.
17. An information encoding device as claimed in any one of claims 14 to 16, further comprising:
and the line coding module is used for performing line coding on the information data to be verified to generate a line coding block containing the information data and the synchronization head.
18. The information encoding apparatus of claim 17, further comprising:
a check information generating module, configured to perform forward error correction coding on the information data and the synchronization header in the line coding block to obtain the check information;
or, the check information generating module is configured to perform forward error correction coding on the information data in the line coding block and the important bit in the synchronization header to obtain the check information; the important bit is a bit used for indicating the type of information data in the same line coding block.
19. The information encoding apparatus of claim 18, further comprising:
the scrambling module is used for scrambling the information data;
the scrambling result of the scrambling module is output to the line coding module; or,
the scrambling module scrambles the information data output by the line coding module and outputs a scrambling result to the verification information generation module.
20. The information encoding apparatus of claim 18, further comprising:
and the sending module is used for sending the check information block and the line coding block corresponding to the check information block.
21. An information decoding apparatus, comprising:
the acquisition module is used for acquiring the check information from the check information block, wherein part of the check information is acquired from X bits preset in a check synchronization head of the check information block, and X is a positive integer;
and the decoding module is used for decoding the line coding block corresponding to the check information block according to the check information acquired by the acquisition module.
22. The information decoding apparatus of claim 21, further comprising:
the receiving module is used for receiving the check information block and the line coding block corresponding to the check information block;
the synchronization module is used for synchronizing the received check information block and the line coding block corresponding to the check information block according to the check synchronization head and the synchronization head of the line coding block;
the acquisition module acquires the check information from the synchronized check information block.
23. The information decoding apparatus according to claim 21 or 22, wherein the decoding module decodes a line coding block corresponding to the check information block as follows:
carrying out forward error correction decoding on the information data in the line coding block and the synchronous head of the line coding block; or,
carrying out forward error correction decoding on the information data in the line coding block and the important bits in the synchronous head of the line coding block; the important bit is a bit used for indicating the type of information data in the same line coding block.
24. The information decoding apparatus of claim 23, further comprising:
the line decoding module is used for performing line decoding on the information data in the line coding block output by the decoding module and the synchronous head in the line coding block; or,
the line decoding module is used for performing line decoding on the information data in the line coding block and the important bit in the synchronization head of the line coding block which are output by the decoding module, and other bits in the synchronization head which do not participate in the forward error correction decoding, and the type of the information data is judged according to the important bit in the synchronization head during line decoding.
25. The information decoding apparatus of claim 24, further comprising:
the descrambling module is used for descrambling the information data;
the descrambling module descrambles the information data output by the line decoding module, or the descrambling module descrambles the information data output by the decoding module and then outputs a descrambling result to the line decoding module.
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| CN 200710109329 CN101312385B (en) | 2007-05-23 | 2007-05-23 | Information encoding and decoding method and apparatus |
| PCT/CN2008/071015 WO2008141582A1 (en) | 2007-05-23 | 2008-05-20 | A method and apparatus for information coding/decoding |
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| CN 200710109329 CN101312385B (en) | 2007-05-23 | 2007-05-23 | Information encoding and decoding method and apparatus |
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| CN101938326B (en) * | 2009-06-30 | 2013-02-27 | 中兴通讯股份有限公司 | Method and device for decoding control information of long-term evolution system |
| CN102195738B (en) | 2010-03-02 | 2015-06-10 | 中兴通讯股份有限公司 | Synchronous processing method and device for downlink frames of GPON (gigabit passive optical network) system |
| CN102025449B (en) * | 2010-11-19 | 2015-10-21 | 中兴通讯股份有限公司 | A kind of method of synchronization of data code blocks and device |
| CN108183771B (en) | 2012-12-18 | 2021-03-23 | 华为技术有限公司 | Data processing method, equipment and system in optical network system |
| US9654250B2 (en) * | 2014-11-10 | 2017-05-16 | Futurewei Technologies, Inc. | Adding operations, administration, and maintenance (OAM) information in 66-bit code |
| CN113381836B (en) * | 2020-02-25 | 2023-03-24 | 华为技术有限公司 | Line coding method and device |
| CN113196661B (en) * | 2021-03-15 | 2024-06-18 | 华为技术有限公司 | Data processing method and related device |
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