CN101312173A - Semiconductor chip package substrate and bonding pad structure thereof - Google Patents

Abstract

A semiconductor die package substrate comprising: a core layer; a conductive structure disposed on a surface of the core layer; and an insulating layer covering the conductive structure, wherein the insulating layer has at least one patterned opening; exposing part of the conductive structure of the patterned opening to be used as a patterned welding pad; the patterning opening comprises a central part and a plurality of wing parts extending outwards from the periphery of the central part; by means of the design of the central area and the wing surface areas of the bonding pad, the adhesion effect of the bonding pad and the solder ball is increased.

Description

Semiconductor chip package substrate and pad structure thereof

technical field

The present invention relates to a ball grid array (BGA) substrate, in particular to a packaging substrate structure with a solder mask define (Solder Mask Define, SMD) pad design for planting solder balls.

current technology

In a general BGA semiconductor package, it is usually necessary to use a substrate as a chip carrier, so that the chip is placed on one side of the substrate and the chip is electrically connected to the conductive structure on the substrate, and the other side of the substrate is planted with a plurality of solder joints. The ball is electrically connected with the conductive structure, and then welded with a printed circuit board by means of the solder ball, so that the chip forms an electrical connection relationship with the printed circuit board through the conductive structure and the solder ball.

Please refer to Fig. 1 a, the substrate 10 mainly includes a core layer 12 and a solder resist layer 14, and a conductive structure (not shown in the figure) and a pad 16 connected to the conductive structure are formed on the core layer 12 for bonding by means of the pad Welding ball, wherein welding pad can be divided into SMD welding pad and non-solder mask limit (NoneSolder Mask Define, NSMD) welding pad, and welding pad as shown in Figure 1a is a SMD welding pad 16, and wherein welding pad 16 size is larger than The opening 20 on the solder resist layer 14 is to limit the exposed area of the pad 16 by means of the opening 20; as shown in Figure 1 b, when the package body 2 with the SMD pad 16 design is electrically connected to the printed circuit board 3, it is By means of the solder balls 18 and the solder pads 16 on the printed circuit board 3, the contact area between the solder balls 18 and the solder pads 16 is small, which will cause the temperature cycle test (Board Level Temperature Cycling Test, Board TCT) results are not good, and it is easy to cause stress concentration between the bonding surface of the solder ball 18 and the solder pad 16, or at the discontinuity of the geometric size, resulting in cracks.

The NSMD pad means that the periphery of the pad 16 is not covered by the solder resist layer 14, as shown in Figure 2a, that is, the surface of the pad 16 and part of the core layer 12 around the pad 16 are exposed by the opening 20 to facilitate solder balls. 18; when the BGA package uses NSMD pad 16, although there is a better TCT result between the solder ball 18 and the pad 16, as shown in Figure 2b, when the package is subjected to external stress, the NSMD soldering The pad 16 is easily separated from the core layer 12 because it is not covered by the solder resist layer, which also causes cracks in the signal circuit.

U.S. Patent No. 6,201,305 and Taiwan Patent No. I234838 propose a structural design of an NSMD pad to improve the separation between the pad and the core layer; in U.S. Patent No. 6,201,305, the pad has multiple radial shapes Arranged arms are in the shape of a starfish, and a circular opening is designed on the solder mask so that the outer ends of the arms are covered by the solder mask, while the central area of the solder pad, the inner end of the arm and the part between the two adjacent arms The core layer is exposed, so that the solder balls are in contact with the exposed part of the pad and part of the core layer at the same time. In addition to increasing the contact area, it is also difficult to separate from the core layer; and Taiwan Patent No. I 234838 uses the above concept to open a solder pad on the pad. The plurality of hollow parts makes the outer end of the solder pad covered by the solder resist layer, while the inner end of the solder pad and the part of the core layer exposed through the hollow part are in contact with the solder ball at the same time, so as to increase the contact area of the solder ball.

However, the above-mentioned US Patent No. 6,201,305 and Taiwan Patent No. I234838 are both aimed at improving the NSMD pads. In the manufacturing process, a complex and difficult etching process must be performed for the shape of the pads.

Contents of the invention

In order to solve the above problems, one object of the present invention is to provide a semiconductor chip packaging substrate and its bonding pad structure, which can increase the contact area between the bonding pad and the solder ball and improve the adhesion effect by means of the design of the patterned bonding pad.

One of the objects of the present invention is to provide a semiconductor chip packaging substrate and its solder pad structure, which uses the patterned opening design of the solder resist layer to define the patterned solder pads, which can effectively improve the adhesion between the solder pads and solder balls and the packaging quality. .

One of the objectives of the present invention is to provide a semiconductor chip packaging substrate and its bonding pad structure, which can strengthen the adhesion effect between the bonding pad and the solder ball, so that the packaged component has better TCT test results.

One of the objects of the present invention is to provide a semiconductor chip packaging substrate and its pad structure, which uses the patterned opening design of the solder resist layer to design and limit the patterned solder pad, wherein the patterned opening of the solder resist layer is made by using general lithography technology It can be completed without additional manufacturing process and has the advantage of simple manufacture.

In order to achieve the above object, an embodiment of the present invention provides a semiconductor chip packaging substrate, comprising: a core layer; a conductive structure disposed on a surface of the core layer; and an insulating layer covering the conductive structure, wherein the insulating layer There is at least one patterned opening; the patterned opening exposes part of the conductive structure as a patterned pad; and the patterned opening includes a central portion and a plurality of wing portions extending outward from the periphery of the central portion.

Another embodiment of the present invention provides a pad structure defined by a solder resist layer, comprising: a central region; and a plurality of airfoil regions extending outward from the periphery of the central portion.

The following is a detailed description with the help of specific embodiments and accompanying drawings, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Brief description of the drawings

FIG. 1 a and FIG. 1 b are respectively a cross-sectional view of an SMD solder pad connected with a solder ball and a schematic diagram of a board-level package in the prior art.

FIG. 2 a and FIG. 2 b are respectively a cross-sectional view and a schematic diagram of cracks of NSMD pads connected with solder balls in the prior art.

FIG. 3 a and FIG. 3 b are respectively a top view of a package substrate and a cross-sectional view along line AA of an embodiment of the present invention.

FIG. 4 is a schematic diagram of a solder pad structure defined by a solder resist layer according to an embodiment of the present invention.

specific implementation

Please refer to FIG. 3a and FIG. 3b, which are respectively a top view of the packaging substrate structure and a cross-sectional view along line AA of an embodiment of the present invention. As shown in the figure, the packaging substrate includes a core layer 30; on the surface, and the conductive structure 32 is preset as the end of the pad; an insulating layer, such as a solder resist layer 34, covers the surface of the core layer 30 to cover the conductive structure 32, and at least one pattern is formed on the solder resist layer 34 The opening 36 is made so that the position of the opening 36 corresponds to the position of the end portion, wherein the opening 36 includes a central portion 361 and a plurality of wing portions 362 extending outward from the periphery of the central portion 361, so that the end is defined by the central portion 361 and the wing portion 362 The exposed area of the portion, and the exposed end portion is used as a solder pad 38 for bonding with a solder ball (not shown in the figure).

Continuing the above description, the central part 361 is a circular hole, and the wing part 362 is arc-shaped. The number of the wing parts 362 can be two or more and connected to the central part 361 in a symmetrical distribution relationship. This has a central The openings 36 of the portion 361 and the wing portion 362 are formed by using a general packaging substrate solder mask manufacturing method through exposure and development by lithography; the material of the core layer 30 is mainly epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 resin or FR5 resin, the conductive structure 32 is a patterned metal layer formed by a copper film laminated on the surface of the core layer 30 and patterned by etching and other manufacturing processes.

In the present invention, since the opening of the solder resist layer has a circular central portion and a peripheral wing portion, the solder pad 38 defined by the opening of the solder resist layer includes a circular central region 381 as shown in FIG. 4 . , and a plurality of arc-shaped airfoil regions 382 connected to the periphery of the central region 381, the airfoil regions 382 are symmetrically distributed on the periphery of the central region 381, and this design of the welding pad 38 with the airfoil region 382 will be additionally increased The contact area between the solder pad 38 and the solder ball is to increase the adhesion effect between the solder pad 38 and the solder ball, thereby having better packaging quality; at the same time, with the help of the design of the airfoil region 382 of the solder pad 38, it can also have better TCT test results.

On the other hand, in the present invention, since the shape of the welding pad is defined by the opening of the solder resist layer, the solder resist layer only needs to be formed by general photolithography in the manufacturing process, and the manufacture is simple, so that the present invention simultaneously It has the advantages of simple manufacturing process and can effectively improve the adhesion effect between the pad and the solder ball.

The above-described embodiments are only for illustrating the technical idea and characteristics of the present invention, and its purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. When the protection scope of the present invention cannot be limited with it, That is, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still fall within the protection scope of the present invention.

Description of main component symbols

2 package body

3 printed circuit board

10 Substrate

12 core layer

14 Solder Mask

16 pads

18 solder balls

20 openings

30 core layer

32 conductive structure

34 solder mask

36 openings

361 Central Department

362 wings

38 pads

381 Central District

382 wing area

Claims (10)

1. A semiconductor chip packaging substrate, comprising: a core layer; a conductive structure disposed on a surface of the core layer; and an insulating layer covering the conductive structure, It is characterized in that the insulating layer has at least one patterned opening; The patterned opening exposes a portion of the conductive structure as a patterned pad; and The patterned opening includes a central portion and a plurality of wing portions extending outward from the periphery of the central portion. 2. The semiconductor chip packaging substrate as claimed in claim 1, wherein the conductive structure is a patterned metal layer. 3. The semiconductor chip package substrate as claimed in claim 1, wherein the insulating layer is a solder resist layer. 4 . The semiconductor chip package substrate as claimed in claim 1 , wherein the wing portions are symmetrically distributed on the periphery of the central portion. 5. The semiconductor chip package substrate as claimed in claim 1, wherein the central portion is circular. 6. The semiconductor chip package substrate as claimed in claim 1, wherein the wing portion is arc-shaped. 7. A pad structure defined by a solder mask, comprising: a Central District; and A plurality of airfoil areas extend outward from the periphery of the central area. 8 . The pad structure defined by the solder resist layer as claimed in claim 7 , wherein the plurality of airfoil regions are symmetrically distributed around the central region. 9. The pad structure defined by the solder resist layer as claimed in claim 7, wherein the central region is circular. 10 . The solder pad structure defined by the solder resist layer as claimed in claim 7 , wherein the airfoil region is arc-shaped. 11 .

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