CN101309401B - Fast advanced video encoding rate computing method and apparatus thereof - Google Patents
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Abstract
The invention provides a method for calculating video encoding rate and a video encoding rate calculating device adopting the method, which is characterized in that the calculating device comprises a parallel scanning device, a parallel level run detecting device, a parallel meter selecting device, a parallel level run rate calculating device and a bit number accumulator which are connected in sequence. The video encoding rate calculating device provided by the invention solves the problem that the estimating speed of residual error block rate in a AVS encoder is low, so that the calculating capability of the high definition AVS real time encoder or the multi-path AVS real time encoder video is enhanced.
Description
Technical field
The invention belongs to the Digital Video Processing field, relate to a kind of video rapid rate computational methods and device thereof, especially a kind of parallel rapid rate computational methods and device thereof that is applicable to advanced audio/video fgs encoder device.
Background technology
Along with the continuous development of audio frequency and video industry, the audio/video encoding/decoding technology also reaches its maturity in the world.JVT has released MPEG-4 AVC/H.264 video coding technique international standard, China has then released audio/video encoding standard AVS (Advanced Audio-Video Coding Standard in InformationTechnology, information technology advanced audio/video coding) national standard.These video encoding standards can efficiently be compressed the great vision signal of amount of information under the condition that keeps the video subjective quality, greatly reduce memory space and network bandwidth requirement.All kinds of Predicting Techniques have been extensive use of among the AVS with further raising code efficiency.In order to select suitable predictive mode, AVS has used the important component part of rate-distortion optimization (RDO) model selection as video coding, the distortion of AVS encoder utilization coding and the bit rate behind the coding calculate the cost of each pattern, and judge the predictive mode of current the best with this.
Therefore, in the process of coding, after encoder is predicted respectively with each predictive mode current macro, need the basis for estimation of the bit number of precognition coding back current macro as model selection.Usually, data transfer rate is easier to learn behind the pairing coding of syntactic elements such as the cost of macro block head and motion vector encoder bit number, and will calculate the bit number after total bit number also needs the residual error data coding.The entropy coding of AVS adopts 2 dimension variable length codes (2D-VLC) that the residual error coefficient after the conversion is carried out entropy coding.Coding generally carries out in the mode that scans 8x8 piece residual error coefficient piece one by one, and for the high definition or multichannel real-time encoder of high-throughput, this process is too slow.Therefore adopt the rate method of estimation of simplifying usually, and the error that method of estimation is brought has caused performance loss.
Therefore, need adopt application-specific integrated circuit (ASIC) (ASIC) to realize that the parallel rapid rate calculation element of high-throughput is the most suitable selection to the field of video applications of carrying out real-time coding at some as high-definition format or multi-channel video signal.
Summary of the invention
The purpose of this invention is to provide a kind of parallel fast rate computational methods and device thereof of the AVS of being applicable to encoder, solve the low problem of residual block rate estimating speed in the AVS coding, be high-definition format or multi-channel video AVS real-time encoder raising rate computing capability.
The present invention is achieved by the following technical solutions:
A kind of video encoding rate calculation element comprises the parallel scanning means that connects successively, and line level distance of swimming checkout gear, parallel table choice device and line level distance of swimming rate calculation element and bit number accumulator; Can also comprise basic syntactic element rate calculation element, link to each other with the input of bit number accumulator.
N data of the parallel processing of phase weekly of video encoding rate calculation element; Parallel scanning means scans the residual error data piece, each cycle and a line output N+1 data, and N data of final cycle output, wherein final cycle is finished the cycle of certain 8x8 piece total data output for each device.
Scan-data exports to and line level distance of swimming checkout gear.Parallel scanning means comprises two and above identical scanning element, and with ping-pong work, each scanning element hocket Data Receiving and output can receive data in the time of parallel scanning means dateout.The scan mode of parallel scanning means is according to the type scanning or the field scan mode of current macro model selection, and wherein macro block mode comprises frame pattern and field mode.
Further, but described and line level distance of swimming checkout gear N+1 data of phase parallel processing weekly.To phase weekly except that N+1 data, the parallel maximum N level-distance of swimming that generates of all the other maximum N non-zero is to data.And line level distance of swimming checkout gear detects between per two non-zero level at interval the zero level number and uses priority encoder to detect last non-zero level as its distance of swimming.And the input data of line level distance of swimming checkout gear are from parallel scanning means, and level-distance of swimming exports parallel table choice device to data.
Further, described parallel table choice device checks successively that from the high frequency of input data maximum N incoming level-distance of swimming is right, respectively each level-distance of swimming is made comparisons to the detected maximum level of parallel table choice device in level and the current 8x8 data block; According to comparative result and the suitable variable length code table of residual block type selecting; Described residual block type comprises the infra-frame prediction luminance block, inter prediction luminance block and chrominance block.Parallel table choice device is selected suitable variable length code table (Variable Length Code according to data, the VLC table), select signal and level-distance of swimming that data are exported to parallel encoding level distance of swimming rate calculation element in the variable length code table. the input data of parallel table choice device are from line level distance of swimming checkout gear also, and data export parallel encoding level distance of swimming rate calculation element to.
Further, described and line level distance of swimming rate calculation element comprises N identical code level distance of swimming rate computing unit, each level distance of swimming rate computing unit concurrent working, each code level distance of swimming rate computing unit is handled a level-distance of swimming to data, and line level distance of swimming rate calculation element N data of phase parallel processing weekly.According to selecting information and present encoding data message compute level-distance of swimming to the bit number behind coding from the variable length code table of parallel table choice device.Add up the earlier number of coded bits of N parallel encoding level distance of swimming rate computing unit output of parallel encoding level distance of swimming rate calculation element, and export data to the bit number accumulator.
Further, the bit number of the syntactic element except that residual error coefficient behind index Columbus sign indicating number coding in the described basic syntactic element rate calculation element computing macro block.And export the result to the bit number accumulator.Described bit number accumulator, accumulative total obtains current macro coded bit number under current predictive mode from the bit number of parallel encoding level distance of swimming rate calculation element and basic syntactic element rate calculation element.
Further, the invention provides a kind of video encoding rate computing method, it is characterized in that: may further comprise the steps,
A), scanning residual error data piece, N+1 data of maximum processing of phase weekly;
B), detect scan-data, data are carried out level-distance of swimming to coding;
C), check successively that from high frequency maximum N incoming level-distance of swimming is right, detected maximum level is made comparisons in respectively that each level-distance of swimming is right level and the current 8x8 data block, selects suitable variable length code table according to comparative result;
D), according to selected coding schedule, calculate the bit number of present encoding pattern;
E), the bit number of the syntactic element except that residual error data behind index Columbus sign indicating number coding in the computing macro block;
F), total bit number of accumulative total current macro coding.
The present invention can pipeline system uninterruptedly handle a plurality of macro blocks under phase 8 the throughput weekly.Critical path delay operating frequency under main stream of CMOS technology is enough to satisfy the requirement of high definition and multichannel SD real-time encoder.If be phases 8 point weekly from the input residual error data of integer transformer unit, then input to the calculating of macro block rate and finish total processing delay 40 cycles only from first 8 residual error data of macro block, be enough to satisfy the demand of streamlined RDO model selection.The present invention realizes as the very lagre scale integrated circuit (VLSIC) (VLSI) of rapid rate counting circuit among the AVS, can be applied in high performance AVS high definition or the SD real-time video coding chip, solve the low problem of residual block rate estimating speed in the AVS coding, be high-definition format or multi-channel video AVS real-time encoder raising rate computing capability.
Description of drawings
Fig. 1 is applicable to the parallel rapid rate computing device structure block diagram of AVS encoder;
Fig. 2 is applicable to the streamline schematic diagram of the parallel rapid rate calculation element of AVS encoder.
Label declaration:
1, parallel scanning means; 2 and line level distance of swimming checkout gear;
3, parallel table choice device; 4 and line level distance of swimming rate calculation element;
5, bit number accumulator; 6, basic syntactic element rate calculation element.
Embodiment
Now in conjunction with the accompanying drawings, specify embodiments of the present invention:
Below explanation is applicable to the parallel rapid rate computing device structure and the workflow of AVS encoder under the N=8, is phase 1x8 piece weekly from the input residual error coefficient of integer transform block, and horizontal direction is imported to low frequency successively by high frequency.
As Fig. 1, the parallel rapid rate calculation element that is applicable to the AVS encoder comprises parallel scanning means 1 and line level distance of swimming checkout gear 2, parallel table choice device 3 and line level distance of swimming rate calculation element 4, bit number accumulator 5, more than device is connected in series successively, comprises that also basic syntactic element rate calculation element 6 also is connected in the input of bit number accumulator simultaneously.
At first, parallel scanning means 1 is handled 8x8 residual error data piece and is finished scanning.Phase and 9 data of line output weekly except that final cycle, 8 data of final cycle output.
Then, and 9 data of line level distance of swimming checkout gear 2 processing inputs, be that all the other 8 non-zero generate distances of swimming except that the 9th data, maximum 8 the level-distances of swimming of parallel generation are right.
Secondly, parallel table choice device 3 is selected suitable VLC table for each input data, and the VLC table is selected with level-distance of swimming exporting parallel encoding level distance of swimming rate calculation element 4 to.
Once more, and comprise 8 parallel encoding level distance of swimming rate computing units in the line level distance of swimming rate calculation element 4, level-distance of swimming of each cell processing is right, be used to from the VLC of parallel table choice device 3 table selection information and present encoding data message, for example information such as predictive mode, frame pattern calculates level-distance of swimming to the bit number behind coding.The add up number of coded bits of 8 parallel encoding level distance of swimming rate computing units output of parallel encoding level distance of swimming rate calculation element 4, and export data to bit number accumulator 5.
At last, the bit number of the syntactic element in basic syntactic element rate calculation element 6 computing macro blocks except that residual error coefficient after the index Columbus sign indicating number is encoded, and export the result to bit number accumulator 5.Bit number accumulator 5 accumulative totals are from the bit number of parallel encoding level distance of swimming rate calculation element and basic syntactic element rate calculation element, all the other syntactic element expenses of macro block obtain current macro bit number behind the accurate coding under the current predictive mode with adding up from the bit number of 4 8x8 pieces in the multicycle and adding.
The parallel rapid rate calculation element workflow that is applicable to the AVS encoder is as follows: as Fig. 2, parallel scanning means receives from the residual error data of integer transform unit and deposits the parallel scanning element of current free time in, after the 4th 1x8 piece input of each 8x8 residual block, by select logic according to scanning sequency by high frequency from the low frequency output factor, cycle 0 output is from the coefficient of high frequency numbering 0 to 8, the coefficient of cycle 1 output numbering 8 to 16, the rest may be inferred until the coefficient of cycles 7 output numbering 56 to 63, and remaining output factor 8 is filled any non-zero.For the 8x8 piece, carry out the processing in 8 cycles altogether, weekly 9 coefficients of phase output.Another can receive the input residual error data when parallel scanning element output scanning data.
And line level distance of swimming checkout gear 2 detects in 9 coefficients except that between coefficient 8 nonzero coefficients 0 number as the distance of swimming of nonzero coefficient, herein coefficient press high frequency to the order of low frequency successively from 0 open numbering.Detect last non-zero level with priority encoder, if the input the 9th data be 0, unless current be final cycle, the distance of swimming of last non-zero level can't be determined.When the distance of swimming of last non-zero level can't be determined, and line level distance of swimming checkout gear 2 to set its distance of swimming values be thereafter 0 several, and this non-zero level is delayed to next period treatment.If being complete 0,9 inputs of following one-period data continue to postpone and its distance of swimming value is increased by 8, import the data non-full zeros or reach final cycle until 9, count addition with the distance of swimming of this non-zero and from 0 of input high-frequency data this moment, and make up with the non-zero itself that postpones, replace first input zero and export parallel table choice device 3 to, handle a 8x8 piece and needed for 8 cycles as first pair of level-distance of swimming.
Parallel table choice device 3 is initialized as 0 with its inner maximum level absolute value (maxAbsLevel) before a 8x8 BOB(beginning of block), select signal (CurrentVLCTable) to be chosen as VLC0_Intra/VLC0_Inter or VLC0_Chroma in current table according to block type.Computing begins the back and compares according to the level absolute value (absLevel) of frequency order from high to low with maximum level absolute value and input.If absLevel is bigger, then maxAbsLevel is updated to absLevel, and the table selection signal (CurrentVLCTable) suitable according to the absLevel selection, be that the right selection of a last level-distance of swimming is constant otherwise keep table to select signal (CurrentVLCTable).So repeat level-distances of swimming all in the 8x8 piece to all having selected suitable VLC table, with the VLC table select with level-distance of swimming to exporting to and line level distance of swimming rate calculation element 4.8 level-distances of swimming at the most for input simultaneously are right, and this process utilizes combinational logic to finish in the same clock cycle, handle the 8x8 piece and need for 8 cycles altogether, but if need further to promote also streamlined of clock frequency.
And line level distance of swimming rate calculation element 4 comprises 8 identical level distance of swimming rate computing units.Level distance of swimming rate computing unit is checked incoming level, need not to handle output 0 if incoming level is 0 explanation current data.If import data is that non-zero is then searched relevant level-distance of swimming to acquisition conversion coefficient (trans_coefficient) in the VLC table that parallel table choice device is selected, and adds the level signal sign bit.If the miss distance of swimming calculation of transform coefficients (trans_coefficient) that then utilizes, and in maximum run (MaxRun) table and VLC table, search distance of swimming acquisition reference level absolute value RefAbsLevel, and utilize level and RefAbsLevel to calculate generation escape level difference (escape_level_diff).Utilize the index Columbus sign indicating number difference calculation of transform coefficients (trans_coefficient) and escape level difference (escape_level_diff) number of coded bits of (if existence) of the suitable exponent number of AVS standard appointment at last, obtain the coded-bit sum after the addition.1 level-distance of swimming of phase processing is right weekly for each level distance of swimming rate computing unit, thereby and line level distance of swimming rate calculation element 4 can to handle maximum 8 level-distances of swimming right the phase weekly, will obtain the right total bit number of maximum 8 the level-distances of swimming of current input and export bit number accumulator 5 to after its output bit number addition.The processing time of a 8x8 piece was 8 cycles.
Syntactic element in basic syntactic element rate calculation element 6 computing macro blocks except that residual error coefficient, macro block (mb) type for example, motion-vector prediction and motion vector difference (for the inter-frame forecast mode macro block), the bit number of each syntactic element behind corresponding exponent number index Columbus sign indicating number coding calculated in intra prediction mode selections (for the intra prediction mode macro block) etc.And export the result to bit number accumulator 4.Basic syntactic element rate calculation element 6 is not present in the streamline, and its need order or parallel rate of finishing all the other syntactic elements before the residual error coefficient rate that streamline is finished whole macro block is calculated are estimated to get final product.
In the whole macro block processing procedure of bit number accumulator 5 accumulative total from the bit number of parallel encoding level distance of swimming rate calculation element 4 and basic syntactic element rate calculation element 6.Comprise in 32 cycles from the residual error coefficient bit number of 4 8x8 pieces and from all the other syntactic element expenses of basic syntactic element rate calculation element 6, obtain current macro bit number behind the accurate coding under the current predictive mode.
The present invention can pipeline system uninterruptedly handle a plurality of macro blocks under phase 8 the throughput weekly.Critical path delay operating frequency under main stream of CMOS technology is enough to satisfy the requirement of high definition and multichannel SD real-time encoder.If be phases 8 point weekly from the input residual error data of integer transformer unit, then input to the calculating of macro block rate and finish total processing delay 40 cycles only from first 8 residual error data of macro block, be enough to satisfy the demand of streamlined RDO model selection.
Rate computational methods of the present invention and device thereof can be widely used in the AVS real-time coding system.The above is preferred embodiment of the present invention only, is not limited to the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. a video encoding rate calculation element is characterized in that: comprise the parallel scanning means that is used for block scan, the also line level distance of swimming checkout gear that is used to generate the level run-length data, the parallel table choice device that is used to select coding schedule that connects successively, also line level distance of swimming rate calculation element and the bit number accumulator that is used to calculate bit number.
2. video encoding rate calculation element as claimed in claim 1 is characterized in that: also comprise basic syntactic element rate calculation element, link to each other with the input of bit number accumulator.
3. video encoding rate calculation element as claimed in claim 1, it is characterized in that: parallel scanning means comprises two and above scanning element, with ping-pong work, described scanning element hocket Data Receiving and output can receive data in the time of parallel scanning means dateout.
4. as claim 1 or 3 described video encoding rate calculation elements, it is characterized in that:
A), N data of the parallel processing of phase weekly of described video encoding rate calculation element; Described parallel scanning means scans the residual error data piece, each cycle and a line output N+1 data, N data of final cycle output;
B), the data of described parallel scanning means are from integer transformer, scan-data exports to and line level distance of swimming checkout gear.
5. video encoding rate calculation element as claimed in claim 4 is characterized in that: described final cycle is finished the cycle of certain 8x8 piece total data output for each device.
6. video encoding rate calculation element as claimed in claim 1 is characterized in that:
A) but, described and line level distance of swimming checkout gear N+1 data of phase parallel processing weekly;
B), the parallel maximum N level-distance of swimming that generates of all the other maximum N non-zero is to data except that N+1 data to phase weekly for described and line level distance of swimming checkout gear;
C), the input data of described and line level distance of swimming checkout gear are from parallel scanning means, level-distance of swimming exports parallel table choice device to data.
7. as claim 1 or 6 described video encoding rate calculation elements, it is characterized in that: described and line level distance of swimming checkout gear detects the zero level number at interval between per two non-zero level, use priority encoder to detect last non-zero level, output level-distance of swimming is to data.
8. video encoding rate calculation element as claimed in claim 1 is characterized in that:
A), described parallel table choice device is selected suitable variable length code table (Variable Length Code, VLC table) according to the level-distance of swimming that receives to data;
B), described parallel table choice device selects signal and level-distance of swimming to export to and line level distance of swimming rate calculation element data are parallel in the variable length code table;
C), the input data of described parallel table choice device from and line level distance of swimming checkout gear, data export to and line level distance of swimming rate calculation element.
9. as claim 1 or 8 described video encoding rate calculation elements, it is characterized in that:
A), described parallel table choice device will be imported data and check successively that from high frequency maximum N incoming level-distance of swimming is right;
B), the detected maximum level of parallel table choice device is made comparisons in respectively that each level-distance of swimming is right level and the current 8x8 data block;
C), described parallel table choice device, according to comparative result and the suitable variable length code table of residual block type selecting; Described residual block type comprises infra-frame prediction luminance block, inter prediction luminance block and chrominance block.
10. video encoding rate calculation element as claimed in claim 1 is characterized in that:
A), described and line level distance of swimming rate calculation element comprises N identical code level distance of swimming rate computing unit, each level distance of swimming rate computing unit concurrent working;
B), each the code level distance of swimming rate computing unit in the described and line level distance of swimming rate calculation element handles a level-distance of swimming to data, and line level distance of swimming rate calculation element N data of phase parallel processing weekly; According to selecting information, present encoding data message from the variable length code table of parallel table choice device, compute level-distance of swimming is to the bit number behind coding;
C), add up the earlier number of coded bits of N parallel code level distance of swimming rate computing unit output of described and line level distance of swimming rate calculation element, and export data to the bit number accumulator.
11. video encoding rate calculation element as claimed in claim 2, it is characterized in that: the bit number of the syntactic element in the described basic syntactic element rate calculation element computing macro block except that residual error coefficient after the index Columbus sign indicating number is encoded, and export the result to the bit number accumulator.
12. video encoding rate calculation element as claimed in claim 1 or 2, it is characterized in that: described bit number accumulator, accumulative total from and line level distance of swimming rate calculation element, or accumulative total from and the bit number of line level distance of swimming rate calculation element and basic syntactic element rate calculation element, obtain current macro coded bit number under current predictive mode.
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