CN101304528A - Mapping method of video processor video data and memory storage space - Google Patents

Abstract

The invention belongs to the technical field of digital video encoding and decoding, and in particular relates to a mapping method between video data of a video processor and memory storage space; it includes six steps, and fully utilizes data access in different pages of a memory with a paging structure according to the mapping relationship Concurrency and other characteristics, divide the luminance component and chrominance component of the video image, and map them to the corresponding page address, row address and column address of the memory in the way of luminance grouping and chrominance grouping, so that the video processor can process the video data The access bandwidth is greatly improved; the storage, replacement and update process of the video image entering the memory is stipulated in the memory, thus ensuring the normal operation of the video processor.

Description

Mapping method of video processor video data and memory storage space

technical field

The invention belongs to the technical field of digital video encoding and decoding, and in particular relates to a mapping method between video data of a video processor and memory storage space.

Background technique

One of the main features of the video processor is the large amount of video data processed, which requires a high data bus bandwidth to meet the requirements of real-time video processing. Most of today's video codec processors use a hybrid video coding model, and the standards followed by the design include MPEG4, H.264, AVS, etc. These standards all use technologies such as spatial predictive coding, temporal predictive coding, and loop filtering. The biggest problem that these technologies bring to the design of video codec processors is that the codec processor needs to access a large amount of original image and reconstructed image data, which not only requires the video codec to be plugged with a large-capacity memory to store the original video data and reconstructed video data, and the memory is required to provide sufficient data bandwidth for the data access of the video codec.

SDRAM, DDR SDRAM, DDR2SDRAM and other memories are widely used in video codec processors because of their large storage space and low cost. These memories are characterized by a paging structure, and their storage space is determined by three address indexes, which are row address, column address and page address; the working characteristic is that when accessing different rows in the same page, the upper The row to be accessed once is precharged, and then an activation command is sent to the row to be accessed currently. The above operations will introduce wait cycles on the data bus; while the rows in different pages can be operated in parallel, the activation command for the rows in another page can be covered by the data reading process in the current page. Similarly, The precharge command for the row in the current page can be covered by the data reading process of another page. Reasonable use of this feature can maximize the data rate on the data bus, that is, each beat has an address unit. data output.

According to the characteristics of SDRAM, DDR SDRAM, DDR2SDRAM and other memories, it can be concluded that in order to maximize the data rate, the data storage addresses pointed to by two adjacent accesses should be located in the same row of the same page, or in different pages. Inside.

A video image generally includes two components: a luminance component and a chrominance component, wherein the chrominance component generally includes two color difference components. The codec process of the video image by the video processor usually processes the luma component and the chrominance component separately. Studying the data access characteristics of the video codec processor and the process of original video image acquisition, we can find that the data access of the video processor is basically block-based data access. Blocks are placed in different memory pages, and the data in each block is best stored in a row of a memory page, and the acquisition and input process of the original video image is basically based on the data input sequence of the row, in order to reduce the delay , to reduce storage buffer overhead, and the original video images can be stored in rows.

The processing flow of the video codec processor to the video sequence mainly refers to the processing process of the video image, including the processing process of different frame types, the processing process when there are special circumstances such as frame skipping, and the resulting access to the memory Video image storage overlay and other processes. Only by properly arranging the mapping between the video images entering the memory and the storage space of the memory can the smooth progress of the video processing flow be guaranteed.

Since the processing of video by the video processor is a continuous process, the original video image continuously enters the memory, and the stored video image in the memory is continuously refreshed, which makes the storage of the video data of the video processor in the storage space itself It contains two levels of content. The first level is to select a storage space for the video image currently entering the memory. The specific content involved includes how much storage space needs to be opened up, and a set of initial row addresses and initial columns for each storage space. Address, how to assign the initial row address and initial column address for the video image entering the memory, can be called frame memory management; the second level is to store the video data in the selected storage space according to a certain format Storage, the specific content involved is to assign page address, row address and column address for each pixel in the video image.

After literature search, it was found that Hansoo Kim and In-Cheol Park designed a video for MPEG-2 video decoder and SDRAM with different paging numbers in "High-Performance and Low-Power Memory-Interface Architecture for video Processing Applications". The main idea of the data storage format is to store by block, the data in the same block is arranged in the same line of the same page, and the data of adjacent blocks is arranged in different pages of SDRAM. This method can also be used for video decoders, but for video encoders, especially those using H.264 standard, MPEG4 standard and AVS standard, the search window involved in motion estimation often spans more data According to this method, the data access rate cannot be better improved, and there is no corresponding solution for selecting an appropriate storage space according to the video processing flow for the video image that needs to be stored for each frame.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art, provide a reasonable design, can better meet the needs of the video processor's normal encoding and decoding process, and support the mapping of video data and memory storage space for special processing such as frame skipping method.

The object of the present invention is to adopt such technical solution to realize: it is characterized in that described mapping method comprises following six steps:

(a) set the number of pixels PPU stored in each address unit of the memory; set the initial row address and the initial column address of the Totalspace group; the luminance component, the Cb chrominance component and the Cr chrominance component of the video image to be stored according to the row A division method in division and block division is divided into corresponding luma grouping, Cb chrominance grouping and Cr chrominance grouping;

(b) in the Totalspace group initial row address and initial column address of setting, select one group of initial row address and initial column address as the initial row address and initial column address of the video image of the required storage that enters memory currently;

(c) assigning the page address and row address of the luminance group;

(d) assigning the column address of each brightness pixel in the brightness group;

(e) according to the page address and the row address of the brightness group, obtain the page address and the row address of the corresponding Cb chrominance grouping and Cr chrominance grouping;

(f) Allocate the column addresses of the chroma pixels in the Cb chroma group and the Cr chroma group.

Because the method of the present invention divides the video image according to the luminance component and the chrominance component, and maps it into the corresponding page address, row address and column address of the memory in the mode of luminance grouping and chrominance grouping, this mapping relationship makes full use of the band The paging structure memory has the characteristics of concurrency of data access in different pages, which greatly improves the video processor's access bandwidth to video data; and stipulates the storage, replacement and update of video images entering the memory in the memory process, thus ensuring the normal operation of the video processor.

Description of drawings

Fig. 1 is the schematic diagram that the pixel point of an address unit occupies the address bus when PPU is equal to 4 in the present invention

Fig. 2 is the schematic diagram that luminance component is divided by row in the present invention

Fig. 3 is the schematic diagram that Cb chroma component and Cr chroma component are divided by row in the present invention

Fig. 4 is one of the schematic diagrams of division of luminance components by blocks in the present invention

Fig. 5 is one of the schematic diagrams that Cb chroma component and Cr chroma component are divided by blocks in the present invention

Fig. 6 is one of the schematic diagrams of the mapping relationship between the video image to be stored in the present invention and the initial row address and the initial column address

Fig. 7 is one of the schematic diagrams of the mapping relationship between the brightness group and the page address row address of the memory in the present invention

Fig. 8 is the second schematic diagram of the mapping relationship between the brightness group and the page address row address of the memory in the present invention

Fig. 9 is a schematic diagram of the luminance grouping obtained by dividing by blocks in the present invention and expanding by rows

Fig. 10 is the second schematic diagram of the mapping relationship between the video image to be stored in the present invention and the initial row address and the initial column address

Figure 11 is a schematic diagram of the Cb chroma grouping or Cr chrominance grouping obtained by dividing blocks in the present invention and expanding them by row

Fig. 12 is a schematic diagram of the address bus occupied by the pixels of an address unit when the PPU is equal to 2 in the present invention

Figure 13 is the third schematic diagram of the mapping relationship between the video image to be stored in the present invention and the initial row address and the initial column address

Fig. 14 is the second schematic diagram of division of luminance components by blocks in the present invention

Fig. 15 is the schematic diagram of Cb chroma component and Cr chroma component divided by blocks in the present invention. The second term involved in the present invention is explained as follows:

Brightness component:

For progressive video sequences, the luminance component of a video image refers to a luminance array formed by all the luminance pixels of a frame of image. A luminance array composed of pixels interlaced, or one up and one down.

Chroma components:

For the progressive sequence, the chrominance component of the video image refers to a chrominance array formed by all the chrominance pixels of a frame of image; The luminance pixels form a chrominance array in an interlaced manner, or one up and one down. Cb chroma pixel and Cr chroma pixel:

The pixels in the chroma component have two different types of pixels, one of which is called a Cb chroma pixel, and the other is called a Cr chroma pixel.

Cb chroma component and Cr chroma component:

In the chroma component, the array composed of all Cb chroma pixels is named Cb chroma component; the array composed of all Cr chroma pixels is named Cr chroma component.

floor(x):

A floor function whose function value is the largest integer not greater than x.

ceil(x):

The upper integer function, the function value of which is the smallest integer not less than x.

Detailed ways:

The mapping method of video processor video data and memory storage space of the present invention adopts above-mentioned (a) to (f) steps to realize, wherein:

The number of pixels PPU stored in the address unit in the (a) step is determined by the memory data bus bit width, and the PPU pixels in each address unit occupy the data bus bit width of the address unit in order; the Totalspace group The initial row address and the initial column address correspond to the total number of frames of video images to be stored, and each group of initial row address and initial column address corresponds to a group of address spaces;

Described row division and block are divided into: row division: the brightness component of the video image that needs storage is divided into LiH line brightness grouping by row, the Cb chrominance component of the video image that needs storage is divided into LiH/ 2-line Cb chrominance grouping, divide the Cr chrominance component of the video image to be stored into LiH/2-line Cr chrominance grouping by line; block division: divide the luminance component of the video image to be stored into McH line×McV A luminance group of 16×16 size is listed, and the Cb chrominance component of the video image to be stored is divided into McH row×McV column Cb chrominance grouping of 8×8 size, and the Cr chrominance component of the video image to be stored is divided into The components are divided into McH row×McV column 8×8 Cr chrominance groups.

According to the mapping relationship, the present invention makes full use of the concurrency of data access in different pages of the memory with paging structure, divides the luminance component and chrominance component of the video image, and maps them to the memory in the way of luminance grouping and chrominance grouping In the corresponding page address, row address and column address, the access bandwidth of the video processor to the video data is greatly improved; the storage, replacement and update process of the video image entering the memory is stipulated in the memory, thus ensuring normal operation of the video processor.

Below in conjunction with accompanying drawing and embodiment, the present invention will be further described:

Example 1: Encoder 7-frame storage scheme

The memory used is W986432DH 512K×4BANKS×32BITSDRAM of Winbond Company, the data bus bit width of this memory is 32 bits, and the number of pages Banknum is equal to 4; the resolution of the video image is 720×576, and the sampling format is 4:2:0; That is, the proportional relationship between the brightness pixel point Y and the number of two color difference pixel points Cb and Cr is: Y:Cb:Cr is equal to 4:1:1, P frame coding refers to 2 frames of images at most, between two consecutive P frames , or there are at most two B frames between the P frame and the I frame; the video processor requires a separate storage space for the original image and the reconstructed image, and the two do not overlap each other in the memory; the processed video sequence is a frame sequence.

It can be obtained from the data bus bit width of the memory: PPU is equal to 4, and the situation that PPU pixels occupy the address bus is shown in Figure 1.

The number of reference images required for P frame compression, the number of B frames stored between two consecutive P frames, or the number of B frames stored between a P frame and an I frame, and the storage requirements of the video processor for the original image and the reconstructed image can be obtained : The total frame number of video images to be stored, Totalspace, is equal to 7. For this reason, 7 groups of initial row addresses and initial column addresses are set in the memory: the first group of initial row addresses and initial column addresses are 0 and 0 respectively, represented by S1 ; The initial row address and initial column address of the second group are 160 and 0, represented by S2; the initial row address and initial column address of the third group are 320 and 0, represented by S3; the initial row address and initial column address of the fourth group are 480 and 0, denoted by S4; the initial row address and initial column address of the fifth group are 640 and 128, denoted by S5; the initial row address and initial column address of the sixth group are 1280 and 0, denoted by S6; the initial group 7 The row address and the initial column address are 1280 and 128, represented by S7.

The luminance component of the original image to be stored is divided into 576 luminance groups by row, as shown in Figure 2; the Cb chroma component is divided into 288 Cb chrominance groups by row, and the Cr chroma component is divided into 288 Cr Chromaticity grouping, as shown in Figure 3; the brightness components of the reconstructed image to be stored are divided into 16×16 brightness groups of 36 rows×45 columns, as shown in Figure 4; the Cb chrominance components are divided into blocks Cb chrominance groups of 8×8 sizes with 36 rows×45 columns, and Cr chrominance components are divided into Cr chrominance components with 8×8 sizes of 36 rows×45 columns by block, as shown in FIG. 5 .

I, B, and P represent three types of original images: I frame, B frame, and P frame. i, p represent I frames, and P frames are reconstructed images generated after encoding. The video processing flow is as follows: the original images are sequentially entered into the memory at a certain time interval, and the encoding of the original images starts after three original images are stored. The original image is coded according to the structure of IBBPBBPBBP.... After the I frame and P frame are stored, they can be encoded, and the B frame cannot be encoded until its forward adjacent I frame or P frame and backward adjacent I frame or P frame are encoded and reconstructed. It encodes.

The initial row address and initial column address of the original image to be stored are one of the four initial row addresses and initial column addresses of S1, S2, S3, and S4. In the initial stage of video processing, the first four original images entering the memory The assigned initial row address and initial column address are S1, S2, S3 and S4 respectively. During video processing, if there is no frame skipping, the initial row address and initial column address of the original image to be stored are S1 , S2, S3, and S4 among the four groups of initial row addresses and initial column addresses corresponding to the group of initial row addresses and initial column addresses corresponding to the original image that has been compressed and processed recently, if there is a frame skipping situation, the original image that needs to be stored The initial row address and initial column address of are the group of initial row addresses and initial column addresses allocated to the original image that needs to be skipped. The initial row address and initial column address of the reconstructed image to be stored are one of the three groups of initial row address and initial column address of S5, S6, and S7. In the initial stage of video processing, the first reconstructed image to be stored is The initial row address and initial column address are allocated as S5, the initial row address and initial column address of the reconstructed image to be stored for the second one are allocated as S6, and the initial row address and initial column address of the reconstructed image to be stored for the third are allocated In S7, during video processing, the initial row address and initial column address of the reconstructed image to be stored are the initial row address and initial column address corresponding to the first stored reconstructed image in S5, S6, and S7. The mapping relationship between the video image to be stored and the initial row address and initial column address is shown in FIG. 6 .

For the original image to be stored, the number of brightness groups SPR that can be stored in a row address in each page of the memory is equal to 1, and the brightness group k shown in Figure 2, when k is equal to 1, the page address selection of the brightness group is 0, the row address is the initial row address; when k is equal to 2, the page address of the brightness group is 1, and the row address is the initial row address; when k is equal to 3, the page address of the brightness group is 2, and the row address is Initial row address, when k is equal to 4, the page address of the brightness group is 3, and the row address is the initial row address; when k is greater than 4, the page address of the brightness group corresponds to the remainder obtained by dividing k by 4 The page address allocated by that luminance group, its row address is the sum of the quotient obtained by dividing k by 4 and the initial row address. The mapping relationship between the brightness group of the original image to be stored and the page address and row address in the memory is shown in FIG. 7 .

For the reconstructed image to be stored, the brightness group Lx_y shown in Figure 4, for L1_1, its allocated page address is 0, and its row address is the initial row address; for L1_2, its allocated page address is 1, and its row address is the initial row address; for L1_3, the allocated page address is 2, and the row address is the initial row address; for L1_4, the allocated page address is 3, and the row address is the initial row address; for L1_k, when k is greater than 4, Then the page address of the brightness group is the page address assigned by the brightness group corresponding to the remainder obtained by dividing k by 4, and its row address is the sum of the quotient obtained by dividing k by 4 and the initial row address; for L3_k, its page The address and row address are the same as the page address and row address of L1_k. For L2_k, its page address is equal to the result of adding 2 to the page address of L1_k and then modulo 4. The offset relative to the page address of L1_k is 2, and its row The address is the sum of the row address allocated by L1_k and ceil(McV/(SPR*Banknum)), that is, the initial row address+ceil(45/(1*4))=the initial row address+12; for L4_k, its page address The row address is the same as the page address and row address assigned by L2_k. For Lz_k, when z is greater than 4, its page address is the page address assigned by the kth luminance component of the row corresponding to the remainder obtained by dividing z by 4 The same, its row address is the row address assigned by the kth luminance component of the row corresponding to the remainder obtained by dividing z by 4 plus the sum of the product of the quotient obtained by dividing z by 4 and the product of 12, and the reconstruction required for storage The mapping relationship between the brightness group of the image and the page address and row address in the memory is shown in FIG. 8 .

For the original image to be stored, the luminance pixel located at the LinepositionL position from left to right in its luminance group, the column address of the allocated storage unit is the initial column address, offset h, floor(( The sum of LinepositionL-1)/4), since only one brightness group is stored in one line, the offset h is equal to 0. For the reconstructed image that needs to be stored, the pixels in the luminance group are expanded into a row as a whole, as shown in Figure 9, then the luminance pixel located at the position of ELinepositionL in order from left to right, the allocated The column address is the sum of the initial column address, offset e, floor((ELinepositionL-1)/PPU), and there are two brightness groups in a row address, Lx_k and L(x+2)_k, then for Lx_k , the value of e is 0, and for L(x+2)_k, the value of e is 64.

For the original image to be stored, the Cb chroma grouping p as shown in Figure 3, its page address is equal to the page address+1 of the brightness grouping (2*p-1) and then the result of taking the modulus of 4, relative to the brightness grouping The page address offset of (2*p-1) is 1, and its row address is equal to the row address+640 of the brightness group (2*p-1), and the Cr chrominance group p, its page address is equal to the brightness group (2* The page address of p) + 1 is the result of modulo 4, the page address offset relative to the luminance group (2*p) is 1, and its row address is equal to the row address of the luminance group (2*p) + 640; For the reconstructed image that needs to be stored, the Cb chrominance group and the Cr chrominance group located in the uth row of the yth row and the Cr chrominance group have the same page address as the page address allocated by the luminance group located in the yth row and the uth column, and their The row address is equal to the row address+320 assigned to the luminance group of the yth row and the uth column.

For the original image to be stored, the Cb chroma pixel or Cr chroma pixel located at the LinepositionC position in the Cb chroma group or Cr chroma group from left to right, the column of the mapped storage unit The address is the initial column address + floor((LinepositionC-1)/PPU); for the reconstructed image to be stored, the Cb chroma pixels or Cr chroma pixels in the Cb chroma group or Cr chroma group are arranged by row Expand, and form a row of Cb pixels or Cr pixels as a whole, as shown in Figure 11, the Cb chroma pixel or Cr chroma pixel located at the position of ELinepositionC in order from left to right, the allocated column The address is Initcol_C1+floor((ELinepositionC-1)/4), and there are four chroma groups assigned to the same row address: Cbx_y, Cb(x+2)_y, Crx_y, Cr(x+2)_y, Initcol_C1 Equal to the initial column address, for Crx_y, Initcol_C1 is equal to the initial column address +16, for Cb(x+2)_y, Initcol_C1 is equal to the initial column address +32, for Cr(x+2)_y, Initcol_C1 is equal to the initial column address +48.

Embodiment 2: Encoder 6-frame storage scheme

The memory used is W986432DH 512K×4BANKS×32BITSDRAM of Winbond Company, the data bus bit width of this memory is 32 bits, and the number of pages Banknum is equal to 4; the resolution of the video image is 720×576, and the sampling format is 4:2:0; That is, the proportional relationship between the brightness pixel point Y and the number of two color difference pixel points Cb and Cr is: Y:Cb:Cr is equal to 4:1:1, P frame coding refers to 2 frames of images at most, between two consecutive P frames , or there are at most two B frames between the P frame and the I frame; the video processor allows the original image and the reconstructed image to share the storage space, and they can overlap each other in the storage space; the processed video sequence is a field sequence.

It can be obtained from the data bus bit width of the memory: PPU is equal to 4, and the situation that PPU pixels occupy the address bus is shown in Figure 1.

The number of reference images required for P frame compression, the number of B frames stored between two consecutive P frames, or the number of B frames stored between a P frame and an I frame, and the storage requirements of the video processor for the original image and the reconstructed image can be obtained : Total space of the total frames of video images to be stored is equal to 6. For this reason, set 6 groups of initial row addresses and initial column addresses in the memory: the first group of initial row addresses and initial column addresses are 0 and 0 respectively, represented by S1; the second group of initial row addresses and initial column addresses are 108 and 0, represented by S2; the initial row address and initial column address of the third group are 216 and 0, represented by S3; the initial row address and initial column address of the fourth group are 324 and 0, represented by S4; the initial row address of the fifth group And the initial column address is 432 and 0, represented by S5; the initial row address and initial column address of the sixth group are 540 and 0, represented by S6.

The brightness component of the video image to be stored is divided into 16×16 brightness groups of 36 rows×45 columns by block, as shown in Figure 4; the Cb chrominance component is divided into 8×8 groups of 36 rows×45 columns by block The Cb chrominance group of size, the Cr chrominance component is divided into 8×8 Cr chrominance components of 36 rows×45 columns by block, as shown in FIG. 5 .

I, B, and P represent three types of original images: I frame, B frame, and P frame. i, p represent I frames, and P frames are reconstructed images generated after encoding. The video processing flow is as follows: the original images are sequentially entered into the memory at a certain time interval, and the encoding of the original images starts after three original images are stored. The original image is coded according to the structure of IBBPBBPBBP.... After the I frame and P frame are stored, they can be encoded, and the B frame cannot be encoded until its forward adjacent I frame or P frame and backward adjacent I frame or P frame are encoded and reconstructed. It encodes.

The initial row address and initial column address of the original image to be stored, in the initial stage of video processing, the initial row address and initial column address assigned to the first 6 original images are S1, S2, S3, S4, S5 and S6 in sequence ; When there is no frame skipping, if there is an encoded B frame in the memory, the initial row address and the initial column address of the original image to be stored are the corresponding group of initial row address and initial column of the B frame address, otherwise if there are i-frames or p-frames that no longer provide reference for current and subsequent encoding in the memory, the initial row address and initial column address of the original image to be stored are those corresponding to the i-frame or p-frame Group initial row address and initial column address, if there is frame skipping, the initial row address and initial column address of the original image to be stored are the initial row address and initial column address allocated by the original image that needs to be skipped, The initial row address and initial column address of the reconstructed image to be stored are the set of initial row address and initial column address corresponding to the reconstructed image without encoding and the original image before reconstruction processing, and the video image has 6 sets of initial row address and initial column address The mapping relationship of the initial column address is shown in FIG. 10 .

For the brightness group Lx_y shown in Figure 4, for L1_1 and L1_2, the assigned page address is 1, and the assigned row address is the initial row address; for L1_3 and L1_4, the assigned page address is 2, and the assigned row address The address is the initial row address; for L1_5 and L1_6, the assigned page address is 3, and the assigned row address is the initial row address; for L1_7 and L1_8, the assigned page address is 0, and the assigned row address is the initial row address Address; for L1_k, when k is greater than 8, the page address of the brightness group is the page address allocated by the brightness group corresponding to the remainder obtained by dividing k by 8, and its row address is the quotient and The sum of the initial row address, for the brightness group L3_k, its page address and row address are the same as those of the brightness group L1_k, for L2_k, its page address is equal to the page address allocated by the brightness group L1_k plus 2 and then 4 As a result of the modulo, the offset relative to the page address assigned by the brightness group L1_k is 2, and its row address is the sum of the row address assigned by the brightness group L1_k and ceil (45/8), that is, the initial row address+6; For L4_k, its page address and row address are the same as those assigned by L2_k. For Lz_k, when z is greater than 4, its page address corresponds to the kth luminance of the row corresponding to the remainder obtained by dividing z by 4 The page address assigned by the component is the same, and its row address is the sum of the row address assigned by the kth luminance component of the row corresponding to the remainder obtained by dividing z by 4 plus the product of the quotient obtained by dividing z by 4 and the product of 6 .

Expand the pixels in the brightness group into a row as a whole, as shown in FIG. 9 . Then the brightness pixel located at the ELinepositionL position in order from left to right, the allocated column address is the sum of the initial column address, offset e, floor((ELinepositionL-1)/4), and is allocated to There are 4 brightness groups of a row address: Lx_k, Lx_(k+1), L(x+2)_k and L(x+2)_(k+1), or two: Lx_k and L(x +2)_k, then for Lx_k, the value of e is 0, for L(x+2)_k, the value of e is 64, for Lx_(k+1), the value of e is 128, for L( x+2)_(k+1), the value of e is 192.

The Cb chroma group and Cr chroma group located in row y, column u have the same page address as the page address allocated by the luminance group located in row y, column u, and the initial row address and initial column address are S1 , S3, S5 video images, the Cb chroma grouping and the Cr chrominance grouping located in the yth row u column, their row address is equal to the row address+648 assigned by the luminance group located in the yth row u column; for For video images whose initial row address and initial column address are S2, S4, and S6, the Cb chrominance group and Cr chrominance group located in row y, column u, and their page addresses are equal to the luminance group located in row y, column u The allocated page address +540.

Expand the Cb chroma pixels or Cr chroma pixels in the Cb chroma group or Cr chroma group by row, and arrange the Cb pixels or Cr pixels in a row as a whole, as shown in Figure 11, then proceed from left to For the Cb chroma pixel or Cr chroma pixel located at the ELinepositionC position on the right, the assigned column address is Initcol_C1+floor((ELinepositionC-1)/4), which is assigned to the chroma group in the same row address There are 8: Cbx_y, Cbx_(y+1), Cb(x+2)_y, Cb(x+2)_(y+1), Crx_y, Crx_(y+1), Cr(x+2)_y and Cr(x+2)_(y+1), or there are 4: Cbx_y, Cb(x+2)_y, Crx_y and Cr(x+2)_y, when the initial video image where the current chroma component is located When the row address and the initial column address are S1, S3 or S5, for Cbx_y, Initcol_C1 is equal to the initial column address, for Crx_y, Initcol_C1 is equal to the initial column address + 16, and for Cb(x+2)_y, Initcol_C1 is equal to the initial column address + 32 , for Cr(x+2)_y, Initcol_C1 is equal to the initial column address +48, for Cbx_(y+1), Initcol_C1 is equal to the initial column address +64, for Crx_(y+1), Initcol_C1 is equal to the initial column address +80, For Cb(x+2)_(y+1), Initcol_C1 is equal to the initial column address +96, for Cr(x+2)_(y+1), Initcol_C1 is equal to the initial column address +112; when the current chroma component is located When the initial row address and initial column address of the video image are S2, S4 or S6, for Cbx_y, Initcol_C1 is equal to 128, for Crx_y, Initcol_C1 is equal to 144, for Cb(x+2)_y, Initcol_C1 is equal to 160, for Cr(x +2)_y, Initcol_C1 is equal to 176, for Cbx_(y+1), Initcol_C1 is equal to 192, for Crx_(y+1), Initcol_C1 is equal to 208, for Cb(x+2)_(y+1), Initcol_C1 is equal to 224 , Initcol_C1 is equal to 240 for Cr(x+2)_(y+1).

Embodiment 3: Decoder 4 frame storage scheme

The memory used is the DDR SDRAM of the MT46V8M16 model of Micron Company, and the data bus of the memory is 16 bits, and the page number Banknum is equal to 4; the resolution of the video image processed by the decoder is 720×576, and the sampling format is 4:2:0; P frame decoding refers to 2 frames of images at most, and supports B frame decoding function.

From the bit width of the data bus of the memory, it can be obtained that: PPU is equal to 2, and the situation that PPU pixels occupy the address bus is shown in FIG. 12 .

According to the number of reference frames required for decoder P frame decoding, it can be obtained that the total number of video image frames to be stored is 4. For this reason, 4 groups of initial row addresses and initial column addresses are set in the memory: the first group of initial row addresses and initial column addresses are 0 and 0 respectively, represented by S1; the second group of initial row addresses and initial column addresses are 0 and 256, represented by S2; the initial row address and initial column address of the third group are 640 and 0, represented by S3; the initial row address and initial column address of the fourth group are 640 and 256, represented by S4.

The brightness component of the video image to be stored is divided into 16×16 brightness groups of 36 rows×45 columns by block, as shown in Figure 4; the Cb chrominance component is divided into 8×8 groups of 36 rows×45 columns by block The Cb chrominance group of size, the Cr chrominance component is divided into 8×8 Cr chrominance components of 36 rows×45 columns by block, as shown in FIG. 5 .

The initial row address and the initial column address of the first 4 video images to be stored are sequentially assigned as S2, S1, S4 and S3, and the initial row address and the initial column address of the video image to be stored next are not in the memory. The decoding of the current and subsequent images is used as a reference and the set of initial row addresses and initial column addresses corresponding to the displayed images are output, as shown in FIG. 13 .

For the brightness group Lx_y shown in Figure 4, for L1_1 and L1_2, the assigned page address is 2, and the assigned row address is the initial row address; for L1_3 and L1_4, the assigned page address is 3, and the assigned row address The address is the initial row address; for L1_5 and L1_6, the assigned page address is 0, and the assigned row address is the initial row address; for L1_7 and L1_8, the assigned page address is 1, and the assigned row address is the initial row Address; for L1_k, when k is greater than 8, the page address of the brightness group is the page address allocated by the brightness group corresponding to the remainder obtained by dividing k by 8, and its row address is the quotient and The sum of the initial row address, for the brightness group L3_k, its page address and row address are the same as those of the brightness group L1_k, for L2_k, its page address is equal to the page address allocated by the brightness group L1_k plus 2 and then 4 As a result of the modulo, the offset relative to the page address allocated by L1_k is 2, and its row address is the sum of the row address allocated by the brightness group L1_k and ceil (45/8), that is, the initial row address + 6; for L4_k , its page address and row address are the same as those allocated by L2_k. For Lz_k, when z is greater than 4, its page address is the same as the kth luminance component of the row corresponding to the remainder obtained by dividing z by 4 The allocated page address is the same, and its row address is the sum of the row address allocated by the kth luminance component of the row corresponding to the remainder obtained by dividing z by 4 plus the product of 6 obtained by dividing z by 4.

Expand the pixels in the luminance group into a row as a whole, as shown in Figure 9, then the luminance pixel located at the ELinepositionL position in the order from left to right, the assigned column address is the initial column address, offset The sum of displacement e, floor((ELinepositionL-1)/2), there are 4 brightness groups assigned to a row address: Lx_k, Lx_(k+1), L(x+2)_k and L( x+2)_(k+1), or there are two: Lx_k and L(x+2)_k, then for Lx_k, the value of e is 0, and for L(x+2)_k, the value of e is 128, for Lx_(k+1), the value of e is 256, and for L(x+2)_(k+1), the value of e is 384.

The Cb chroma group and Cr chroma group located in row y, column u, their page address is equal to the page address allocated by the luminance group in row y, column u, and the row address is equal to the luminance group in row y, column u The allocated row address +640.

Expand the Cb chroma pixels or Cr chroma pixels in the Cb chroma group or Cr chroma group by row, and arrange the Cb pixels or Cr pixels in a row as a whole, as shown in Figure 11, then proceed from left to For the Cb chroma pixel or Cr chroma pixel located at the ELinepositionC position on the right, the assigned column address is Initcol_C1+floor((ELinepositionC-1)/2), which is assigned to the chroma group in the same row address There are 8: Cbx_y, Cbx_(y+1), Cb(x+2)_y, Cb(x+2)_(y+1), Crx_y, Crx_(y+1), Cr(x+2)_y and Cr(x+2)_(y+1), or there are 4: Cbx_y, Cb(x+2)_y, Crx_y and Cr(x+2)_y, for Cbx_y, Initcol_C1 is equal to the initial column address, for Crx_y , Initcol_C1 is equal to the initial column address +32, for Cb(x+2)_y, Initcol_C1 is equal to the initial column address +64, for Cr(x+2)_y, Initcol_C1 is equal to the initial column address +96, for Cbx_(y+1) , Initcol_C1 is equal to the initial column address +128, for Crx_(y+1), Initcol_C1 is equal to the initial column address +160, for Cb(x+2)_(y+1), Initcol_C1 is equal to the initial column address +192, for Cr( x+2)_(y+1), Initcol_C1 is equal to initial column address+224.

Embodiment 4: High-definition encoder 6-frame storage scheme

The memory used is DDR2SDRAM of the MT47H64M16 type of Micron Company. The data bus bit width of this memory is 16 bits, and the page number Banknum is equal to 8; the resolution of the video image is 1920×1088, and the sampling format is 4:2:0; P frame Coding refers to a maximum of 2 frames of images, between two consecutive P frames, or a maximum of two B frames between a P frame and an I frame; the video processor allows the original image and the reconstructed image to share storage space, and they can interact with each other in the storage space Overlay; the processed video sequence is a sequence of frames.

From the bit width of the data bus of the memory, it can be obtained that: PPU is equal to 2, and the situation that PPU pixels occupy the address bus is shown in FIG. 12 .

The number of reference images required for P frame compression, the number of B frames stored between two consecutive P frames, or the number of B frames stored between a P frame and an I frame, and the storage requirements of the video processor for the original image and the reconstructed image can be obtained : Total space of the total frames of video images to be stored is equal to 6. For this reason, 6 groups of initial row addresses and initial column addresses are set in the memory: the first group of initial row addresses and initial column addresses are 0 and 0 respectively, represented by S1; the second group of initial row addresses and initial column addresses are 144 and 0, represented by S2; the initial row address and initial column address of the third group are 288 and 0, represented by S3; the initial row address and initial column address of the fourth group are 432 and 0, represented by S4; the initial row address of the fifth group And the initial column address is 576 and 0, represented by S5; the initial row address and initial column address of the sixth group are 720 and 0, represented by S6.

The luminance component of the video image to be stored is divided into 16×16 luminance groups of 68 rows×120 columns by block, as shown in Figure 14; the Cb chrominance component is divided into 8×8 groups of 68 rows×120 columns by block The Cb chrominance group of size, the Cr chrominance component is divided into 8×8 Cr chrominance components of 68 rows×120 columns by block, as shown in Figure 15 .

The initial row address and initial column address of the original image to be stored, in the initial stage of video processing, the initial row address and initial column address assigned to the first 6 original images are S1, S2, S3, S4, S5 and S6 in sequence ; In the case of no frame skipping, if there is an encoded B frame in the memory, the initial row address and initial column address of the original image to be stored are the corresponding group of initial row address and initial column address of the B frame , otherwise if there is an i-frame or p-frame in the memory that no longer provides reference for the current and subsequent encoding, the initial row address and initial column address of the original image to be stored are the group corresponding to the i-frame or p-frame Initial row address and initial column address, if there is frame skipping, the initial row address and initial column address of the original image to be stored are the initial row address and initial column address allocated by the original image that needs to be skipped, so The initial row address and initial column address of the reconstructed image to be stored are the set of initial row address and initial column address corresponding to the reconstructed image without encoding and the original image before reconstruction processing, and the video image has 6 sets of initial row address and initial column address The mapping relationship of column addresses is shown in Figure 10.

For the brightness group Lx_y shown in Figure 14, for L1_1, L1_2, L1_3 and L1_4, the page address allocated to it is 0, and the allocated row address is the initial row address; for L1_5, L1_6, L1_7 and L1_8, the allocated The page address is 1, and the assigned row address is the initial row address; for L1_9, L1_10, L1_11, and L1_12, the assigned page address is 2, and the assigned row address is the initial row address; for L1_13, L1_14, L1_15, and L1_16, The allocated page address is 3, and the allocated row address is the initial row address; for L1_17, L1_18, L1_19 and L1_20, the allocated page address is 4, and the allocated row address is the initial row address; for L1_21, L1_22, For L1_23 and L1_24, the allocated page address is 5, and the allocated row address is the initial row address; for L1_25, L1_26, L1_27 and L1_28, the allocated page address is 6, and the allocated row address is the initial row address; For L1_29, L1_30, L1_31, and L1_32, the page address assigned to them is 7, and the assigned row address is the initial row address; for L1_k, when k is greater than 32, the page address of the brightness group is the remainder obtained by dividing k by 32 The page address allocated by the corresponding brightness group, its row address is the sum of the quotient obtained by dividing k by 32 and the initial row address, for the brightness group L5_k, its page address and row address are the same as the page address and row address of the brightness group L1_k The address is the same. For L2_k, its page address is equal to the result of adding 1 to the page address assigned by the brightness group L1_k and then modulo 4. The offset relative to the page address of L1_k is 1, and its row address is assigned by the brightness group L1_k The sum of the row address and ceil(120/32), that is, the initial row address + 4; for L3_k, its page address is equal to the result of adding 1 to the page address assigned by the brightness group L2_k and then modulo 4, relative to the page of L2_k The address offset is 1, and its row address is the row address assigned by the brightness group L2_k + 4; for L4_k, its page address is equal to the result of adding 1 to the page address assigned by the brightness group L3_k and then modulo 4, relative to L3_k The offset of the page address is 1, and its row address is the row address assigned by brightness group L3_k+4; for L6_k, its page address and row address are the same as those assigned by L2_k; for L7_k, its The page address and row address are the same as those assigned by L3_k; for L8_k, its page address and row address are the same as those assigned by L4_k; for Lz_k, when z is greater than 8, its page address It is the same as the page address assigned to the k-th luminance component of the row corresponding to the remainder obtained by dividing z by 8, and its row address is the row assigned to the k-th luminance component of the row corresponding to the remainder obtained by dividing z by 8 The address is added to the sum of the quotient obtained by dividing z by 8 and the product of 4.

Expand the pixels in the brightness group into a row as a whole, as shown in FIG. 9 . Then the brightness pixel located at the ELinepositionL position in order from left to right, the allocated column address is the sum of the initial column address, offset e, floor((ELinepositionL-1)/2), and is allocated to There are 8 brightness groups of a row address: Lx_k, Lx_(k+1), Lx_(k+2), Lx_(k+3), L(x+4)_k, L(x+4)_(k +1), L(x+4)_(k+2) and L(x+4)_(k+3), or there are 4: Lx_k, Lx_(k+1), Lx_(k+2) and Lx_(k+3), then for Lx_k, the value of e is 0, for Lx_(k+1), the value of e is 128, for Lx_(k+2), the value of e is 256, for Lx_(k+3), the value of e is 384, for L(x+1)_k, the value of e is 512, and for L(x+1)_(k+1), the value of e is 640 , for L(x+1)_(k+2), the value of e is 768, and for L(x+1)_(k+3), the value of e is 896.

The Cb chroma group and Cr chroma group located in row y, column u have the same page address as the page address allocated by the luminance group located in row y, column u, and the initial row address and initial column address are S1 , S3, S5 video images, the Cb chrominance grouping and the Cr chrominance grouping located in the yth row u column, their page address is equal to the page address+864 assigned by the luminance group located in the yth row u column; for For video images whose initial row address and initial column address are S2, S4, and S6, the Cb chrominance group and Cr chrominance group located in row y, column u, and their page addresses are equal to the luminance group located in row y, column u The allocated page address +720.

Expand the Cb chroma pixels or Cr chroma pixels in the Cb chroma group or Cr chroma group by row, and arrange a row of Cb pixels or Cr pixels as a whole, as shown in FIG. 11 . Then the Cb chroma pixel or Cr chroma pixel located at the position of ELinepositionC in order from left to right, the allocated column address is Initcol_C1+floor((ELinepositionC-1)/2), which is allocated to the same row address There are 16 chroma groupings: Cbx_y, Cbx_(y+1), Cbx_(y+2), Cbx_(y+3), Cb(x+4)_y, Cb(x+4)_(y+ 1), Cb(x+4)_(y+2), Cb(x+4)_(y+3), Crx_y, Crx_(y+1), Crx_(y+2), Crx_(y+3 ), Cr(x+4)_y, Cr(x+4)_(y+1), Cr(x+4)_(y+2), and Cr(x+4)_(y+3), or There are 8: Cbx_y, Cbx_(y+1), Cbx_(y+2), Cbx_(y+3), Crx_y, Crx_(y+1), Crx_(y+2) and Crx_(y+3), When the initial row address and initial column address of the video image where the current chrominance component is located are S1, S3 or S5, for Cbx_y, Initcol_C1 is equal to the initial column address, for Crx_y, Initcol_C1 is equal to the initial column address + 32, for Cbx_(y+ 1), Initcol_C1 is equal to the initial column address +64, for Crx_(y+1), Initcol_C1 is equal to the initial column address +96, for Cbx_(y+2), Initcol_C1 is equal to the initial column address +128, for Crx_(y+2) , Initcol_C1 is equal to the initial column address +160, for Cbx_(y+3), Initcol_C1 is equal to the initial column address +192, for Crx_(y+3), Initcol_C1 is equal to the initial column address +224, for Cb(x+4)_y, Initcol_C1 is equal to the initial column address +256, for Cr(x+4)_y, Initcol_C1 is equal to the initial column address +288, for Cb(x+4)_(y+1), Initcol_C1 is equal to the initial column address +320, for Cr( x+4)_(y+1), Initcol_C1 is equal to the initial column address +352, for Cb(x+4)_(y+2), Initcol_C1 is equal to the initial column address +384, for Cr(x+4)_( y+2), Initcol_C1 is equal to the initial column address +416, for Cb(x+4)_(y+3), Initcol_C1 is equal to the initial column address +448, for Cr(x+4)_(y+3), Initcol_C1 Equal to the initial column address + 480; when the initial row address and initial column address of the video image where the current chrominance component is located are S2, S4 or S6, for Cbx_y, Initcol_C1 is equal to 512, for Crx_y, Initcol_C1 is equal to 544, for Cbx_(y +1), Initcol_C1 is equal to 576, for Crx_(y+1), Initcol_C1 is equal to 608, for Cbx_(y+2), Initcol_C1 is equal to 640, for Crx_(y+2), Initcol_C1 is equal to 672, for Cbx_(y+3 ), Initcol_C1 is equal to 704, for Crx_(y+3), Initcol_C1 is equal to 736, for Cb(x+4)_y, Initcol_C1 is equal to 768, for Cr(x+4)_y, Initcol_C1 is equal to 800, for Cb(x+4 )_(y+1), Initcol_C1 is equal to 832, for Cr(x+4)_(y+1), Initcol_C1 is equal to 864, for Cb(x+4)_(y+2), Initcol_C1 is equal to 896, for Cr (x+4)_(y+2), Initcol_C1 is equal to 928, for Cb(x+4)_(y+3), Initcol_C1 is equal to 960, for Cr(x+4)_(y+3), Initcol_C1 is equal to 992.

Claims (8)

1, the mapping method of a kind of video processor video data and memory storage space is characterized in that, comprises following six steps:

The pixel number PPU that a, each address location of setting memory are deposited; Set Totalspace group initial row address and initial column address; Luminance component, Cb chromatic component and the Cr chromatic component of the video image of required storage are divided according to row and a kind of dividing mode of piece in dividing is divided into corresponding brightness grouping, the grouping of Cb colourity and the grouping of Cr colourity;

B, in Totalspace group initial row address of setting and initial column address, select one group of initial row address and initial column address as initial row address and initial column address when the video image of the required storage that advance into memory;

C, the page address and the row address that distribute brightness to divide into groups;

D, the column address of distributing each the luminance pixel point in the brightness grouping;

E, according to the page address and the row address of brightness grouping, obtain page address and row address that grouping of corresponding C b colourity and Cr colourity are divided into groups;

F, the column address of distributing chroma pixel point in grouping of Cb colourity and the grouping of Cr colourity.

2, the mapping method of video processor video data as claimed in claim 1 and memory storage space, it is characterized in that the pixel number PPU that described address location is deposited is determined that by the memory data bus bit wide PPU pixel in each address location takies the data/address bus bit wide of address location in order; Described Totalspace group initial row address is corresponding with the totalframes of the video image of required storage with the initial column address, the corresponding group address space in each group initial row address and initial column address;

3, the mapping method of video processor video data as claimed in claim 1 and memory storage space is characterized in that described row is divided and piece is divided into:

Row is divided: the luminance component of the video image of required storage is divided into the capable brightness grouping of LiH by row, the Cb chromatic component of the video image of required storage is divided into the capable Cb colourity grouping of LiH/2 by row, the Cr chromatic component of the video image of required storage is divided into the capable Cr colourity grouping of LiH/2 by row;

Piece is divided: with the luminance component of the video image of required storage be divided into McH capable * the brightness grouping of McV row 16 * 16 size, with the Cb chromatic component of the video image of required storage be divided into McH capable * the Cb colourity grouping of McV row 8 * 8 size, with the Cr chromatic component of the video image of required storage be divided into McH capable * the Cr colourity grouping of McV row 8 * 8 size.

4, the mapping method of video processor video data as claimed in claim 1 and memory storage space, it is characterized in that described video image when the required storage that advances into memory is a kind of video image in original image and the reconstructed image at least, described in Totalspace group initial row address of setting and initial column address, select one group of initial row address and initial column address to be as the initial row address of the video image of working as the required storage that advances into memory and the method for initial column address:

For the video decode processor: if there be as yet not initial row address and the initial column address of shining upon with video image in the memory, then the initial row address of the video image of required storage and initial column address are one of those group initial row addresses of not shining upon with video image as yet and initial column address, otherwise the initial row address of the video image of required storage and initial column address are not do reference for current and successive image decoding and exported in the memory to show the image that finishes pairing that group initial row address and initial column address;

For the video coding processor: by one of following 2 decision:

(1) the initial row address of the original image of required storage and initial column address are one of OPTnum group initial row address and initial column address, in the starting stage of Video processing, the initial address row address of the original image of required storage and initial column address are a certain group of initial row address and the initial column address of not shining upon with video image as yet in OPTnum group initial row address and the initial column address, in video processing procedure, the if there is no situation of frame-skipping, the initial row address of the original image of required storage and initial column address are original image pairing that group initial row address and initial column address that nearest encoding process finishes in OPTnum group initial row address and the initial column address, if there is the situation of frame-skipping, the initial row address of the original image of required storage and initial column address are that group initial row address and initial column address for realizing that the frame-skipping function obtains in OPTnum group initial row address and the initial column address, the initial row address of the reconstructed image of required storage and initial column address are one of RPTnum group initial row address and initial column address, in the starting stage of Video processing, the initial row address of the reconstructed image of required storage and initial column address are a certain group of initial row address and the initial column address of not shining upon with video image as yet in RPTnum group initial row address and the initial column address, in video processing procedure, the initial row address of the reconstructed image of required storage and initial column address are pairing that group initial row address and initial column address of the reconstructed image of storage at first in RPTnum group initial row address and the initial column address;

(2) the initial row address of the original image of required storage and initial column address, in the starting stage of Video processing, be a certain group of initial row address and the initial column address of not shining upon with video image as yet in Totalspace group initial row address and the initial column address, in video processing procedure, when not having the situation of frame-skipping, if the encoded B frame that finishes is arranged in the memory, the initial row address of the original image of required storage and initial column address are pairing that group initial row address and initial column address of this B frame, i frame or p frame that reference no longer is provided for current and next code are arranged in the memory else if, then the initial row address of the original image of required storage and initial column address are this i frame or p frame pairing that group initial row address and initial column address, if there is the situation of frame-skipping, the initial row address of the original image of required storage and initial column address are to be that group initial row address and the initial column address of realizing that the frame-skipping function obtains, and the initial row address of the reconstructed image of required storage and initial column address are this reconstructed image un-encoded, original image before the reconstruction process pairing that group initial row address and initial column address.

5, the mapping method of video processor video data as claimed in claim 1 and memory storage space is characterized in that page address and row address that described distribution brightness is divided into groups, and its method is:

When the dividing mode of dividing according to row when luminance component was divided, from top to bottom k brightness grouping in luminance component divided into groups if k is the 1st brightness, and then for it distributes any one page address, its row address is exactly the initial row address; K is n*SPR+1 brightness grouping else if, be to be different from a divide into groups page address of the page address that distributed of front n*SPR brightness of this brightness grouping then for the page address of its distribution, its row address is the initial row address, else if k greater than m*SPR+1 smaller or equal to (m+1) * SPR, then the page address for its distribution is identical with the page address that m*SPR+1 brightness grouping distributed, its row address equals the initial row address, k is greater than SPR*Banknum else if, then the page address of this brightness grouping is the page address that is distributed except that pairing that brightness grouping of the remainder of k gained with (SPR*Banknum), its row address be the merchant that removes the k gained with (SPR*Banknum) with the initial row address with, wherein Banknum is the branch number of pages of memory, n is more than or equal to 1 integer less than Banknum, SPR is the integer greater than 0, and m is more than or equal to 0 integer less than Banknum;

When luminance component was divided according to the dividing mode of piece division, if this brightness grouping is k brightness grouping of the 1st row, when k was the 1st brightness grouping, for it distributes any one page address, its row address was exactly the initial row address; When k is n*SPR+1 brightness grouping, be to be different from a divide into groups page address of the page address that distributed of front n*SPR brightness of this brightness grouping then for the page address of its distribution, its row address is the initial row address, when k greater than m*SPR+1 during smaller or equal to (m+1) * SPR, then identical for the divide into groups page address that distributed of m*SPR+1 brightness of the page address of its distribution and the 1st row, its row address is the initial row address, as k during greater than SPR*Banknum, then the page address of this brightness grouping is the page address that is distributed except that pairing that brightness grouping of the remainder of k gained with (SPR*Banknum), its row address be the merchant that removes the k gained with (SPR*Banknum) with the initial row address with, wherein Banknum is the branch number of pages of memory, n is more than or equal to 1 integer less than Banknum, SPR is the integer greater than 0, m is more than or equal to 0 integer less than Banknum, for capable k the brightness grouping of z, when z equals Sn, its page address is identical with the page address and the row address of k brightness grouping of row address and the 1st row, when z greater than 1 during less than Sn, the page address that capable k the brightness grouping of its page address and z-1 is distributed has the side-play amount of deltab, deltab is more than or equal to 1 integer smaller or equal to Banknum/ (Sn-1), its row address be the row address that distributed of capable k brightness grouping of z-1 with ceil (McV/ (SPR*Banknum)) with, when z greater than Sn during smaller or equal to 2* (Sn-1), its page address is identical with page address and the row address that capable k the brightness grouping of z-Sn+1 is distributed with row address, as z during greater than 2* (Sn-1), its page address is identical with k the page address that luminance component distributed of the pairing row of remainder that removes the z gained with (2*Sn-2), its row address for k the row address that luminance component distributed that removes the pairing row of remainder of z gained with (2*Sn-2) add usefulness (2*Sn-2) remove the merchant of z gained and ceil (McV/ (SPR*Banknum)) long-pending gained with, Sn is greater than 2 integers smaller or equal to (1+Banknum/2).

6, the mapping method of video processor video data as claimed in claim 1 and memory storage space is characterized in that the column address of each luminance pixel point in the described distribution brightness grouping, and its method is:

When luminance component is divided according to the dividing mode of row division, then be positioned at the luminance pixel point of LinepositionL position in the brightness grouping by order from left to right, the column address of the memory cell of being distributed is the initial column address, side-play amount h, floor ((LinepositionL-1)/PPU) three sum, h is the integer more than or equal to 0, is assigned to the different brightness groupings in the same row address, has different side-play amount h;

When luminance component is divided according to the dividing mode of piece division, luminance pixel in the brightness grouping is pressed row to launch, the integral body pixel that is in line, then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/PPU) three sum, e is the integer more than or equal to 0, is assigned to brightness groupings different in the same row address, has different side-play amount e.

7, the mapping method of video processor video data as claimed in claim 1 and memory storage space, it is characterized in that described page address and row address according to the brightness grouping, obtain the page address and the row address of grouping of corresponding C b colourity and the grouping of Cr colourity, its method is:

When the dividing mode of dividing according to row when Cb chromatic component and Cr chromatic component is divided, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p-1 the brightness in luminance component of p Cb colourity grouping divides into groups to be distributed in the Cb chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p-1 the brightness in luminance component of p Cb colourity grouping divides into groups to be distributed in the Cb chromatic component, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, or: the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p-1 the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p-1 the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p the brightness grouping in luminance component of p Cb colourity grouping distributed in the Cb chromatic component has the side-play amount of beta between row address that from top to bottom p Cb colourity is divided into groups in the Cb chromatic component and from top to bottom 2*p brightness divides into groups to be distributed in luminance component the row address;

When the dividing mode of dividing according to piece when Cb chromatic component and Cr chromatic component is divided, be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u row of y, their page address is identical with the page address that the brightness grouping that is positioned at the capable u row of y is distributed, and the row address that their row address divides into groups to be distributed with respect to the brightness of the capable u row of y has the side-play amount of gama.

8, the mapping method of a kind of video processor video data as claimed in claim 1 and memory storage space is characterized in that described distribution Cb colourity is divided into groups and the column address of the interior chroma pixel point of Cr colourity grouping, and its method is:

When the dividing mode of dividing according to row when Cb chromatic component and Cr chromatic component is divided, then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of LinepositionC position in grouping of Cb colourity or the grouping of Cr colourity by order from left to right, the column address of the memory cell of being shone upon is Initcol_C1+floor ((LinepositionC-1)/PPU);

When the dividing mode of dividing according to piece when Cb chromatic component and Cr chromatic component is divided, Cb chroma pixel point in grouping of Cb colourity or the grouping of Cr colourity or Cr chroma pixel are pressed the row expansion, integral body be in line Cb pixel or Cr pixel, then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of ELinepositionC position according to order from left to right, the column address of being distributed is Initcol_C1+floor ((ELinepositionC-1)/PPU), be assigned to Cb colourity groupings different in the same row address and the grouping of Cr colourity, have different Initcol_C1.

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