CN101304015B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device with improved moisture resistance and a manufacturing method thereof, and provides a manufacturing method of a semiconductor device capable of simplifying the manufacturing process and improving productivity. The present invention provides a highly reliable semiconductor device such as a CSP structure and a method of manufacturing the same by covering the side surface of a semiconductor chip or the like with a thick protective layer to prevent intrusion of moisture or the like. To provide such a highly productive method of manufacturing a semiconductor device, the semiconductor device can be divided without going through a dicing process by etching the support from the back side of the support attached to the semiconductor chip.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a CSP (Chip Size Package: Chip Size Package) type semiconductor device using a support and a manufacturing method thereof. the

Background technique

In recent years, CSP has been widely concerned as a new packaging technology. The CSP refers to a small package having approximately the same size and outer shape as that of a semiconductor chip. A BGA (Ball Grid Array: ball grid array) type semiconductor device is known as one type of CSP. In a BGA type semiconductor device, a plurality of ball-shaped terminals made of a metal material such as solder are arranged on one surface of a package. the

In order to increase the mounting density, thinning of semiconductor chips is required, and in order to meet this requirement, it is necessary to reduce the thickness of the semiconductor substrate. However, if the semiconductor substrate becomes thinner, it will become warped or damaged due to a reduction in strength during the manufacturing process, making it impossible to transport. Therefore, a support such as a glass substrate or a protective tape is bonded to one surface of the semiconductor substrate, and the surface to which the support is not bonded is ground to reduce the thickness of the semiconductor substrate. the

29 is a schematic cross-sectional view showing a conventional BGA-type semiconductor device provided with a carrier. A semiconductor integrated circuit 101 composed of elements such as a CCD (Charge Coupled Device) image sensor or a CMOS image sensor is formed on the surface of a semiconductor substrate 100 made of silicon (Si), and is integrated with the semiconductor through an insulating film 103. The circuit 101 is electrically connected to the pad electrode 102 . The pad electrode 102 is covered with a passivation film 104 made of a silicon nitride film or the like. the

A support body 105 such as a glass substrate is bonded to the surface of the semiconductor substrate 100 via an adhesive layer 106 made of epoxy resin or the like. In order to firmly maintain the thinned semiconductor substrate 100 in the manufacturing process, and to prevent warping and damage of the support body 105 itself, the support body 105 is formed thicker. For example, when the thickness of the thinned semiconductor substrate 100 is about 100 μm, the support The thickness of the body 105 is about 400 μm. the

An insulating film 107 made of a silicon oxide film, a silicon nitride film, or the like is formed on the side surface and the back surface of the semiconductor substrate 100 . A wiring layer 108 electrically connected to the pad electrode 102 is formed on the insulating film 107 along the side surface and the back surface of the semiconductor substrate 100 . A protective layer 109 made of solder resist or the like is formed to cover the insulating film 107 and the wiring layer 108. An opening is formed in a predetermined region of the protective layer 109, and a spherical conductive terminal 110 electrically connected to the wiring layer 108 through the opening is formed. the

Such a semiconductor device is manufactured through a process of dicing the support body 105, the protective layer 109, and the like with a dicing blade along a predetermined dicing line DL that is the boundary of each semiconductor device (so-called dicing process). the

Such techniques are described in, for example, the following patent documents. the

Patent Document 1: Japanese Patent Laid-Open No. 2006-93367

Although the above-mentioned semiconductor device has a protective layer 109 covering the wiring layer 108 connected to the pad electrode 102, the moisture resistance of the contact portion between the protective layer 109 and the adhesive layer 106 made of hygroscopic resin and the support body or the like is weak. , there is a problem in reliability that the support body 105 may peel off from the semiconductor element. the

As precision processing progresses, the number of chips per wafer increases, and the number of dicing lines D1 for one wafer also increases. Therefore, the conventional manufacturing method of dividing the above-mentioned dicing lines DL one by one has a problem that the dicing process takes a long time. In particular, when a highly rigid substrate such as a glass substrate is used as the support body 105, it is difficult to cut the support body 105, which is one of the reasons why the cutting process takes a long time. In addition, electronic devices are required to be more highly functional and thinner. the

Contents of the invention

The object of the present invention is to provide a semiconductor device with high reliability, and its further object is to provide a method of manufacturing a semiconductor device with simplified manufacturing steps and good productivity. Purpose. the

The present invention was developed in view of the above-mentioned problems, and its main features are as follows. That is, the semiconductor device of the present invention includes: a metal pad connected to a circuit element in a semiconductor chip and formed near the side surface of the semiconductor chip; an insulating film formed on the side surface and the back surface of the semiconductor chip; The back surface of the metal pad is connected to the metal wiring extending from the side surface of the semiconductor chip to the back surface in contact with the insulating film, and the protection formed by filling the side surface and the back surface of the semiconductor chip layer, and a conductive terminal electrically connected to the metal wiring through an opening formed in the protective layer. the

The protection layer is composed of a first protection layer and a second protection layer. the

There is a support body bonded so as to cover the surface portion of the semiconductor chip including the metal pad. the

Another semiconductor device is laminated on the semiconductor device so that the protective layer of the upper semiconductor device is in contact with the lower semiconductor device. the

And the semiconductor device of the present invention includes: a metal pad connected to a circuit element in a semiconductor chip and formed near the side surface of the semiconductor chip; an insulating film formed on the side surface and the back surface of the semiconductor chip; The metal wiring connected to the back surface of the metal pad and extending from the side surface to the back surface of the semiconductor chip in contact with the insulating film, the protective layer formed on the side surface and the back surface of the semiconductor chip, and the A conductive terminal connected to the metal wiring in an opening of the protective layer, and a conductive film formed on the protective layer and filling a side surface of the semiconductor chip. the

The semiconductor device has a support adhered so as to cover the surface portion of the semiconductor chip including the metal pad. the

The method for manufacturing a semiconductor device according to the present invention includes: preparing a semiconductor substrate on which a metal pad is formed via a first insulating film, and bonding the surface side of the semiconductor substrate including the metal pad to the surface of a support. A step of bonding; a step of removing a part from the back side of the semiconductor substrate to expose the first insulating film; a step of forming a second insulating film on the entire back surface of the semiconductor substrate; removing the first and second insulating films. A step of exposing the metal pad by exposing a part of the insulating film; a step of forming a metal wiring connected to the back surface of the metal pad and extending to the back surface of the semiconductor substrate; removing a part of the semiconductor substrate and The process of forming a groove reaching halfway in the thickness direction of the support on the surface of the support; the process of filling the entire back surface of the semiconductor substrate including the groove to form a protective layer; forming a protective layer through the protective layer. The process of electrically connecting the conductive terminal to the metal wiring through the opening. the

The step of forming the protective layer includes a step of forming a second protective layer on the first protective layer after forming the first protective layer. the

The method for manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor substrate on which a metal pad is formed via a first insulating film, and bonding the surface side of the semiconductor substrate including the metal pad to the surface of a support. ; a process of removing a part of the semiconductor substrate from the back side to expose the first insulating film; a process of forming a second insulating film on the entire back surface of the semiconductor substrate; removing the first and second insulating films exposing the metal pad by removing a part of the film; forming a metal wiring connected to the back surface of the metal pad and extending to the back surface of the semiconductor substrate; removing a part of the semiconductor substrate and The process of forming a groove on the surface of the support body reaching halfway in the thickness direction of the support body; the process of forming a first protective layer on the back side of the semiconductor substrate including the groove; a step of forming a conductive terminal electrically connected to the metal wiring through the opening; and a step of forming a second protection layer on the first protection layer. the

In the step of forming the protective layer or the first protective layer, an injection molding resin is applied. the

In the step of forming the second protective layer, a conductive material is coated. the

It has the process of thinning the said support body. And it has the process of removing the said support body. the

The manufacturing method of the semiconductor device of the present invention includes: the step of bonding the surface side of the wafer-like semiconductor substrate to the surface of the support; the step of removing a part of the semiconductor substrate; A step of forming a groove in the middle of the thickness direction of the support; a step of etching the back surface of the support until the groove is exposed from the back surface of the support, and obtaining individual semiconductor devices by dividing the support. the

The method for manufacturing a semiconductor device according to the present invention includes: a step of attaching a tape to the surface side of a wafer-shaped semiconductor substrate and attaching the surface of the support to the tape; a step of removing a part of the semiconductor substrate; A step of forming a groove on the surface of the tape on the semiconductor substrate side that reaches halfway in the thickness direction of the tape; layer; a step of etching the back of the support until the tape is exposed from the back side of the support; supplying a dissolving agent to the exposed tape to peel the tape from the semiconductor substrate, and passing A step of separating the semiconductor substrate and the support to obtain individual semiconductor devices. the

The manufacturing method of the semiconductor device of the present invention includes: the step of bonding the surface side of the wafer-shaped semiconductor substrate to the surface of the support; the step of removing a part of the semiconductor substrate; The process of the groove in the middle of the body thickness direction; the process of etching at least the position corresponding to the groove on the back surface of the support body to make the thickness of the support body corresponding to the groove thin; by applying a load to the support body And a step of dividing the support body along the grooves to obtain individual semiconductor devices. the

According to the present invention, since the protective layer is formed to bury the entire semiconductor chip, it is possible to provide a semiconductor device having improved moisture resistance compared with conventional structures. According to the present invention, since individualized semiconductor devices can be obtained in one process without dividing the dicing lines one by one, the time required for the dicing process can be greatly shortened, and productivity can be improved. Since there is a step of thinning the support or a step of removing the support, the thickness of the semiconductor device can be reduced. the

Description of drawings

1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

3A and B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

10 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention;

12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention;

13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention;

14 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention;

15 is a cross-sectional view illustrating a manufacturing method of a semiconductor device according to a seventh embodiment of the present invention;

16 is a cross-sectional view illustrating a manufacturing method of a semiconductor device according to a seventh embodiment of the present invention;

17 is a cross-sectional view illustrating a manufacturing method of a semiconductor device according to a seventh embodiment of the present invention;

18 is a cross-sectional view illustrating a manufacturing method of a semiconductor device according to a seventh embodiment of the present invention;

19 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention;

20 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a ninth embodiment of the present invention;

21 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a ninth embodiment of the present invention;

22 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a ninth embodiment of the present invention;

23 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a tenth embodiment of the present invention;

24 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a tenth embodiment of the present invention;

25 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention;

26 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an eleventh embodiment of the present invention;

27 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention;

28 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an eleventh embodiment of the present invention;

Fig. 29 is a cross-sectional view illustrating a conventional semiconductor device. the

Symbol Description

1. 101 Semiconductor integrated circuits

2. 100 semiconductor substrates

2a semiconductor chip

3, 103 insulation film 4, 38, 68, 102 pad electrodes

5. 104 passivation film

6, 71, 52, 106 adhesive layer

7. 105 support body

8, 12, 18, 32, 40, 42, 54, 61 openings

9, 107 insulation film

10, 108 wiring layer

11, 53 slots

13, 13a, 21, 31, 41, 55, 109 protective layer, first protective layer

14, 15, 110 conductive terminals

20, 30, 35, 37, 43, 45, 56, 60, 67, 70, 75 semiconductor devices

DL cutting line

35, 65 The first semiconductor device

36, 66 The second semiconductor device

46 conductive paste

16, 47 resist layer

50 bands

72, 51 cavities

17 Protective parts

A first embodiment of the present invention will be described below with reference to the drawings. 1 to 8 are cross-sectional views or plan views respectively shown in the order of manufacturing steps. The manufacturing process described below is performed using a wafer-shaped semiconductor substrate. A plurality of semiconductor devices are formed in a matrix with predetermined dicing lines DL as boundaries. For convenience, a process of forming one of the semiconductor devices will be described. the

Detailed ways

First, as shown in FIG. 1, a semiconductor integrated circuit 1 (such as a light-receiving element or light-emitting element such as a CCD sensor, a CMOS sensor, and an illuminance sensor, a drive circuit or a logic circuit composed of a semiconductor element such as a laminated transistor, etc., is prepared to be formed on its surface. The wafer-shaped semiconductor substrate 2 made of silicon (Si) or the like, such as wirings connected thereto. The semiconductor substrate 2 has a thickness of, for example, about 300 μm to 700 μm. On the surface of the semiconductor substrate 2, an insulating film 3 (for example, a silicon oxide film formed by a thermal oxidation method or a CVD method) is formed to have a film thickness of, for example, 2 μm. the

Then, a metal layer such as aluminum (Al), aluminum alloy, or copper (Cu) is formed by sputtering, electroplating, or other film-forming methods, and the metal layer is etched using a resist layer (not shown) as a mask. The pad electrode 4 is formed on the insulating film 3 with a film thickness of, for example, 1 μm. The pad electrode 4 is an electrode for external connection that electrically connects the semiconductor integrated circuit 1 and its peripheral elements via wiring not shown. A power supply voltage, a ground voltage, or various signals are supplied to the semiconductor integrated circuit 1 , the semiconductor substrate 2 , and the like via the pad electrode 4 from the conductive terminal 14 described later. The arrangement position of the pad electrode 4 is not limited, and may be arranged on the semiconductor integrated circuit 1 . the

Next, a passivation film 5 (such as a silicon nitride film formed by CVD) is formed on the surface of the semiconductor substrate 2 to cover part or all of the pad electrode 4 . In FIG. 1 , passivation film 5 is formed to cover part of pad electrode 4 . the

Then, on the surface of the semiconductor substrate 2 including the pad electrode 4, it is bonded via an adhesive layer 6 made of epoxy resin, polyimide (such as photosensitive polyimide), resist, acrylic, or the like. Wafer-shaped support body 7 . In this embodiment, the surface of the support body 7 on the semiconductor substrate 2 side is defined as the front surface, and the other surface is defined as the rear surface. When the semiconductor integrated circuit 1 includes a light-receiving element and a light-emitting element, since the adhesive layer 6 becomes a passage of light emitted from the semiconductor integrated circuit 1 or light incident on the semiconductor integrated circuit 1, it is preferable to be transparent. Constructed of materials with good properties that transmit light. the

The support body 7 may be, for example, a film-shaped protective tape, may be a rigid substrate such as glass, quartz, ceramics, or metal, or may be made of resin. The support body 7 supports the semiconductor substrate 2 and also has the function of protecting the element surface, and its film thickness is, for example, about 400 μm. When the semiconductor integrated circuit 1 includes a light-receiving element and a light-emitting element, the support body 7 is made of a transparent or translucent material and has a light-transmitting property. the

Then, the back surface of the semiconductor substrate 2 is ground using a back grinding device (grinder) to reduce the thickness of the semiconductor substrate 2 to a predetermined thickness (for example, about 100 μm). This grinding step may be an etching treatment, or grinding and etching treatment may be used together. Depending on the application and specifications of the final product and the initial thickness of the semiconductor substrate 2 to be prepared, this grinding step may not be necessary. the

Then, as shown in FIG. 2, only a predetermined area corresponding to the pad electrode 4 in the semiconductor substrate 2 is selectively etched from the back side of the semiconductor substrate 2, so that a part of the insulating film 3 is exposed. Hereinafter, this exposed portion is referred to as an opening 8 . The openings 8 are formed in a lattice shape on the back side of the semiconductor substrate 2 , so that the wafer-shaped semiconductor substrate 2 is divided into islands as shown in FIGS. 3A and 3B . the

The selective etching of the semiconductor substrate 2 will be described with reference to FIGS. 3A and 3B . 3A and 3B are schematic plan views viewed from the semiconductor substrate 2 side, and FIG. 2 corresponds to a cross-sectional view taken along line X-X in FIGS. 3A and 3B . the

As shown in FIG. 3A , the semiconductor substrate 2 may be etched into a substantially rectangular shape narrower than the support body 7 . As shown in FIG. 3B , by etching only the region where the pad electrode 4 is formed, the outer periphery of the semiconductor substrate 2 can also be made uneven. In the latter case, the overlapping area of the semiconductor substrate 2 and the support body 7 is large, and the semiconductor substrate 2 remains near the outer periphery of the support body 7 . Therefore, from the viewpoint of improving the support strength of the support body 7 to the semiconductor substrate 2, the latter structure is preferable. According to the latter structure, since the warping of the support body 7 caused by the difference in thermal expansion coefficient between the semiconductor substrate 2 and the support body 7 can be prevented, cracks and peeling of the semiconductor device can be prevented. The semiconductor substrate 2 may also be designed in a shape different from the planar shape shown in FIGS. 3A and 3B . The manufacturing process when the semiconductor substrate 2 is etched as shown in FIG. 3A will be described later. the

In the present embodiment, the sidewall of the semiconductor substrate 2 is etched obliquely so that the lateral width of the semiconductor substrate 2 becomes wider as it approaches the surface side, but it is also possible to make the width of the semiconductor substrate 2 constant so that the sidewall is aligned with the main surface of the support body 7. Etching is done vertically. the

Then, an insulating film 9 formed by a plasma CVD method or the like such as a silicon oxide film or a silicon nitride film is formed on the side surface and the back surface of the semiconductor substrate 2 including the inside of the opening 8 . Next, as shown in FIG. 4 , the insulating film 3 and the insulating film 9 are selectively etched using a resist layer (not shown) as a mask. This etching selectively removes insulating film 3 and insulating film 9 formed in the region from part of pad electrode 4 to dicing line DL, and at least part of pad electrode 4 is exposed at the bottom of opening 8 . the

Then, metal layers such as aluminum (Al) and copper (Cu) serving as the wiring layer 10 are formed into a film thickness of, for example, 1 μm by sputtering, plating, or other film-forming methods. Then, the metal layer is selectively etched using a resist layer (not shown) as a mask. As shown in FIG. 5 , the metal layer is connected to the pad electrode 4 by this etching to form the wiring layer 10 formed on the side surface and the back surface of the semiconductor substrate 2 . the

Then, an unillustrated electrode connection layer (for example, lamination of a nickel layer and a gold layer) covering the wiring layer 10 is formed. The reason why the electrode connection layer is formed is because the wiring layer 10 made of aluminum or the like is difficult to join with the conductive terminal 14 made of solder or the like, and also to prevent the material of the conductive terminal 14 from flowing into the wiring layer 10. The electrode connection layer may also be formed after the protective layer 13 is formed. the

Then, as shown in FIG. 6 , a portion of the passivation film 5 , adhesive layer 6 , and support 7 are removed from the semiconductor substrate 2 side by dicing or dry etching to form a groove 11 halfway through the thickness of the support 7 . A plurality of grooves 11 are formed in the vertical and horizontal directions with respect to the surface of the support body 7 along the boundary (dicing line DL) of each semiconductor device. In this way, the semiconductor substrate 2 is divided into semiconductor chips. The description will continue below as the semiconductor chip 2a. the

As long as the side surface of the adhesive layer 6 is exposed, the cross-sectional shape of the groove 11 is not limited to the V-shape shown in FIG. From the viewpoint of good inner coverage, it is preferable to set it into a V-shape or a shape in which the upper part (the part close to the surface of the semiconductor chip 2a) is curved outward. the

Next, as shown in FIG. 7 , the protective layer 13 having the opening 12 at a position corresponding to the formation region of the conductive terminal 14 described later is formed so thick that the groove 11 is formed from the side surface to the back surface of the semiconductor chip 2 a. The entire semiconductor chip 2a is buried. the

Here, the protective layer 13 is formed, for example, as follows. First, an injection resin having an opening 12 is formed to be about 30 μm higher than the semiconductor chip 2 a so as to bury the semiconductor chip 2 a using, for example, a screen printing method. the

As the material of the protective layer 13, organic materials such as polyimide resin and solder resist can be used. An absorbing material that absorbs visible light, infrared rays, or the like can also be used. the

As a method for forming the protective layer 13, coating can be performed by a dispensing method (coating method). the

As described above, the protective layer 13 of this embodiment completely covers the side surfaces of the adhesive layer 6 and is formed so thick that it fills the entire semiconductor chip 2a. Therefore, the semiconductor device 20 of the present invention has improved moisture resistance compared with conventional semiconductor devices. Therefore, even if a solder resist film having poor moisture resistance is used as the protective layer 13 in the conventional manner, since the solder resist film is formed sufficiently thicker than the conventional structure, the moisture resistance does not decrease. the

Then, a conductive material (such as solder) is printed on the electrode connection layer surface exposed from the opening 12 of the protective layer 13, and the conductive material is reflowed by heat treatment to form the spherical conductive terminal 14 shown in FIG. 8 . The method of forming the conductive terminal 14 is not limited to the above, and may be formed by an electrolytic plating method, a so-called dispensing method of applying solder or the like to a predetermined area using a dispenser, or the like. Thus, the pad electrode 4 is electrically connected to the conductive terminal 14 via the wiring layer 10 . the

Although illustration is omitted, by uniformly etching the entire back surface of the support 7, the support 7 can be thinned to a predetermined thickness (for example, about 50 μm), and the semiconductor device 20 can also be thinned. change. the

As the etching method, mechanical etching using a back grinding device (grinder), or spin wet etching in which etching is performed using a chemical solution containing hydrofluoric acid or the like while rotating the substrate is preferable. However, other etching methods such as immersion etching may be used as long as the entire back surface of the support body 7 is etched. the

As shown in FIG. 8 , the chip size package type semiconductor device 20 is completed by cutting the protective layer 13 and the support body 7 using a dicing blade. The semiconductor device 20 is mounted on a printed circuit board or the like via the conductive terminals 14 . the

In the first embodiment, the entire semiconductor chip 2 a is completely covered by the protective layer 13 including the adhesive layer 6 sideways. Therefore, contact of the adhesive layer 6 with the outside air is suppressed, and intrusion of corrosive substances (such as moisture) into the semiconductor integrated circuits 1 or the adhesive layer 6 can be prevented. the

A second embodiment of the present invention will be described below with reference to the drawings. The same structures and manufacturing steps as those of the first embodiment are denoted by the same symbols, and description thereof will be omitted. the

As shown in FIG. 8 , in the first embodiment, the entire back surface of the semiconductor substrate 2 is covered with a protective layer 13 . In contrast, as shown in FIG. 9, the semiconductor device 30 of the second embodiment is characterized in that the following process is adopted, that is, the first protective layer 13a is formed on the back surface of the adjacent semiconductor substrate 2. As shown in FIG. 10, in this The second protective layer 31 having openings is formed on the first protective layer 13a. Conductive terminals 14 are formed on the electrode connection layer through openings formed in the second protection layer 31 . the

Here, in this embodiment, as the first protective layer 13a, for example, an underfill material to which a filler is added is applied using a dispensing method. As the material of the first protective layer 13a, organic materials such as injection molding resin, polyimide resin, and solder resist film can be used. An absorbing material that absorbs visible light, infrared rays, or the like may be used, or a reflective material that reflects visible light, infrared rays, or the like may be used. A solder resist material is used as the second protective layer 31 . the

Next, a third embodiment of the present invention will be described with reference to FIG. 11. FIG. The same structures and manufacturing steps as those of the first and second embodiments are denoted by the same symbols and their descriptions are omitted. the

In the first and second embodiments, the protective layer 13 and the first protective layer 13a are formed in such a manner as to fill the groove 11 . On the other hand, as shown in FIG. 11, the semiconductor device 35 of the third embodiment is characterized in that a protective layer 41 having an opening is formed on the back surface of the semiconductor substrate 2 with a substantially uniform film thickness. The conductive terminal 14 is formed on the electrode connection layer through the opening of the protective layer 41 . The conductive paste 46 (for example, silver paste) is formed so as to cover the grooves 11 by a dispensing method. Conductive paste 46 may also be formed using screen printing. the

The semiconductor device 35 described above has formed the protective layer 41 in the same manner as the protective layer 109 formed in the conventional semiconductor device 100, and then used the conductive paste 46 to fill the groove 11 and the side surface of the semiconductor chip 2a, so it is different from the conventional structure. Compared with improved moisture resistance. Since the conductive paste 46 is formed, visible light, infrared rays, and the like can be reflected. the

If an adhesive layer is formed on the semiconductor integrated circuit 1, the quality of the semiconductor device may be lowered. For example, when the semiconductor integrated circuit 1 includes a light-receiving element and a light-emitting element, the adhesive layer prevents light incident on the semiconductor integrated circuit 1 (or light output from the semiconductor integrated circuit 1), and desired quality may not be obtained. In addition, there is a problem that light of a specific wavelength such as blue light (Blu-Ray) degrades the adhesive layer, and the operating quality of the semiconductor device is lowered due to the deteriorated adhesive layer. the

Thus, as shown in FIG. 12 , the semiconductor device 45 of the fourth embodiment does not interpose the adhesive layer 52 between the semiconductor integrated circuit 1 and the support body 7 by forming the cavity 51 . Therefore, it is an effective structure for a semiconductor device whose operation quality is lowered due to the existence of the adhesive layer 52 (for example, a semiconductor device for blue light receiving light). The structure having the cavity 51 is described as the fourth embodiment, but the present invention can also adopt the structure having the cavity 51 for the above-mentioned first, second, and third embodiments. the

When the support body 7 is completely etched with the cavity 51, as shown in FIG. device 60. The present invention can also adopt a structure in which the supporting body is completely etched for the first, second and third embodiments described above. the

Next, a multilayer semiconductor device 67 in which a plurality of semiconductor devices including the adhesive layer 52 having the opening 61 is laminated in the vertical (vertical) direction will be described with reference to FIG. 14 as a sixth embodiment. FIG. 14 shows a cross-sectional view of a laminated semiconductor device 67 in which first and second semiconductor devices 65 and 66 are sequentially laminated. The semiconductor devices 65 and 66 include a pad electrode 68 exposed to the outside from the opening 61 . Except for the point that the pad electrode 68 is exposed to the outside from the opening 61 , it has the same structure as the pad electrode 4 already described. the

In the laminated semiconductor device 67, after each semiconductor device 65, 66 is completed, the conductive terminal 14 of the second semiconductor device 66 is aligned and overlapped with the pad electrode 68 of the first semiconductor device 65, and then, for example, is bonded by thermocompression. This is accomplished by connecting the conductive terminal 14 to the pad electrode 68 . In the above description, it has been described that semiconductor devices of the same type (same size) are laminated, but as long as the pad electrodes 68 and the conductive terminals 14 are aligned, it is not limited to lamination of the same type (same size) semiconductor devices. lamination between semiconductor devices. Of course, it is also possible to further laminate other semiconductor devices on the semiconductor device 66 . the

Since this layered semiconductor device 67 does not have the support body 7, the height of the layered structure can be set to a minimum. Since the protective layer 13 is formed by filling the semiconductor substrate 2 with the protective layer 13, that is, covering the entire semiconductor chip 2a from the side surface to the back surface, it is also possible to laminate the upper and lower semiconductor devices 65, 66 in a state of close contact. , so it becomes a strong structure such as impact resistance. The protection layer 13 may also be composed of a first protection layer 13 a and a second protection layer 31 . the

Next, a seventh embodiment will be described with reference to FIGS. 1 to 6 and FIGS. 15 to 18 . Since Fig. 1 to Fig. 6 have been described in the first embodiment, detailed description is omitted, but the depth of the groove 11 in Fig. 6 is set in consideration of the thickness of the support body 7 after singulation, for example, if the When the thickness is set to about 50 μm, the groove 11 is formed so that the bottom thereof is arranged at a depth of about 70 μm from the surface of the support body 7 . Even when the groove 11 is formed by using a dicing blade, the process of using the dicing blade is only this process, and the dicing blade is not used in the process of obtaining each semiconductor device as will be described later. Therefore, compared with the manufacturing method in which the dicing blade is used in the two steps of forming the groove 11 and the step of obtaining each semiconductor device, the present embodiment uses fewer steps using the dicing blade, so the time spent on the entire manufacturing process can be shortened. time needed. the

Then, as shown in FIG. 15 , a protective layer 21 having openings 12 , 18 is formed with a thickness of, for example, 10 μm at positions corresponding to the formation regions of conductive terminals 15 described later and grooves 11 . The protective layer 21 is formed, for example, as follows. First, organic materials such as polyimide resin and solder resist are applied to the entire surface by a coating-coating method, followed by heat treatment (pre-baking). Then, the applied organic-based material is exposed-developed to form an opening exposing a predetermined area, which is then subjected to heat treatment (post-baking). In this way, the protective layer 21 having the openings 12 and 18 is obtained at positions corresponding to the formation regions of the conductive terminals 15 and the grooves 11 . Although the protective layer 21 in this embodiment completely covers the side surface of the adhesive layer 6 , only the side surface of the support body 7 is covered near the semiconductor substrate 2 , at least the protective layer 21 is not formed on the cutting line DL. the

In other words, the end portion of the protective layer 21 is arranged halfway from the surface of the support body 7 to the bottom of the groove 11 , and the protective layer 21 is not formed on the bottom of the groove 11 . By forming the openings 18 at positions corresponding to the grooves 11 of the protective layer 21 in this way, it is possible to prevent adjacent semiconductor devices from being connected through the protective layer 21 after the backside etching process of the support body 7 described later, and to properly connect the semiconductor devices. separate. the

Then, a conductive material (such as solder) is printed on the electrode connection layer surface exposed from the opening 12 of the protective layer 21, and the conductive material is reflowed by heat treatment to form the spherical conductive terminal 15 shown in FIG. 16 . The method of forming the conductive terminal 15 is not limited to the above, and may be formed by electrolytic plating, a so-called dispensing method (coating method) in which solder or the like is applied to a predetermined area using a dispenser, or the like. In this way, the pad electrode 4 is electrically connected to the conductive terminal 15 via the wiring layer 10 . the

Then, a liquid resist material is spin-coated from the back side of the semiconductor substrate 2 , and the entire conductive terminal 15 and protective layer 21 including the inner wall of the groove 11 are covered with the resist layer 16 . The resist layer 16 has a thickness to bury the semiconductor chip 2a. This resist layer 16 is then hardened by performing heat treatment. Since the groove 11 is filled with the resist layer 16 via the opening 18 , the resist layer 16 is in contact with the support body 7 at the bottom of the groove 11 . the

Next, a protective member 17 such as a film-like UV tape or a glass substrate is bonded to the back surface of the semiconductor chip 2a. The protection member 17 holds the semiconductor chip 2 a and has a function of protecting the conductive terminals 15 and the like during a backside etching process of the support body 7 described below and subsequent transportation. the

Next, as shown in FIG. 17, the entire back surface of the support body 7 is uniformly etched from the back surface of the support body 7 until the grooves 11 and the resist layer 16 are exposed, and the support body 7 is thinned to a predetermined thickness (for example, about 50 μm). ). As the etching method, mechanical etching using a back grinding device (grinder), or spin wet etching in which etching is performed using a chemical solution containing hydrofluoric acid or the like while rotating the substrate is preferable. However, other etching methods such as dip etching may be used as long as the entire back surface of the support body 7 is etched. the

The etching of the support body 7 is controlled in time according to a pre-calculated etching ratio, or the exposure of the resist layer 16 is detected by an optical device, and terminated by such a method. In this way, the wafer-shaped support body 7 is singulated in an island shape, that is, the chip-shaped singulated semiconductor devices 70 can be collectively formed. the

Even if the groove 11 is exposed from the back surface of the support body 7, the resist layer 16 is formed in the groove 11, and the protective member 17 is bonded to the back surface of the semiconductor chip 2a. Therefore, the individual semiconductor devices 70 are not dispersed. Since the resist layer 16 and the protective member 17 act as barriers, corrosive substances such as chemicals do not enter the semiconductor chip 2a side, and the operating characteristics of the semiconductor device 70 do not deteriorate. the

After the back surface of the support body 7 is etched, each semiconductor device 70 is transported with the protective member 17 bonded thereto, but the gap between adjacent semiconductor devices 70 is filled with the resist layer 16 . Therefore, mechanical damage such as chipping due to rubbing between adjacent semiconductor devices 70 is less likely to occur during transportation. the

Then, a predetermined dissolving agent is supplied from the back side of the support body 7 to dissolve the exposed resist layer 16 , and then the singulated semiconductor devices 70 are picked up from the protection member 17 . When the protective member 17 is a UV tape, the semiconductor device 70 can be easily picked up by irradiating ultraviolet rays to the protective member 17 to reduce its adhesiveness. the

It is also possible to bond a new tape on the back of the support body 7, then peel off the protective member 17, and then supply a prescribed dissolving agent from the back side of the semiconductor chip 2a to dissolve the resist layer 16. the

As shown in FIG. 18 , a chip-scale package type semiconductor device 70 is completed through the above steps. The semiconductor device 70 is mounted on a printed board or the like via the conductive terminals 15 . the

In the seventh embodiment described above, each semiconductor device is obtained by etching the entire back surface of the support body 7 instead of dividing each semiconductor device one by one by the dicing line DL as in the prior art. Therefore, since all the semiconductor devices are collectively singulated, the time required for the dicing process can be greatly shortened, and productivity can be dramatically improved. the

In the seventh embodiment, thinning of the support body 7 and singulation of the semiconductor device are achieved at the same time, so that thinner semiconductor devices can be manufactured more efficiently than in the prior art. Since the thinning of the support body 7 is carried out after all the structural elements of the semiconductor device such as the wiring layer 10, the conductive terminal 15, and the protective layer 21 are formed, the reduction in the rigidity of the support body 7 caused by the thinning will not be affected by each structural element. stage of formation. the

Even if the groove 11 is exposed from the back surface of the support body 7 by etching the back surface of the support body 7, the resist layer 16 is formed in the groove 11, and the protective member 17 is attached to the back surface of the semiconductor chip 2a. Therefore, etching substances (for example, fine particles generated during etching of the back surface of the support body 7 and chemicals used in the etching step) do not enter the semiconductor chip 2a side, and quality deterioration can be suppressed. the

In the seventh embodiment, the side of the adhesive layer 6 is completely covered by the protective layer 21 , and the side of the support 7 close to the semiconductor substrate 2 is covered. Therefore, contact of the adhesive layer 6 with the outside air is suppressed, and intrusion of etching substances (such as moisture) into the semiconductor integrated circuits 1 and the adhesive layer 6 can be prevented. the

An eighth embodiment of the present invention will be described below with reference to the drawings. The same structures and manufacturing steps as those of the seventh embodiment are denoted by the same symbols and their descriptions are omitted. the

As shown in FIG. 17 , in the seventh embodiment, the back surface of the support body 7 is etched halfway in the thickness direction of the support body 7 . In contrast, the eighth embodiment is characterized in that the process of etching the entire support body 7 is employed. The etching of the support body 7 is terminated when the entire support body 7 is etched, for example, by controlling the etching ratio. As shown in FIG. 19 , through this process, a semiconductor device 75 having an adhesive layer 6 on the top can be obtained. At this time, the adhesive layer 6 has a function of protecting the upper surface of the semiconductor chip 2a. the

In the eighth embodiment, as in the seventh embodiment, all of the semiconductor devices are collectively singulated, so that the time required for the dicing process can be greatly shortened, and productivity can be improved. Furthermore, since the thickness of the support body 7 is eliminated, a semiconductor device thinner than that of the seventh embodiment can be obtained. the

Next, a ninth embodiment of the present invention will be described with reference to the drawings. The same structures and manufacturing steps as those of the seventh and eighth embodiments are denoted by the same symbols and their descriptions are omitted. the

In the seventh and eighth embodiments, the adhesive layer 6 is uniformly formed between the semiconductor substrate 2 and the support body 7 . In contrast, as shown in FIG. 20, the ninth embodiment is characterized in that an adhesive layer 71 is locally formed, and the cavity 51 in FIG. 12 of the fourth embodiment is formed between the semiconductor chip 2a and the support body 7. The cavity 72. the

The cavity 72 is an internal space surrounded by the semiconductor chip 2a, the adhesive layer 71 and the support body 7, for example, by coating the material of the adhesive layer 71 annularly on the surface of the semiconductor substrate 2, and then bonding the support body 7. form. the

With the cavity 72 in this state, the back surface of the support body 7 is etched until the groove 11 is exposed in the same manner as described with reference to FIGS. 16 and 17 , thereby forming a semiconductor device including the cavity 72 . the

Although the description of the fourth embodiment is repeated, if an adhesive layer is formed on the semiconductor integrated circuit 1, the quality of the semiconductor device may be lowered. For example, when the semiconductor integrated circuit 1 includes a light-receiving element and a light-emitting element, the adhesive layer prevents light incident on the semiconductor integrated circuit 1 (or light output from the semiconductor integrated circuit 1), and desired quality may not be obtained. the

In addition, there is a problem that the adhesive layer is degraded by light of a specific wavelength such as blue light, and the operating quality of the semiconductor device is lowered by the degraded adhesive layer. the

Since the ninth embodiment forms the cavity 72 similarly to the fourth embodiment, the adhesive layer 52 is not interposed between the semiconductor integrated circuit 1 and the support body 7 . Therefore, it becomes an effective structure for a semiconductor device whose operation quality is lowered due to the presence of the adhesive layer (for example, a semiconductor device for blue light receiving light). the

In the state having the cavity 72 as shown in FIG. 20 , when the support body 7 is completely etched as described in the eighth embodiment, as shown in FIG. The semiconductor device of the adhesive layer 71 . This is the same structure as the structure of the adhesive layer 52 having the opening 61 in the fifth embodiment shown in FIG. 13 . the

Therefore, similarly to the description of the sixth embodiment, a plurality of semiconductor devices including the adhesive layer 71 having the opening 32 as shown in FIG. 22 can be laminated in the vertical direction to form a laminated semiconductor device. Although it is repeated, its outline will be described with reference to FIG. 22 . FIG. 22 shows a cross-sectional view of a laminated semiconductor device 37 in which semiconductor devices 35 and 36 are sequentially laminated. The semiconductor devices 35 and 36 include a pad electrode 38 exposed to the outside from the opening 32 . Except for the point that the pad electrode 38 is exposed to the outside from the opening 32 , it has the same structure as the pad electrode 4 already described. the

In the laminated semiconductor device 37, after the semiconductor devices 65 and 66 are completed, the conductive terminals 15 of the semiconductor device 36 are aligned and overlapped with the pad electrodes 38 of the semiconductor device 35, and then the conductive terminals 15 and The pad electrodes 38 are connected to complete. It is of course also possible to laminate other semiconductor devices on the semiconductor device 36 . Since this layered semiconductor device 37 does not have the support body 7, the height of the layered structure can be set to a minimum. the

A tenth embodiment of the present invention will be described below with reference to the drawings. The same structures and the same manufacturing steps as those of the seventh to ninth embodiments are denoted by the same symbols and their descriptions are omitted. the

In the seventh to ninth embodiments, the entire back surface of the support body 7 is uniformly etched. In contrast, the tenth embodiment employs a process of partially etching the back surface of the support body 7 . First, as shown in FIG. 23, the groove 11 and the resist layer 16 are formed, and after the protective member 17 is bonded on the back surface of the semiconductor chip 2a, the resist layer 47 will have an opening 40 at a position corresponding to the groove 11. Formed on the back of the support body 7 . the

Then, as shown in FIG. 24 , the back surface of the support body 7 is partially etched using the resist layer 47 as a mask to form the opening 42 . A plurality of openings 42 are formed in the vertical and horizontal directions relative to the back surface of the support body 7 at positions facing the grooves 11 , that is, along the boundaries of the respective semiconductor devices. This etching is carried out until the opening 42 reaches the groove 11 and the groove 11 and the resist layer 16 are exposed. In this way, the wafer-shaped support body 7 is singulated in an island shape, and a chip-shaped substrate is formed together. semiconductor device 43 . the

As an etching method, wet etching is preferable from the viewpoint of processing a large number of substrates at one time and shortening the manufacturing process time. In this case, the resist layer 47 may be immersed in a container filled with a predetermined chemical solution. Etching of the rear side of the support body 7 can also be performed by dry etching and sandblasting. the

In Fig. 24, the side wall of the support body 7 that reaches the groove 11 from the back is obliquely etched, but when the support body 7 is etched by anisotropic etching such as dry etching and sandblasting, it is also possible to make the side wall and the support body 7 The main face is approximately vertical. the

Then, a predetermined dissolving agent is supplied from the opening 42 to dissolve the resist layer 16, and then each semiconductor device 43 is peeled off from the protective member 17,

In the tenth embodiment described above, instead of dividing the dicing line DL one by one to obtain each semiconductor device as in the prior art, the resist layer 47 having the opening 42 along the boundary of each semiconductor device is used to form the support The backside of body 7 is partially etched to obtain individual semiconductor devices. Therefore, since all the semiconductor devices are collectively singulated, the time required for the dicing process can be greatly shortened, and productivity can be dramatically improved. the

An eleventh embodiment of the present invention will be described below with reference to the drawings. The structures and manufacturing steps that are the same as those of the seventh to tenth embodiments are denoted by the same symbols and their descriptions are omitted. the

As shown in FIG. 25 , a tape 50 is bonded to the surface of the semiconductor substrate 2 via an adhesive layer 6 , and a support body 7 is bonded to the tape 50 . The tape 50 is made of polyimide, for example, and is preferably made of a material different from the adhesive layer 6 and the protective layer 55 described later. This is because a solvent for lowering the viscosity of the tape 50 may be supplied when the tape 50 is removed, and the adhesive layer 6 and the protective layer 55 are not removed simultaneously at this time. Then, the opening 8, the insulating film 9, the wiring layer 10, and the like are formed in the same steps as in the seventh embodiment. the

Then, as shown in FIG. 26, the passivation film 5, the adhesive layer 6, and the tape 50 are partially removed from the semiconductor chip 2a side by a dicing blade and dry etching, thereby forming a groove 53 reaching halfway in the thickness direction of the tape 50. A plurality of grooves 53 are formed vertically and horizontally with respect to the surface of the tape 50 along the boundaries (cutting lines DL) of the respective semiconductor devices. the

Then, a protective layer 55 made of solder resist or the like having the openings 12 and 54 is formed at a position corresponding to the formation region of the conductive terminal 15 and the groove 53 . Although the protective layer 55 of this embodiment completely covers the side of the adhesive layer 6, the side of the tape 50 is only covered near the semiconductor chip 2a, at least the protective layer 55 is not formed on the dicing line DL. the

In other words, the end portion of the protective layer 55 is arranged halfway from the side of the adhesive layer 6 to the bottom of the groove 53 , and the protective layer 55 is not formed on the bottom of the groove 53 . By forming the opening 54 at the position corresponding to the groove 53 in this way, adjacent semiconductor devices can be prevented from being connected through the protective layer 55 when the tape 50 is removed, and each semiconductor device can be properly separated. the

Then, as shown in FIG. 27 , conductive terminals 15 are formed on the electrode connection layer exposed from the opening 12 of the protective layer 55 . Next, a resist material is applied from the back side of the semiconductor chip 2 a, and the entire conductive terminal 15 and protective layer 55 including the inner wall of the groove 53 are covered with the resist layer 16 . The resist layer 16 is in contact with the tape 50 at the bottom of the trench 53 . Then, the protective member 17 is bonded to the back surface of the semiconductor chip 2a. the

Next, as described using FIG. 24 , the support body 7 is partially etched using the resist layer 47 to expose the tape 50 . Then, a predetermined dissolving agent is supplied to the exposed tape 50 to remove the tape 50 and separate the semiconductor chip 2 a from the support body 7 . the

Next, the resist layer 16 is removed, and the singulated semiconductor devices 56 are picked up from the protection member 17 . Through the above steps, the chip size package type semiconductor device 56 shown in FIG. 28 is completed. the

In the eleventh embodiment, as in the seventh to tenth embodiments, all the semiconductor devices are collectively singulated, so that the time required for the dicing process can be greatly shortened, and productivity can be improved. Furthermore, since the thickness of the support body 7 is eliminated, a thin semiconductor device can be obtained. the

A twelfth embodiment of the present invention will be described below. The descriptions of the same structures and manufacturing processes as those of the first to fifth embodiments are omitted or simplified. the

As shown in FIG. 16 , in the seventh embodiment, the entire conductive terminal 15 and the protective layer 21 are covered with the resist layer 16 including the inner wall of the groove 11 . In contrast, in the twelfth embodiment, the resist layer 16 is not formed, and the protective member 17 is attached to the back surface of the semiconductor chip 2a. Except for the point that the resist layer 16 is not formed, it is the same structure as that of FIG. 16 , so the illustration of the twelfth embodiment is omitted. the

Then, the entire back surface of the support body 7 is uniformly etched, or a resist layer having openings at positions corresponding to the grooves 11 is selectively formed on the back surface of the support body 7 (see FIG. 23 ). The layer serves as a mask to partially etch the carrier 7 . the

Here, in the seventh and tenth embodiments, the etching is performed until the grooves 11 are exposed. In this way, the wafer-like support body 7 is singulated, and semiconductor devices singulated into chips are collectively formed. In contrast, in the twelfth embodiment, the etching of the support body 7 is stopped when the groove 11 is almost exposed. That is, the thickness of the supporting body 7 is very thin at the positions corresponding to the grooves 11 . The thickness of the support body 7 at this position is, for example, 50 to 100 μm. the

Since the etching is not carried out before the groove 11 is exposed, even if the resist layer 16 is not formed, the support body 7 becomes an obstacle so that corrosion substances (such as particles generated during etching of the back side of the support body 7 and the etching process are used) chemical solution, etc.) does not intrude toward the semiconductor substrate 2 side, and quality deterioration can be suppressed. the

Then, a physical mechanical load is applied to the thinned portion of the support body 7 to cut the support body 7 along the groove 11 . Specifically, for example, the support body 7 is cut by applying predetermined pressure along the groove 11 from the back side of the support body 7 toward the front side using human hands or a predetermined instrument. the

In this way, the wafer-shaped support body 7 is singulated into islands, that is, semiconductor devices singulated into chips are formed. the

In this way, it is also possible to achieve singulation of the semiconductor device by going through two steps (the step of etching the back surface of the support body 7 and the step of applying a physical load to the corresponding positions of the grooves 11). According to this manufacturing method, there is an advantage that it is possible to prevent corrosion substances from entering the semiconductor chip 2 a side without forming the resist layer 16 . Since there is no need to use a cutting knife, the time required for the cutting process can be shortened. By continuously or simultaneously applying a physical load to all the positions corresponding to the grooves 11 on the back surface of the support body 7 , substantially all of the singulated semiconductor devices can be obtained, and productivity can be improved. the

This invention is not limited to the said Example, Of course, it can change in the range which does not deviate from the summary. For example, the above-described embodiment has described a BGA (Ball Grid Array) type semiconductor device with spherical conductive terminals, but the present invention can also be applied to an LGA (Land Grid Array: Surface Grid Array) type and other CSP (Chip Size Package) types. semiconductor device. the

In the above embodiments, the conductive terminals are formed on the back surface of the semiconductor substrate, but the conductive terminals may be arranged adjacent to the side surface of the semiconductor substrate. the

Although the protective layers 21 and 55 are formed in the seventh to twelfth embodiments, they can also be applied to semiconductor devices that do not form a protective layer, and can be widely used as a manufacturing method for efficiently obtaining semiconductor devices that are singulated into chips. . In this case, it is preferable to use a metal material (for example, copper) that is highly resistant to corrosive substances (moisture, etc.) as the wiring layer 10 . the

Claims (14)

1. A semiconductor device comprising: a metal pad connected to a circuit element in a semiconductor chip and formed near a side surface of the semiconductor chip, an insulating film formed on the side surface and the back surface of the semiconductor chip, a metal wiring connected to the back surface of the metal pad and extending from the side surface to the back surface of the semiconductor chip in contact with the insulating film, a protective layer that fills the whole including the end of the semiconductor chip with a uniform surface, a conductive terminal electrically connected to the metal wiring through an opening formed in the protective layer, The thickness of the end portion of the protective layer is thicker than the total thickness of the semiconductor chip, the insulating film, and the metal wiring. 2. The semiconductor device according to claim 1, wherein the protective layer comprises a first protective layer and a second protective layer. 3. The semiconductor device according to claim 1 or 2, further comprising a support body bonded so as to cover the surface portion of the semiconductor chip including the metal pad. 4. A semiconductor device, characterized in that other semiconductor devices are laminated on the semiconductor device according to claim 1, and the protective layer of the semiconductor device according to claim 1 on the upper side and the semiconductor device on the lower side are formed together. connect. 5. A semiconductor device comprising: a metal pad connected to a circuit element in a semiconductor chip and formed near a side surface of the semiconductor chip, an insulating film formed on the side surface and the back surface of the semiconductor chip, a metal wiring connected to the back surface of the metal pad and extending from the side surface to the back surface of the semiconductor chip in contact with the insulating film, a protective layer formed on the side and back of the semiconductor chip, a conductive terminal connected to the metal wiring through an opening formed in the protective layer, A conductive film formed on the protective layer and buried in a uniform surface from the side surface to the end of the semiconductor chip. 6. The semiconductor device according to claim 5, further comprising a support body bonded so as to cover the surface portion of the semiconductor chip including the metal pad. 7. A method of manufacturing a semiconductor device, comprising: A step of preparing a semiconductor substrate on which a metal pad is formed via a first insulating film, and bonding the surface side of the semiconductor substrate including the metal pad to the surface of the support, a step of removing a part of the semiconductor substrate from the rear surface thereof to expose the first insulating film, a step of forming a second insulating film on the entire back surface of the semiconductor substrate, a step of removing a part of the first and second insulating films to expose the metal pad, forming a metal wiring connected to the back surface of the metal pad and extending on the back surface of the semiconductor substrate, A step of removing a part of the semiconductor substrate to form a groove reaching halfway in the thickness direction of the support on the surface of the support, a step of forming a protective layer so as to fill the entire back surface of the semiconductor substrate including the groove, A step of forming a conductive terminal electrically connected to the metal wiring through an opening formed in the protective layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the protective layer includes a step of forming a second protective layer on the first protective layer after forming the first protective layer. 9. A method of manufacturing a semiconductor device, comprising: A step of preparing a semiconductor substrate on which a metal pad is formed via a first insulating film, and bonding the surface side of the semiconductor substrate including the metal pad to the surface of the support, a step of removing a part of the semiconductor substrate from the rear surface thereof to expose the first insulating film, a step of forming a second insulating film on the entire back surface of the semiconductor substrate, a step of removing a part of the first and second insulating films to expose the metal pad, forming a metal wiring connected to the back surface of the metal pad and extending on the back surface of the semiconductor substrate, A step of removing a part of the semiconductor substrate and forming a groove reaching halfway in the thickness direction of the support on the surface of the support, a step of forming a first protective layer on the rear surface side of the semiconductor substrate including the groove, a step of forming a conductive terminal electrically connected to the metal wiring through an opening formed in the first protective layer, A step of forming a second protection layer on the first protection layer. 10. The method of manufacturing a semiconductor device according to claim 7, wherein an injection molding resin is applied in the step of forming the protective layer. 11. The method of manufacturing a semiconductor device according to claim 8 or 9, wherein an injection molding resin is applied in the step of forming the first protective layer. 12. The method of manufacturing a semiconductor device according to claim 9, wherein a conductive material is applied in the step of forming the second protective layer. 13. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of reducing the thickness of the support. 14. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of removing the support.

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