CN101299448B - Luminescence transistor with vertical gate structure and preparation method thereof - Google Patents

Abstract

The invention discloses a luminescent transistor with the vertical gate structure and the preparation method, which is provided with a buffer layer, a high concentration n-type layer, an intrinsic layer, a multiquantum well layer, a p-type layer on the substrate in turn; the outside of the buffer layer, the high concentration n-type layer and the intrinsic layer enwraps the oxide layer and the metallic aluminium layer in turn. A source electrode is formed on the high concentration n-type layer, a drain electrode is arranged on the p-type layer and the gate electrode is connected with the metallic aluminium layer. The luminescent transistor with the vertical gate structure is formed with an even channel on the lateral periphery of the transistor, and the intrinsic layer is not formed with the short-channel effect, which increases the pressure resistance.

Description

Light-emitting transistor with vertical gate structure and preparation method thereof

technical field

The invention relates to a light-emitting transistor, in particular to a light-emitting transistor with a vertical gate structure and a preparation method thereof.

Background technique

MOSFET transistors occupy a dominant position in both discrete devices and integrated circuits. They have good temperature stability, high input impedance, and low power consumption. In particular, there is natural isolation between each device, which is most suitable for making large-scale integrated circuits. Since the MOSFET is a voltage-controlled device, it does not require any input current, and only one of the large number of holes and electrons is used as the working carrier of the MOSFET, so there is no carrier accumulation effect, so that it has excellent conversion characteristics and breakdown resistance. very good.

LED is used more and more in the field of semiconductor lighting. It is mainly used to make electronic display screens, LCD display backlights, high-power lamps and street lamps, semiconductor lighting lamps, etc. In these applications, the number of LEDs is large and the total control current is large, requiring special The control circuit of the control circuit, and the control circuit is complicated, and it is urgent to improve the light-emitting diode.

Contents of the invention

The invention adds an electrode to the traditional light-emitting diode, and changes the original two-terminal current control to three-terminal voltage control. When a large number of LED applications and high-power LED applications are used, the light-emitting transistor can be used to save a lot of traditional LED current. Dedicated circuits increase the reliability of the overall application and greatly reduce the application cost.

However, adding electrodes to the light-emitting diode may occupy more light-emitting surfaces and reduce luminous efficiency. In terms of occupying as little light-emitting surface as possible, a vertical gate structure is selected. This structure is formed on the periphery of the light-emitting transistor compared with the general horizontal structure. The gate can control the conductive channel between the source and the drain in a large area, so that the light extraction of the light-emitting surface is more uniform, and it is easy to control the light extraction of the light-emitting area through related processes.

The object of the present invention is to provide a light-emitting transistor with a vertical gate structure with relatively uniform light extraction and low power consumption.

The present invention also provides a preparation method of the light-emitting transistor with the above-mentioned vertical gate structure.

A light-emitting transistor with a vertical gate structure of the present invention is characterized in that: a buffer layer, a high-concentration n-type layer, an intrinsic layer, a multi-quantum well layer, and a p-type layer are sequentially grown on the substrate; A first notch is opened on the outside of the multi-quantum well layer and the intrinsic layer, and a source electrode connected to the high-concentration n-type layer is arranged on the first notch; the outer sides of the buffer layer, the high-concentration n-type layer and the intrinsic layer are sequentially Wrapping the first oxide layer and the first metal aluminum layer, except the outside of the first notch; there is a second notch on the side of the p-type layer and the multi-quantum well layer, and the second notch is grown on the second notch. An oxide layer, the first oxide layer is connected to the second oxide layer; the second metal aluminum layer is grown on the second oxide layer, the first metal aluminum layer is connected to the second metal aluminum layer; the second oxide layer and The second metal aluminum layer is not connected to the multi-quantum well layer; a drain electrode is arranged on the p-type layer, and a gate electrode is arranged on the second metal aluminum layer.

The aforementioned substrate may be square, preferably a square substrate with rounded and chamfered corners. Further, the first notch and the second notch are arranged at different corners.

A method for preparing a light-emitting transistor with a vertical gate structure of the present invention comprises the following steps:

(a) A buffer layer, a high-concentration n-type layer, an intrinsic layer, a multi-quantum well layer, and a p-type layer are sequentially grown on the substrate;

(b) Etching away the outer surfaces of the buffer layer, high-concentration n-type layer, intrinsic layer, multiple quantum well layer, and p-type layer;

(c) growing the first oxide layer and the first metal aluminum layer sequentially on the outer sides of the buffer layer, high-concentration n-type layer, intrinsic layer, multi-quantum well layer, and p-type layer, and then the multi-quantum well layer and p The first oxide layer and the first metal aluminum layer on the outer surface of the mold layer are etched away;

(d) Selecting the position of the first notch on the side of the p-type layer, etching to the high-concentration n-type layer, and etching away the first oxide layer and the first metal aluminum layer outside the first notch;

(e) Select the second notch position on the side of the p-type layer, etch to the intrinsic layer; grow a second oxide layer connected to the first oxide layer on the second notch, and then grow a second oxide layer connected to the first oxide layer. a second metal aluminum layer connected to the metal aluminum layer;

(f) making a source electrode connected to the high-concentration n-type layer on the first notch; making a gate electrode on the second metal aluminum layer; making a drain electrode on the p-type layer.

In the light-emitting transistor with a vertical gate structure of the present invention, the gate region is on the periphery of the side of the transistor, the channel formed is uniform, the intrinsic layer does not form a short channel effect, and the withstand voltage performance is improved.

Description of drawings

Fig. 1 is the schematic diagram of embodiment 1 growth main part;

Fig. 2 is a schematic diagram of growing oxides on the side and surface of the main body in Example 1;

3 is a schematic diagram of etching away the drain electrode region 13 and part of the oxide side in Embodiment 1;

Fig. 4 is a schematic diagram of evaporating metal aluminum on the side of the oxide and forming a drain electrode in region 13 in embodiment 1;

5 is a schematic longitudinal cross-sectional view along the center of the light-emitting transistor formed in Example 1;

6 is a top view of the light-emitting transistor finally formed in Example 1;

FIG. 7 is a front cross-sectional view along the line connecting the centers of the source electrode and the gate electrode in FIG. 6 .

Among them, 1 is the drain electrode, 2 is the p-type layer, 3 is the multi-quantum well layer, 4 is the first oxide layer, 41 is the second oxide layer, 5 is the first metal aluminum layer, and 51 is the second metal aluminum layer , 6 is the intrinsic layer, 7 is the n-type layer, 8 is the buffer layer, 9 is the substrate, 10 is the conductive channel, 11 is the source electrode, 12 is the gate electrode, 13 is the drain electrode region, 14 is the second concave Mouth, 15 is the first notch.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

The invention is suitable for GaN and GaAlInP series materials, the luminescent colors of GaN materials are green and blue, and the GaAlInP materials are red, orange and yellow.

Example 1

The preparation method of the present embodiment is as follows:

(1) The lattice matching between SiC and GaN is good, and there are many excellent characteristics. SiC is selected as the substrate 9; a 2.0um thick GaN buffer layer 8 is grown on the substrate 9; the first conductive layer is epitaxially grown on the buffer layer. The high-concentration Si-doped n-type GaN layer 7 is used as the electron emission region, the growth temperature is about 1050 degrees, and the thickness is selected to be 3um, wherein the doping concentration of Si is 1×10 ¹⁹ atoms/cm ³ ; on the n-type GaN layer 7 To form the intrinsic GaN layer 6, in order to prevent the electrons in the high-concentration n-type GaN layer 7 from diffusing to the intrinsic layer 6, the thickness of the intrinsic layer 6 should be much larger than the diffusion width of the electrons, generally 400-500nm is suitable; Continue to grow the InGaN/GaN superlattice structure on the layer 6 to form 10-20 multi-quantum well layers 3 as high-brightness active light-emitting regions. The growth temperature is about 750 degrees. The thickness of the multi-quantum well layer 3 is generally selected as 150-300 nm ; Mg-doped p-type GaN material is grown on the multi-quantum well layer 3 to form a p-type layer 2, wherein the doping concentration of Mg is 1×10 ¹⁹ atoms/cm ³ ; the growth temperature is about 900 degrees, and the p-type layer 2 The thickness is 200nm, and the above growth is shown in Figure 1.

(2) As shown in accompanying drawing 2, etch the side part of the main body, and then grow the first oxide layer 4. Since the growth and etching process of the _SiO2 material is relatively mature, the oxide layer is selected to use _SiO2 as the material. layer wraps p-type layer 2, multi-quantum well layer 3, intrinsic layer 6, n-type layer 7, and buffer layer 8. The side thickness of the first oxide layer 4 is selected to be 120-150 nm, and the surface oxide thickness of the p-type layer 2 is About 80-100nm.

(3) Etch the peripheral side and the drain electrode region 13 at a distance of 60 to 70 nm from the side by pattern exposure, as shown in Figure 3; the side etching part is shown in the figure, which is used for the next step of evaporation of aluminum Prepare.

(4) Then, a layer of aluminum is evaporated on the main body by evaporation method, and the first metal aluminum layer 5 is formed on the outer surface and the drain electrode 1 is formed in ohmic contact, as shown in FIG. 4 .

(5) Remove the metal and oxide on the side surfaces of the p-type layer 2 and the multi-quantum well layer 3 by etching and exposure processes, and remove the oxide layer on the upper surface. The structure is shown in Figure 5.

(6) Through an etching process, one corner of the p-type layer 2 is etched to the high-concentration n-type GaN layer 7 to form a first notch 15, and the etching depth of the first notch 15 is the surface or surface of the n-type layer 7 Hereinafter, it is enough to ensure that the source electrode formed in the later stage can have good contact with the semiconductor layer, and the first oxide layer 4 and the first metal aluminum layer 5 on the periphery of the first notch 15 are also etched away, and the p-type layer 2 and the first aluminum layer are etched away. A corner adjacent to the first notch 15 is etched to the intrinsic layer 6, and the etching depth is based on the interface between the intrinsic layer 6 and the multi-quantum well layer 3, so that electrons can enter the quantum well layer through the channel here. , forming the second notch 14 .

The second oxide layer 41 is grown on the second notch 14. The second oxide can be made of aluminum oxide, and the oxide layer can be formed by directly oxidizing aluminum. The second oxide layer 41 and the first oxide layer 4, the second metal aluminum layer 51 is evaporated on the second oxide layer 41, and the second metal aluminum layer 51 is connected to the first metal aluminum layer 5. The second oxide layer 41 and the second metal aluminum layer 51 are not connected to the multi-quantum well layer 3 .

A gate electrode 12 is formed on the second metal aluminum layer 51 , and a source electrode 11 is formed on the first notch 15 as an ohmic contact. Wherein the gate electrode 12 retracts the side electrode of the main body to the second notch 14, and ensures excellent contact between the metal layer and the side metal, and the second oxide layer 41 here is used to isolate the metal electrode from the intrinsic layer 6. touch.

The light-emitting transistor with a vertical gate structure in this embodiment has the following characteristics:

(1) The gate electrode, drain electrode and source electrode are integrated in the light-emitting area, and placing the gate area on the periphery of the side of the transistor saves a lot of space, allowing the light-emitting surface to expand in a large area.

(2) The conductive channel 10 is formed on the side of the transistor, and the light extraction is relatively uniform and the power consumption is low. The channel current can be controlled by driving with a small voltage, and the luminance of light can be further controlled.

(3) Use the intrinsic layer 6 to block the contact between the p-type layer 2 used as the drain region and the n-type layer 7 used as the source region, so that when no voltage is applied to the gate, the p-i-n layer of the light-emitting transistor is non-conductive of.

(4) The light-emitting transistor can increase the light extraction efficiency by increasing the internal quantum efficiency. The multi-quantum well layer 3 greatly improves the luminous efficiency, and the multi-quantum well layer 3 grows on the intrinsic layer 6 as a light-emitting active region, and a small critical current can be obtained by using the multi-quantum well as the active light-emitting region. Materials can alter the lattice mismatch to generate compressive or tensile strains that can change wavelength and reduce critical current.

(5) The gate area of the vertical structure is located on the side periphery of the light-emitting transistor, the oxide layer 4 is formed on the side of the light-emitting transistor, the metal aluminum layer 5 surrounds the oxide layer 4, and finally the metal layer 5 is included in a certain part of the transistor. A gate electrode is formed at the corner, and when a voltage is applied to the gate electrode, a conduction channel 10 is formed in the intrinsic layer 6 to open a channel for electrons to enter the multi-quantum well layer 3 .

Claims (5)

1. A light-emitting transistor with a vertical gate structure, characterized in that: a buffer layer (8), a high-concentration n-type layer (7), an intrinsic layer (6), and a multi-quantum layer are grown sequentially on a substrate (9). well layer (3), p-type layer (2); a first notch (15) is opened on the outside of the p-type layer (2), the multi-quantum well layer (3) and the intrinsic layer (6), and the first notch The source electrode (11) connected to the high-concentration n-type layer (7) is arranged on the mouth (15); the outer sides of the buffer layer (8), high-concentration n-type layer (7) and intrinsic layer (6) are wrapped in sequence The first oxide layer (4) and the first metal aluminum layer (5), except the outside of the first notch (15); the side of the p-type layer (2) and the multi-quantum well layer (3) has a second Two notches (14), the second oxide layer (41) is grown on the second notch (14), the first oxide layer (4) is connected with the second oxide layer (41); the second oxide layer The second metal aluminum layer (51) is grown on the layer (41), and the first metal aluminum layer (5) is connected with the second metal aluminum layer (51); the second oxide layer (41) and the second metal aluminum layer ( 51) It is not connected to the multi-quantum well layer (3); the drain electrode (1) is arranged on the p-type layer (2), and the gate electrode (12) is arranged on the second metal aluminum layer (51). 2. The light-emitting transistor with a vertical gate structure according to claim 1, characterized in that the substrate (9) is square. 3. The light-emitting transistor with a vertical gate structure according to claim 2, characterized in that the four corners of the substrate (9) are all rounded and chamfered. 4. The light-emitting transistor with a vertical gate structure according to claim 2 or 3, characterized in that the first notch (15) and the second notch (14) are arranged at different corners. 5. The preparation method of the light-emitting transistor with vertical gate structure according to claim 1, comprising the following steps: (a) a buffer layer (8), a high-concentration n-type layer (7), an intrinsic layer (6), a multi-quantum well layer (3), and a p-type layer (2) are sequentially grown on the substrate (9); (b) Etching away the outer surfaces of the buffer layer (8), the high-concentration n-type layer (7), the intrinsic layer (6), the multi-quantum well layer (3), and the p-type layer (2); (c) The first oxide layer is sequentially grown on the outer surfaces of the buffer layer (8), the high-concentration n-type layer (7), the intrinsic layer (6), the multi-quantum well layer (3), and the p-type layer (2) (4) and the first metal aluminum layer (5), then the first oxide layer (4) and the first metal aluminum layer (5) on the outer side of the multi-quantum well layer (3) and the p-type layer (2) etch away; (d) select the first notch (15) position on the side of the p-type layer (2), etch to the high-concentration n-type layer (7), the first oxide layer (4) outside the first notch (15) ) and the first metal aluminum layer (5) are also etched away; (e) select the second notch (14) position on the side of the p-type layer (2), etch to the intrinsic layer (6); grow on the second notch (14) and the first oxide layer ( 4) a connected second oxide layer (41), and then grow a second metal aluminum layer (51) connected to the first metal aluminum layer (5); (f) make a source electrode (11) connected to the high-concentration n-type layer (7) on the first recess (15); make a gate electrode (12) on the second metal aluminum layer (51); The drain electrode (1) is formed on the layer (2).

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