CN101290803B - Shift register device and shift register thereof - Google Patents

Abstract

A shift register device and a shift register thereof. The shift register comprises an input unit, a feedback unit, an output unit and a reset unit. The shift register of the invention can use any switch element selected from MOS, BJT and other switch transistors to form the circuit of the shift register, and uses the special coupling relation of the units to match with the clock signals with different pulse periods to achieve the register and displacement of the input signal.

Description

Shift register device and its shift register

field of invention

The present invention relates to a driver device, and in particular to a shift register device of a driver device and a shift register thereof.

technical background

FIG. 1 is a shift register architecture in a conventional driver device, which is generally known as a Thomson circuit. The shift register includes NMOS transistors (N type metal oxide semiconductor transistor) 102-108, and capacitors 110, 112. IN, OUT, RES and COM in the figure respectively represent input signal, output signal, reset signal and common potential, while CLK1 and CLK2 represent two different clock signals respectively.

The input signal IN is a pulse signal, and the pulse enabling periods of the input signal IN and the clock signal CLK1 are the same, while the pulse enabling periods of the clock signals CLK1 and CLK2 are different from each other. When the clock signal CLK1 is at a high potential and the clock signal CLK2 is at a low potential, the shift register needs to use the capacitors 110 and 112 to maintain the gate voltage of the NMOS transistor 104, and then keep the NMOS transistor 104 in an on state, so that When the clock signal CLK2 changes to a high potential, it can be output as the output signal OUT of the circuit.

FIG. 2 is a known structure of a shift register device, which is widely used in liquid crystal screens, for example, a gate driver in a liquid crystal screen adopts this structure. The shift register device in the figure includes shift registers 201˜N+1, and these shift registers all adopt the shift register structure shown in FIG. 1 . In the figure, IN represents an input signal, OUT(1)˜OUT(N) respectively represent output signals of the shift registers 201˜N, and CLKS1 and CLKS2 also represent two different clock signals respectively. As for the IP in each shift register, it is represented as the input terminal of the circuit of FIG. 1 receiving the input signal IN, RP is represented as the input terminal of the circuit of FIG. 1 receiving the reset signal RES, and CK1P is represented as the input terminal of the circuit of FIG. 1 receiving the clock signal CLK1. , and CK2P is shown as the input end of the circuit in Fig. 1 receiving the clock signal CLK2.

A feature of this shift register device is that the reset signal of each stage of shift register is provided by the output signal of its next stage of shift register. Therefore, although the shift register device only needs to provide N output signals, it needs N+1 shift registers to operate.

Can know by above-mentioned, because this kind of shift register device adopts known shift register, and must additionally adopt a shift register to operate, so it has bigger circuit size, makes the manufacturing shift register device jointly Costs are difficult to reduce.

Contents of the invention

The object of the present invention is to provide a kind of shift register device, and it adopts the shift register of the present invention, and it does not need to adopt an extra shift register to operate, so its circuit size can be reduced, and it makes its manufacturing cost can be reduced.

Based on the above and other objectives, the present invention proposes a shift register, which includes an input unit, an output unit, a feedback unit and a reset unit. The input unit is used for receiving the input signal and the first clock signal, and outputting the input signal according to the first clock signal. The output unit is used for receiving the second clock signal and the input signal from the input unit, and outputs the second clock signal to an output terminal according to the input signal. The feedback unit is used for receiving the second clock signal and the input signal from the input unit, and feeding back the signal at the output end to the output unit according to the second clock signal. The reset unit is used for receiving the reset signal, and according to the reset signal, couples the output end to the low potential signal.

Based on the above and other objectives, the present invention proposes a shift register, which includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an input terminal and an output terminal. Each of the aforementioned switches has a first terminal, a second terminal and a control terminal respectively. The input end is connected to the first end of the first switch. The output terminal is connected to the first terminal of the second switch, the first terminal of the fourth switch and the second terminal of the third switch. Wherein the second end of the first switch, the control end of the second switch and the first end of the third switch are connected to each other, the second end of the second switch is connected to the control end of the third switch, and the control end of the first switch is connected to to the control terminal of the fourth switch.

Based on the above and other objectives, the present invention provides a shift register device, which includes a first shift register and a second shift register. The first shift register includes a first input terminal, a first output terminal, a first reset terminal, a first control terminal and a second control terminal. The second shift register includes a second input terminal, a second output terminal, a second reset terminal, a third control terminal and a fourth control terminal. The first output terminal is electrically connected to the second input terminal, the first control terminal and the fourth control terminal are commonly coupled to the first clock signal, and the second control terminal and the third control terminal are commonly coupled to the second clock signal.

According to the shift register according to an embodiment of the present invention, the control terminal of the first switch and the control terminal of the fourth switch are coupled to the first signal, and the second terminal of the second switch is coupled to the control terminal of the third switch second signal. The second terminal of the fourth switch and the second terminal of the fifth switch are coupled to the low potential signal, the first terminal of the fifth switch is connected to the output terminal, and is connected to the first terminal of the second switch and the first terminal of the fourth switch. One end is connected to the second end of the third switch.

According to the shift register according to an embodiment of the present invention, the above-mentioned input signal is a pulse signal, and the pulse signal is the same as the pulse enable period of the first clock signal, and the pulse wave of the first clock signal and the second clock signal The enabling periods are different from each other, and the pulse period of the reset signal is located between the pulse periods of the first clock signal and the second clock signal.

According to the shift register according to an embodiment of the present invention, the above-mentioned reset signal is a first clock signal.

According to the shift register according to an embodiment of the present invention, the above-mentioned input signal is a pulse signal, and the pulse signal is the same as the pulse enabling period of the first signal, and the pulse enabling period of the first signal and the second signal are different from each other, and the pulse period of the reset signal is located between the pulse periods of the first signal and the second signal.

According to the shift register according to an embodiment of the present invention, the above-mentioned reset signal is a first signal.

According to the shift register according to an embodiment of the present invention, the above-mentioned input unit, output unit, feedback unit, and reset unit are selected from the group consisting of a thin film transistor, an NMOS, a PMOS, and a BJT transistor. The same is true for the above-mentioned first switch, second switch, third switch, fourth switch and fifth switch.

According to the shift register device according to an embodiment of the present invention, the above-mentioned first shift register adopts the above-mentioned shift register.

The present invention uses five MOS transistors to make a shift register, and utilizes the parasitic capacitance effect of the MOS transistors to match clock signals different from each other in two pulse periods to achieve the displacement of the input signal. In addition, the shift register device of the present invention adopts a plurality of shift registers of the present invention, and makes the pulse period of the reset signal required by the shift register be located between the pulse periods of the above two different clock signals, or Using one of the clock signals as the reset signal, the shift register device of the present invention only needs to use the same number of shift registers as its output signal, so its circuit size is reduced, and its manufacturing cost is reduced.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a traditional shift register architecture;

Fig. 2 is a known shift register device architecture;

Fig. 3 is a shift register according to a first embodiment of the present invention;

Fig. 4 is each signal sequence diagram of the circuit shown in Fig. 3;

FIG. 5 is a structure of a shift register device according to the present invention;

Fig. 6 is a timing diagram of each signal applied to the circuit shown in Fig. 5 in Fig. 3;

FIG. 7 is a shift register according to a second embodiment of the present invention;

FIG. 8 is a shift register according to a third embodiment of the present invention;

Fig. 9 is each signal sequence diagram of circuit shown in Fig. 7 and Fig. 8;

FIG. 10 is another shift register device architecture according to the present invention.

Detailed ways

FIG. 3 is a shift register according to the first embodiment of the present invention. The shift register includes an input unit 311 , a feedback unit 312 , a reset unit 313 and an output unit 314 . In this embodiment, each unit is composed of at least one switch, for example, the input unit 311 includes the switch 301 , the feedback unit 312 includes the switch 302 , the reset unit 313 includes the switches 303 and 305 , and the output unit 314 includes the switch 304 . The switches 301 - 305 all have a first terminal, a second terminal and a control terminal, and these switches are all determined to be turned on or not according to the signal received by the control terminal.

The first end of the switch 301 of the input unit 311 receives an input signal IN, and the control end thereof receives a clock signal CLK1 (ie, the first signal) to determine whether to transmit the input signal IN to the second end. The first end of the switch 304 of the output unit 314 receives the clock signal CLK2 (i.e. the second signal), the second end outputs an output signal OUT, and its control end is coupled to the second end of the switch 301, so as to determine whether the first The clock signal CLK2 at one end is output to the second end as the output signal OUT. The switch 304 can maintain the voltage of its control end at least until the clock signal CLK2 turns high. The first end of the switch 302 of the feedback unit 312 is coupled to the second end of the switch 301, and its control end receives a clock signal CLK2, so as to determine whether to feed back the output signal OUT connected to the second end to the first end. output unit. The first terminal of the switch 303 of the reset unit 313 is coupled to the second terminal of the switch 302, and the second terminal of the switch 303 is coupled to a low potential signal V _L of the system. In this embodiment, the low potential signal V _L The low potential is not higher than CLK2, and the control terminal receives the clock signal CLK1, so as to determine whether to reset the output signal of the output unit. The first terminal of the switch 305 is coupled to the second terminal of the switch 304 and the first terminal of the switch 303, and its second terminal is also coupled to the low potential signal V _L , and its control terminal receives the reset signal RES. In addition, when the shift register When applied to a driving device of a liquid crystal display, the reset signal RES can be an OE (Output Enable) signal, and the switch 305 determines whether to reset the output signal of the output unit according to the reset signal RES. In addition, when the shift register is applied to a driving device of a liquid crystal display, the low potential signal V _L can be a V _L signal.

In this embodiment, the switches 301 - 305 can be implemented with NMOS transistors, PMOS transistors, thin film transistors, BJT transistors or other electronic switching elements. In addition, the input unit 311, the feedback unit 312, the reset unit 313, and the output unit 314 in this embodiment are not limited to the internal implementation shown in FIG. 3, and each unit can also be composed of multiple switches or any other Implementations may be implemented in other circuit forms that yield the functions described above.

Fig. 4 is a signal sequence control diagram according to the circuit shown in Fig. 3, each signal name in Fig. 4 corresponds to each signal name in Fig. 3 respectively, wherein, the input signal IN is a pulse signal, and this pulse signal and clock signal The pulse enabling period of CLK1 is the same, but the pulse enabling period of the clock signal CLK1 and the clock signal CLK2 are different from each other, and the pulse period of the reset signal RES is located in the pulse period of both the clock signal CLK1 and the clock signal CLK2 between. In other words, the duty cycle of the clock signal CLK1 and the clock signal CLK2 must be less than 50% of the system clock cycle, in this embodiment, the preferred duty cycle of CLK1 and CLK2 is less than 48.5%, so that the pulse of the reset signal RES The pulse period can be located between the pulse periods of the clock signal CLK1 and the clock signal CLK2 . In addition, when CLK1 and CLK2 have the same pulse width, the preferred clock width ratio of the RES signal to CLK1 and CLK2 is less than 0.03, and the best operating timing disclosed in this embodiment is that the pulse width of RES is 1.6 microseconds (us), and the clock signal width of both CLK1 and CLK2 is 63.5 microseconds (us).

Refer to FIG. 3 and FIG. 4 . When the input signal IN and the clock signal CLK1 are at a high potential and the clock signal CLK2 is at a low potential, the switch 301 and the switch 303 are in a conducting state, so the shift register can use the clock signal CLK1 to open the switch 301 to sample the input signal IN , and use the switch 303 to firstly couple the output terminal of the shift register to the low potential terminal V _L of the system to reset the output terminal. The low potential terminal V _L is not higher than the low potential of CLK2. Next, the clock signal CLK1 turns to a low potential, and the reset signal RES turns to a high potential. At this time, the switch 305 is turned on, and the output terminal OUT of the output unit is coupled to the low potential terminal V _L of the system, so as to further reduce the weight. At this time, the clock signal CLK2 continues to maintain a low potential, and the switch 304 uses its own parasitic capacitance to store the charge supplied by the sampled input signal IN, so as to maintain its gate voltage at least until the clock signal CLK2 turns. After being high potential. Since the maintaining time is determined by the size of the transistor used as the switch 304, the size of the transistor used as the switch 304 must be large enough to maintain the on-time of the switch 304 after the clock signal CLK2 turns high.

Next, the clock signal CLK2 turns to a high potential, while the clock signal CLK1 and the reset signal RES both present a low potential, and since the switch 304 is still in a conducting state, the output signal OUT can be output. At the same time, the switch 302 of the feedback unit is also turned on, so the output signal OUT is fed back to the control terminal of the switch 304 of the output unit to ensure that the switch 304 of the output unit can output the output signal OUT completely.

The shift register of the present invention can reduce or avoid the use of passive elements, thereby reducing the size of the circuit. Even, the user can make use of the spare space to make an additional set of shift registers with the same structure. When one of the two sets of shift registers fails to operate normally, the other set of shift registers can be used. to replace.

With the teachings of the above-mentioned embodiments, users can use multiple shift registers as in the first embodiment to construct a shift register device, as shown in FIG. A shift register device made up of stacked bit registers. In Fig. 5, IN is represented as an input signal, OUT(1)~OUT(N) are respectively represented as output signals of shift registers 501~N, and CLKS1 and CLKS2 represent two different clock signals respectively, and an interleaved The way of connection is connected to CK1P and CK2P of each shift register, CK1P is shown as the control terminal of the circuit of FIG. 3 receiving the clock signal CLK1, and CK2P is shown as the control terminal of the circuit of FIG. 3 receiving the clock signal CLK2. IP in each shift register is indicated as the input terminal of the input unit in FIG. 3 receiving the input signal IN, and RP is indicated as the reset terminal of the reset unit in FIG. 3 receiving the reset signal RES. Therefore, when the input signal IN to the (N-1)th shift register is a high potential, and the timing signals different from CLKS1 and CLKS2 are combined, after a clock signal time is delayed, it will be output at the OUT(N-1) A high potential signal, and the OUT(N-1) signal also becomes the input signal of the Nth shift register, and then the OUT(N-1) will be reset back to a low potential signal by the RES signal. In the same way, when the input signal IN to the (N)th shift register is a high potential, after a delay of one clock signal time, a high potential signal will be output at the OUT(N), and then the OUT(N) will be It will be reset back to a low level signal by the RES signal.

FIG. 6 is a timing diagram of signals in the circuit shown in FIG. 5 , and the names of the signals in FIG. 6 correspond to the names of the signals in FIG. 5 . As mentioned in the aforementioned article, the duty cycles of the clock signal CLKS1 and the clock signal CLKS2 must be less than 50% of the system clock cycle, so that the pulse period of the reset signal RES can be located at the pulse of both the clock signal CLKS1 and the clock signal CLKS2. Between waves, and it can be seen from Figure 5 that each stage of shift register uses the same RES reset signal. In this way, an N-stage shift register device only needs N shift registers, and the N+1-th stage shift register is no longer needed to provide the N-stage reset signal. Therefore, the shift register device of the present invention only needs N shift registers to operate.

With the teaching of the relevant description in Figure 3, after appropriately modifying the circuit shown in Figure 3, other types of shift registers can also be changed, which can also perform signal shift operations without using the reset signal RES, as shown in the figure 7. FIG. 7 is a shift register according to a second embodiment of the present invention. Comparing the circuits shown in Figure 3 and Figure 7, it can be clearly found that the circuit in Figure 7 only changes the signal received by the control terminal of the switch 305 in Figure 3, that is, the original reset signal RES is changed to the clock signal CLK1 to form a Reset unit 714 .

In addition, Fig. 8 shows the shift register of the third embodiment of the present invention. Comparing the circuits shown in FIG. 7 and FIG. 8, it can be clearly found that the circuit in FIG. 8 simplifies the reset unit 714 in the circuit in FIG. Since the circuits shown in Fig. 7 and Fig. 8 only use the clock signal CLK1 to reset their output terminals, these two circuits only need to use the clock signals CLK1 and CLK2 to perform signal displacement. The second and third embodiments also illustrate that the reset signal RES can be different signals. Similarly, according to the flexible use of the reset signal RES in the above-mentioned embodiments, in other embodiments, the control terminals of the switch 305 and the switch 705 in the reset unit of the first and second embodiments of the present invention can also be Another reset signal is coupled, not limited to the clock signal CLK1 , wherein the pulse enable period of the other reset signal can be designed to be the same as that of the clock signal CLK1 . FIG. 9 is a timing diagram of each signal in the circuits shown in FIG. 7 and FIG. 8 , and the names of the signals in FIG. 9 correspond to the names of the signals in FIG. 7 and FIG. 8 respectively.

With the teaching of the circuit shown in FIG. 7 and FIG. 8 above, the user can use a plurality of shift registers shown in FIG. 7 or 8 to construct a shift register device, as shown in FIG. 10 . The shift register device in FIG. 10 includes shift registers 1001~K, and these shift registers all adopt the shift register structure shown in FIG. 7 or FIG. 8 . In the figure, IN represents the input signal, OUT(1)~OUT(K) represent the output signals of the shift registers 1001~K respectively, and CLKS1 and CLKS2 respectively represent two different clock signals. As for IP in each shift register, it is represented as the input end of the circuit shown in FIG. 7 or 8 receiving the input signal IN, CK1P is represented as the control terminal of the circuit shown in FIG. 7 or 8 receiving the clock signal CLK1, and CK2P is represented as The circuit shown in FIG. 7 or FIG. 8 receives the control terminal of the clock signal CLK2, and CLKS1 and CLKS2 are connected to CK1P and CK2P of each shift register in an interleaved manner.

As shown in Figure 10, when an input signal IN to the (K-1)th shift register is at a high potential, coupled with timing signals different from CLKS1 and CLKS2, after a delay of one clock signal time, the shift register at the OUT ( K-1) outputs a high potential signal, and the OUT(K-1) signal also becomes the input signal of the Nth shift register, and then the OUT(K-1) will be reset back to low by the CLKS1 signal potential signal. In the same way, when the input signal IN to the (K)th shift register is a high potential, after a delay of one clock signal time, a high potential signal will also be output at the OUT (K), and then the OUT (K) will be Will be reset back to a low level signal by the CLKS2 signal.

In each of the above-mentioned embodiments, the main feature of the shift register of the present invention has been described as having an input unit, an output unit, a reset unit and a feedback unit, and it has also been described that multiple sets of shift registers having this feature A shift register device composed of registers, this shift register device has the characteristics of an interleaved CLKS1 and CLKS2 connection mode and a RES reset signal. In other embodiments, CLKS1 can even be used as the source of the reset signal RES and can be Achieve the function of the displacement of the input signal. In addition, because the present invention can reduce or avoid the use of passive components, the circuit size and area occupied by the circuit can be reduced, and the yield rate can be improved due to the simplification of the components used.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the disclosed embodiments, but should include various alternatives and modifications that do not depart from the present invention, and are covered by the appended claims.

Claims (14)

1. A shift register, comprising: An input unit is used to receive an input signal and a first clock signal, and output the input signal according to the first clock signal; an output unit for receiving a second clock signal and receiving the input signal from the input unit, and outputting the second clock signal to an output terminal according to the input signal; a feedback unit for receiving the second clock signal and the input signal from the input unit, and feeding back the signal at the output end to the output unit according to the second clock signal; and A reset unit is used for receiving a reset signal and coupling the output end to a low potential signal according to the reset signal. 2. The shift register as claimed in claim 1, wherein each of the input unit, the output unit, the feedback unit and the reset unit comprises a first terminal, a second terminal and a control terminal respectively, and the The input unit, the output unit, the feedback unit and the reset unit respectively determine whether to conduct according to the signal received by the control terminal. 3. The shift register as claimed in claim 1, wherein the first terminal of the input unit is coupled to the input signal, the second terminal of the input unit is coupled to the control terminal of the output unit, and the control terminal of the input unit is The first clock signal is received. 4. The shift register as claimed in claim 1, wherein the first terminal of the output unit is coupled to the second clock signal, the second terminal of the output unit is coupled to the output terminal, and the control terminal of the output unit is coupled to Connect to the second terminal of the input unit. 5. The shift register as claimed in claim 1, wherein the first end of the feedback unit is coupled to the output of the output unit, and the second end of the feedback unit is coupled to the second end of the input unit and the output The control terminal of the feedback unit is coupled to the second clock signal. 6. The shift register as claimed in claim 1, wherein the first terminal of the reset unit is coupled to the output terminal, the second terminal of the reset unit is coupled to the low potential signal, and the control of the reset unit The terminal is coupled to the reset signal. 7. The shift register as claimed in claim 6, wherein a control terminal of the reset unit receives the reset signal, thereby coupling the output terminal to the low potential signal. 8. The shift register as claimed in claim 1, wherein the input signal is a pulse signal, the pulse signal is the same as the pulse enable period of the first clock signal, and the first clock signal is the same as the second clock signal The pulse enabling periods of the signals are different from each other, and the pulse period of the reset signal is located between the pulse periods of the first clock signal and the second clock signal. 9. The shift register as claimed in claim 1, wherein the input unit, the output unit, the feedback unit and the reset unit are selected from the group consisting of a thin film transistor, an NMOS and a PMOS, BJT transistor Group. 10. A shift register comprising: a first switch, a second switch, a third switch, a fourth switch and a fifth switch, each of which has a first terminal, a second terminal and a control terminal; an input terminal connected to the first terminal of the first switch; and an output terminal connected to the first terminal of the second switch, the first terminal of the fourth switch and the second terminal of the third switch, wherein the second terminal of the first switch and the control terminal of the second switch The first terminal of the third switch is connected to each other, the second terminal of the second switch is connected to the control terminal of the third switch, and the control terminal of the first switch is connected to the control terminal of the fourth switch. 11. The shift register as claimed in claim 10, wherein the control terminal of the first switch and the control terminal of the fourth switch are coupled to a first signal, and the second terminal of the second switch is connected to the third switch The control terminal is coupled to a second signal. 12. The shift register as claimed in claim 10, wherein the second terminal of the fourth switch and the second terminal of the fifth switch are coupled to a low potential signal, and the first terminal of the fifth switch is connected to the The output terminal is connected to the first terminal of the second switch, the first terminal of the fourth switch and the second terminal of the third switch. 13. A shift register device, comprising: A first shift register, including a first input terminal, a first output terminal, a first reset terminal, a first control terminal and a second control terminal; and A second shift register, including a second input terminal, a second output terminal, a second reset terminal, a third control terminal and a fourth control terminal, Wherein the first output terminal is electrically connected to the second input terminal, the first control terminal and the fourth control terminal are commonly coupled to a first clock signal, and the second control terminal and the third control terminal are commonly coupled to a Second clock signal. 14. The shift register device as claimed in claim 13, wherein the first shift register comprises: An input unit is used to receive an input signal and a first clock signal, and output the input signal according to the first clock signal; an output unit for receiving a second clock signal and receiving the input signal from the input unit, and outputting the second clock signal to an output terminal according to the input signal; a feedback unit for receiving the second clock signal and the input signal from the input unit, and feeding back the signal at the output end to the output unit according to the second clock signal; and A reset unit is used for receiving a reset signal and coupling the output end to a low potential signal according to the reset signal.

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