CN101281330A - Liquid crystal display and display panel thereof - Google Patents

Abstract

The invention discloses a liquid crystal display and a display panel thereof. The display panel comprises a plurality of pixel column units and a plurality of level switching units. Each pixel column unit is connected in series between a scanning line and a level switching line. The first end of each switching unit is used for receiving the common voltage of the display panel, and the second end of each switching unit is electrically connected to the corresponding horizontal switching line. Therefore, the invention not only reduces the flicker noise of the display panel, but also improves the picture quality of the liquid crystal display.

Description

Liquid crystal display and its display panel

technical field

The present invention relates to a liquid crystal display and its display panel, and in particular to a liquid crystal display and its display panel which utilize pixel row units to selectively receive a common voltage.

Background technique

Liquid crystal display (Liquid Crystal Display, LCD) has been widely used recently, and replaces cathode ray tube display (Cathode Ray Tube, CRT) as one of the mainstreams of next-generation displays. With the improvement of semiconductor technology, large-size liquid crystal displays are born one after another, but another technical bottleneck arises, that is, as the size of the display panel increases, the problem of screen flickering becomes more and more serious.

The structure of the pixel unit in the traditional display panel is divided into two types, one is the structural schematic diagram of the pixel unit 100 shown in FIG. 1 , and the other is the structural schematic diagram of the pixel unit 200 shown in FIG. 2 . Referring to FIG. 1 and FIG. 2 together, the pixel units 100 and 200 each include a thin film transistor 101 , a liquid crystal capacitor C _LC , a storage capacitor C _S , and a parasitic capacitor C _gd . The biggest difference is that the pixel unit 100 is designed with the storage capacitor _CS on the common voltage (common voltage, Vcom) (CS on common), while the pixel unit 200 is designed with the storage capacitor _CS on the scan line G _m-1 Design (Cs on gate).

Regardless of which of the above pixel units is used, when the gate signal SG output by the gate driver (gate driver, not shown) drops from the high level V _H to the low level V _L rapidly, the thin film transistor 101 is turned off. When , the coupling effect (coupling effect) caused by the parasitic capacitance C _gd will cause the drain terminal voltage V _D of the thin film transistor 101 to drop by a voltage difference ΔV _FT , as shown in formula (1):

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; FT</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; LC</span>}}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GP</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Where ΔV _GP =V _H -V _L , and the varying voltage difference ΔV _FT is called feed-through voltage. It can be known from the formula (1) that because the feed-through voltage ΔV _FT of the pixel units in the traditional display panel is not the same, it will cause flicker noise of the display panel, which will aggravate the flickering of the picture presented by the liquid crystal display .

In order to alleviate the screen flickering derived from the above-mentioned feedthrough effect, related technologies have been correspondingly developed, including:

1. Adjust the common voltage provided to the display panel according to the value of the feed-through voltage ΔV _FT .

2. Use the driving technology of 3-level or 4-level gate signal.

FIG. 3 is a simulated waveform diagram of the related art 1 mentioned above. It is applicable to the pixel unit 100 disclosed above, please refer to FIG. 1 and FIG. 3 in combination. When the gate signal SG is at a high level V _H , the thin film transistor 101 is turned on. At this time, the source voltage V _S transmitted through the data line SL will be stored on the liquid crystal capacitor C _LC , so that the level of the drain terminal voltage V _D changes to the level of the source voltage V _S. However, when the gate signal SG drops rapidly from the high level V _H to the low level V _L , the level of the drain terminal voltage V _D will drop by the value of the feed-through voltage ΔV _FT . In order to eliminate the screen flicker caused by the feed-through voltage ΔV _FT , the related art 1 adjusts the common voltage Vcom of the display panel to an optimal common voltage V'com.

However, in related art 1, when adjusting the common voltage Vcom, complicated manual measurements must be performed first to find the optimum common voltage V'com provided to the display panel. In addition, the characteristics of each display panel are different, so the above-mentioned optimal common voltage V'com may not completely match each display panel.

FIG. 4 is a simulation waveform diagram of the related art 2 above. It is applicable to the pixel unit 200 disclosed above, please refer to FIG. 2 and FIG. 4 in combination. When the level of the drain terminal voltage V _D drops by a value of the feed-through voltage ΔV _FT , related technology 2 uses the compensation voltage V _P provided by the gate signal SG _m-1 and SG _m during the low-level period, causing the drain terminal voltage The level of V _D is charged in stages to the level of the source voltage V _S .

However, the compensation voltage V _P provided by the related art 2 can be calculated according to a theoretical formula. But in practical applications, the gate signal SG is generated by a gate driver in the liquid crystal display. Therefore, while improving the accuracy of the compensation voltage _VP , it must be exchanged by increasing the design complexity of the gate driver. In this way, when the related art 2 eliminates the screen flickering displayed by the liquid crystal display, it also increases the design complexity of the gate driver, which leads to more layout area and power consumption of the liquid crystal display.

Contents of the invention

The object of the present invention is to provide a display panel, which utilizes a switching unit to control the time point when the pixel column unit receives the common voltage of the display panel. Thus, compared with the prior art, the display panel of the present invention can eliminate the feedthrough effect on the display without changing the common voltage of the display panel and without increasing the circuit complexity of the gate driver. panel impact.

Another object of the present invention is to provide a liquid crystal display, which can be used in the liquid crystal display of the present invention according to the spirit of the above-mentioned display panel of the present invention, thereby not only achieving the advantages of the above-mentioned display panel of the present invention, but also enabling Reduce the flickering noise of the display panel, so as to improve the picture quality presented by the liquid crystal display.

To achieve the above or other objectives, the present invention provides a display panel suitable for liquid crystal displays. The display panel includes a plurality of pixel column units and a plurality of switching units. Each pixel row unit is connected in series between a scanning line and a level switching line, and the first end of each switching unit is used to receive the common voltage of the display panel, and the second end of each switching unit is electrically Connect to level switch line. In this way, each switching unit turns on its first end and second end before its corresponding gate signal goes high, so that its corresponding pixel row unit receives the common voltage from the display panel. In addition, each switching unit disconnects its first end and second end before its corresponding gate signal goes low, so that its corresponding pixel row unit is switched to a floating state.

In an embodiment of the present invention, each pixel row unit includes N pixel units, and the N pixel units are in one-to-one correspondence with N data lines, and N is an integer greater than 0. Each pixel unit includes a first switch and a storage circuit. The first switch is used to determine whether the corresponding data line is electrically connected to the storage circuit. The storage circuit is used to determine the display gray scale of the display panel.

It should be noted that the storage circuit includes at least one liquid crystal capacitor, and the first switch is a thin film transistor. In addition, the data line is electrically connected to the source driver of the liquid crystal display.

In an embodiment of the present invention, each switching unit includes at least one switch. And the gate driver of the liquid crystal display generates the above gate signals and a plurality of level switching signals, and each switching unit determines the conduction state of its first terminal and the second terminal according to its corresponding level switching signal.

From another point of view, the present invention provides a liquid crystal display including a display panel, a plurality of switching units, and a driving unit. Wherein the display panel includes at least a plurality of pixel column units, each pixel column unit is connected in series between a scanning line and a level switching line, and the first end of each switching unit is used to receive the common voltage of the display panel, each A second end of a switching unit is electrically connected to the level switching line. In this way, each switching unit turns on its first end and second end before its corresponding gate signal goes high, so that its corresponding pixel row unit receives the common voltage from the display panel. In addition, each switching unit disconnects its first end and second end before its corresponding gate signal goes low, so that its corresponding pixel column unit switches to a floating state. The driving unit is used to drive the display panel.

In an embodiment of the present invention, the driving unit includes a gate driver and a source driver. The gate driver is used to generate the above-mentioned gate signals, and the source driver is used to generate the source voltage required to drive the pixel row unit.

In the liquid crystal display and its display panel provided by the present invention, the time point at which the pixel column units receive the common voltage of the display panel is controlled by the switching unit. Therefore, the present invention not only reduces the flickering noise of the display panel, but also improves the picture quality presented by the liquid crystal display.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are exemplified below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic structural diagram of a pixel unit of a conventional display panel.

FIG. 2 is a schematic structural diagram of another pixel unit of a conventional display panel.

FIG. 3 is a simulation waveform diagram of the related art 1 mentioned above.

FIG. 4 is a simulation waveform diagram of the related art 2 above.

FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a simulated waveform of the embodiment in FIG. 5 .

FIG. 7A is a partial structural view of the embodiment of FIG. 5 .

FIG. 7B is a working principle diagram of the pixel unit _PI1 .

FIG. 8 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present invention.

Detailed ways

The main technical feature of the present invention is that the pixel row unit selectively receives the common voltage from the display panel under the conduction state of both ends of the switching unit, thereby eliminating the flicker noise caused by the feedthrough effect. The display panel and liquid crystal display of the present invention will be illustrated below, but they are not intended to limit the present invention. Those skilled in the art can slightly modify the following embodiments according to the spirit of the present invention, but they still belong to the scope of the present invention.

FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention. For the convenience of illustration, FIG. 5 further shows the source driver 502 and the gate driver 503 . Referring to FIG. 5 , the display panel 501 includes a plurality of pixel column units and a plurality of switching units. In order to clearly show each component, FIG. 5 only shows the pixel column units 510 and 520 and the switching units 530 and 540 here. The pixel column unit 510 is connected in series between the scanning line _GL1 and the level switching line _CL1 . The pixel column unit 520 is connected in series between the scanning line GL ₂ and the level switching line CL ₂ . The first end of the switching unit 530 is used to receive the common voltage Vcom of the display panel 501 , and the second end of the switching unit 530 is electrically connected to the level switching line CL ₁ . In addition, the first end of the switching unit 540 is used to receive the common voltage Vcom of the display panel 501 , and the second end of the switching unit 540 is electrically connected to the level switching line CL ₂ .

To further illustrate, the pixel column unit 510 includes N pixel units PI ₁ -P _N . N pixel units PI ₁ ˜P _N correspond one-to-one to N data lines SL ₁ ˜SL _N , and N is an integer greater than 0. In addition, each of the pixel units PI ₁ -P _N includes a switch, a storage circuit, and a parasitic capacitor. It should be noted that the switches of each of the pixel units PI ₁ -P _N include a thin film transistor, and the storage circuit includes at least a liquid crystal capacitor.

For example, the pixel unit PI ₁ includes a switch SW ₅₁ , a storage circuit (liquid crystal capacitor C ₅₁ ), and a parasitic capacitor C _gd1 . The first end of the switch SW ₅₁ is electrically connected to the corresponding data line SL ₁ , and the control end of the switch SW ₅₁ is electrically connected to the scan line GL ₁ . The storage circuit (liquid crystal capacitor C ₅₁ ) is connected in series between the second end of the switch SW ₅₁ and the level switching line CL ₁ . The parasitic capacitor C _gd1 is electrically connected to the scan line GL ₁ and the second terminal of the switch SW ₅₁ .

Similarly, the pixel unit PI ₂ includes a switch SW ₅₂ , a storage circuit (liquid crystal capacitor C ₅₂ ), and a parasitic capacitor C _gd2 . The first end of the switch SW ₅₂ is electrically connected to the corresponding data line SL ₂ , and the control end of the switch SW ₅₂ is electrically connected to the scan line GL ₁ . The storage circuit (liquid crystal capacitor C ₅₂ ) is connected in series between the second end of the switch SW ₅₂ and the level switching line CL ₁ . The parasitic capacitor C _gd2 is electrically connected to the scan line _GL1 and the second terminal of the switch _SW52 . The detailed structures of the pixel units PI ₃ ˜P _N are deduced by analogy, which will not be repeated here.

On the other hand, the detailed structure of the above-mentioned pixel column unit 520 is similar to that of the pixel column unit 510 . The pixel column unit 520 includes N pixel units PII ₁ -PII _N . The N pixel units PII ₁ -PII _N are also in one-to-one correspondence with the N data lines SL ₁ -SL _N. In addition, each of the pixel units PII ₁ -PII _N includes a switch, a storage circuit, and a parasitic capacitor. Similarly, the switches of each of the pixel units PII ₁ -PII _N include a thin film transistor, and the storage circuit includes at least a liquid crystal capacitor.

For example, the pixel unit PII ₁ includes a switch SW ₅₃ , a storage circuit (liquid crystal capacitor C ₅₃ ), and a parasitic capacitor C _gd3 . The first end of the switch SW ₅₃ is electrically connected to the corresponding data line SL ₁ , and the control end of the switch SW ₅₃ is electrically connected to the scan line GL ₂ . The storage circuit (liquid crystal capacitor C ₅₃ ) is connected in series between the second end of the switch SW ₅₃ and the level switching line CL ₂ . The parasitic capacitor C _gd3 is electrically connected to the scan line GL ₂ and the second terminal of the switch SW ₅₃ .

Similarly, the pixel unit PII ₂ includes a switch SW ₅₄ , a storage circuit (liquid crystal capacitor C ₅₄ ), and a parasitic capacitor C _gd4 . The first end of the switch SW ₅₄ is electrically connected to the corresponding data line SL ₂ , and the control end of the switch SW ₅₄ is electrically connected to the scan line GL ₂ . The storage circuit (liquid crystal capacitor C ₅₄ ) is connected in series between the second end of the switch SW ₅₄ and the level switching line CL ₂ . The parasitic capacitor C _gd4 is electrically connected to the scan line GL ₂ and the second terminal of the switch SW ₅₄ . The detailed structure of the pixel units PII ₃ ˜PII _N can be deduced by analogy, which will not be repeated here.

Before entering the interoperability mechanism between the pixel column units 510-520 and the switching units 530-540, it must be understood that the display panel 501 is suitable for a liquid crystal display (not shown here), and the source driver 502 and the gate driver 503 It is the component covered by the liquid crystal display. The source driver 502 is electrically connected to the data lines SL ₁ -SL _N , and the gate driver 503 is electrically connected to the scan lines GL ₁ and GL ₂ . Here, the source driver 502 is used to generate source voltages VS ₁ -V _N required to drive the pixel column units 510 and 520 . The gate driver 503 is used for generating the gate signals SG ₁ and SG _N required to switch the pixel column units 510 and 520 .

FIG. 6 is a diagram illustrating a simulated waveform of the embodiment in FIG. 5 . For the convenience of illustration, the pixel column unit 510 and the switching unit 530 are taken as an example, and are shown as shown in FIG. 7A , and FIG. 7A further indicates the node voltages VD ₁ and VC ₁ . Please refer to FIG. 6 and FIG. 7A , the pixel unit PI ₁ receives the gate signal SG ₁ through the scan line GL ₁ , and receives the source voltage VS ₁ through the data line SL ₁ . The switching unit 530 determines the conduction state of its first terminal and the second terminal according to a level switching signal SC ₁ , and the level switching signal SC ₁ can be provided by the gate driver 503, or other devices according to design requirements. Components are provided. It should be noted that the switching unit 530 includes at least one switch SW ₅₅ .

Before the gate signal SG ₁ is switched from the low level V _L to the high level V _H , that is, before the gate signal SG ₁ turns high, the switching unit 530 will switch according to the level switching signal SC ₁ (such as logic 1). Conducting the first end and the second end thereof. Therefore, when the gate signal SG ₁ is at the high level V _H , the second end of the storage circuit (the liquid crystal capacitor C ₅₁ ) is electrically connected to the common voltage Vcom, and the level of the node voltage VC ₁ also changes to the common voltage Vcom accordingly. The level of the voltage Vcom. At the same time, due to the turn-on of the switch _SW51 , the source voltage _VS1 charges the storage circuit (liquid crystal capacitor _C51 ), causing the level of the node voltage _VD1 to change to the level of the source voltage _VS1 .

Before the gate signal _SG1 is switched from a high level _VH to a low level _VL , that is, before the gate signal _SG1 turns low, the switching unit 530 will switch the signal _SC1 according to the level (such as logic 0). And disconnect its first end and second end. At this time, referring to _the working principle diagram _of the pixel unit PI ₁ shown in FIG. When the pole signal SG ₁ switches from the high level V _H to the low level V _L , the voltage difference ΔV _GP formed by the gate signal SG ₁ will be stored in the liquid crystal capacitor C ₅₁ and the parasitic capacitor C _gd1 respectively according to the voltage division theorem . In other words, the level of the node voltage _VD1 will change at this time, and correspondingly, the amount of charge stored in the storage circuit (liquid crystal capacitor C ₅₁ ) will also change accordingly, wherein the variation of the node voltage _VD1 is ΔVD ₁ =ΔV _GP *C _gd1 /(C _gd1 +C ₅₁ ).

In contrast to the implementation of this embodiment, when the gate signal _SG1 is switched from the high level V _H to the low level V _L , since the second terminal of the storage circuit (liquid crystal capacitor C ₅₁ ) is in a floating state Therefore, based on the principle of charge conservation, the levels of the node voltages VD ₁ and VC ₁ at this time will drop by a voltage difference ΔV _GP (as shown in FIG. 6 ). In this way, the amount of charge stored in the storage circuit (the liquid crystal capacitor C ₅₁ ) does not change before and after the low transition of the gate signal SG ₁ . In other words, the pixel unit 510 will not change the display grayscale of the display panel 501 due to the feed-through effect.

The other pixel units PI ₂ ˜P _N in the pixel column unit 510 also cooperate with the control of the switching unit 530 to receive the common voltage Vcom before the high transition of the gate signal SG ₁ and switch before the low transition of the gate signal SG ₁ to the floating state. In this way, an operation mechanism similar to that of the pixel unit _PI1 is achieved, thereby eliminating the flickering noise of the display panel 501 .

Continuing to refer to FIG. 5 , the mutual operation mechanism of the pixel row unit 520 and the switching unit 540 is similar to the mutual operation mechanism of the above-mentioned pixel row unit 510 and the switching unit 530 . Here, the switching unit 540 also determines the conduction state of its first terminal and the second terminal according to a level switching signal SC ₂ , and the level switching signal SC ₂ can be provided by the gate driver 503 , or can be determined according to design requirements. provided by other components. It should be noted that the switching unit 540 includes at least one switch SW ₅₆ .

Under the control of the level switching signal SC ₂ , the switching unit 540 causes the pixel units PII ₂ to PII _N to receive the common voltage Vcom before the high transition of the gate signal SG ₂ , and switch to Vcom before the low transition of the gate signal SG ₂ floating state. In this way, before and after the low transition of the gate signal SG ₂ , the feedthrough effect caused by the parasitic capacitances (such as C _gd3 , C _gd4 ) will not change the value stored in the storage circuit (such as the liquid crystal capacitances C ₅₃ , C ₅₄ ) in the amount of charge. By analogy, it can be deduced that any pixel column unit in the display panel 501 can eliminate the flicker noise caused by the feed-through effect under the control of the corresponding switching unit.

FIG. 8 is a schematic structural diagram of a liquid crystal display according to an embodiment of the present invention. Referring to FIG. 8, a liquid crystal display 800 includes a display panel 801, a driving unit 802, and a plurality of switching units. The display panel 801 includes a plurality of pixel column units. In order to clearly represent each component, only the switching units 803 and 804 and the pixel column units 810 and 820 are shown here. Since the embodiment in FIG. 8 is an extension of the embodiment in FIG. 5 , each pixel row unit in the display panel 801 is structurally the same as the pixel row unit in the embodiment in FIG. 5 , and details are not repeated here.

However, the biggest difference between the display panel 801 and the display panel 501 is that no switching unit is configured in the display panel 801 . However, in order to achieve the effect of the display panel 501, the embodiment in FIG. 8 uses multiple switching units (such as switching units 803 and 804) configured outside the display panel 801 to execute multiple switching units (such as switching units 530 and 804) in the display panel 501. 540) has the function.

Therefore, the overall architecture of the embodiment in FIG. 8 is similar to that in the embodiment in FIG. 5 . The pixel column unit 810 is connected in series between the scanning line _GL1 and the level switching line _CL1 . The pixel column unit 820 is connected in series between the scanning line GL ₂ and the level switching line CL ₂ . The first end of the switching unit 803 is used to receive the common voltage Vcom, and the second end of the switching unit 803 is electrically connected to the level switching line CL ₁ . The first end of the switching unit 804 is used to receive the common voltage Vcom, and the second end of the switching unit 804 is electrically connected to the level switching line CL ₂ . In addition, the driving unit 802 is electrically connected to the display panel 801 .

To further illustrate, the driving unit 802 includes a source driver 830 and a gate driver 840 . The source driver 830 is electrically connected to the data lines SL ₁ ˜SL _N , and the gate driver 840 is electrically connected to the scan lines GL ₁ and GL ₂ . It should be noted that each switching unit in the liquid crystal display 800 includes at least one switch. For example, the switching unit 803 includes a switch SW ₈₁ , and the switching unit 804 includes a switch SW ₈₂ .

Continuing to refer to FIG. 8 , the source driver 830 is used to generate source voltages VS ₁ ˜V _N required to drive the pixel column units 810 and 820 . The gate driver 840 is used for generating the gate signals SG ₁ and SG ₂ required for switching the pixel column units 810 and 820 . In addition, the switching units 803 and 804 determine the conduction states of the first end and the second end of the switching units 803 and 804 respectively according to the level switching signals SC ₁ and SC ₂ . The level switching signals SC ₁ and SC ₂ can be provided by the gate driver 840 , or provided by other components according to design requirements.

Before the gate signal _SG1 is switched from low level to high level, that is, before the gate signal _SG1 is in a high state, the switching unit 803 will conduct the first end and the second end of the switching unit 803 according to the level switching signal _SC1 . end. Here, the pixel column unit 810 receives the source voltages VS ₁ -V _N from the source driver 830 with the common voltage Vcom as a reference point.

However, before the gate signal _SG1 switches from high level to low level, that is, before the gate signal _SG1 turns low, the switching unit 803 will disconnect its first terminal according to the level switching signal _SC1 with the second end. Here, since the pixel row unit 810 is switched to a floating state, the flicker noise caused by the feedthrough effect will be suppressed. By analogy, the mutual operation mechanism of the pixel column unit 820 and the switching unit 804 is described. As for other details of this embodiment, the above-mentioned embodiments have been covered, and no further description is given here.

To sum up, the present invention utilizes the switching unit to control the time point when the pixel row unit receives the common voltage. In this way, before and after the low transition of the gate signal, the display gray scale of the display panel will not be affected by the feedthrough effect. In other words, the present invention can not only reduce the flickering noise of the display panel, but also improve the picture quality presented by the liquid crystal display.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (17)

1. A display panel, suitable for a liquid crystal display, the display panel comprising: A plurality of pixel row units, each of which is connected in series between a scanning line and a level switching line, and receives a gate signal through its corresponding scanning line; and A plurality of switching units respectively have a first end and a second end, the first end of each of the switching units is used to receive the common voltage of the display panel, the second end of each of the switching units is electrically is connected to its corresponding level switching line, and each of these switching units conducts its first end and second end before its corresponding gate signal high transition, and the corresponding gate The first terminal and the second terminal are disconnected before the signal low transition. 2. The display panel according to claim 1, wherein each of the pixel row units comprises N pixel units, and the N pixel units correspond to the N data lines one-to-one, and N is an integer greater than 0, Each pixel unit includes: A first switch has a first end, a second end and a control end, the first end is electrically connected to the corresponding data line, and the control end is electrically connected to the corresponding scan line; and A storage circuit is connected in series between the second end of the first switch and the corresponding level switching line, and is used to determine the display gray scale of the display panel. 3. The display panel as claimed in claim 2, wherein the storage circuit comprises at least one liquid crystal capacitor. 4. The display panel as claimed in claim 2, wherein the first switch is a thin film transistor. 5. The display panel according to claim 2, wherein each pixel unit further comprises: A parasitic capacitor is electrically connected to the corresponding scan line and the second end of the first switch. 6. The display panel as claimed in claim 2, wherein the data lines are electrically connected to a source driver of the liquid crystal display. 7. The display panel as claimed in claim 1, wherein the scan lines are electrically connected to a gate driver of the liquid crystal display. 8. The display panel as claimed in claim 1 , wherein each switching unit comprises at least one switch. 9. The display panel according to claim 7, wherein the gate driver of the liquid crystal display generates the gate signals and a plurality of level switching signals, and each of the switching units is based on its corresponding voltage The conduction state of the first end and the second end is determined by switching the signal at level. 10. A liquid crystal display, comprising: A display panel, at least including: A plurality of pixel row units, each pixel row unit is connected in series between a scanning line and a level switching line, and receives a gate signal through its corresponding scanning line; A plurality of switching units respectively have a first end and a second end, the first end of each of the switching units is used to receive the common voltage of the display panel, the second end of each of the switching units is electrically is connected to its corresponding level switching line, and each of these switching units conducts the first terminal and the second terminal before the high transition of its corresponding gate signal, and the corresponding gate disconnecting the first terminal and the second terminal before the low signal transition; and A driving unit is electrically connected to the display panel for driving the display panel. 11. The liquid crystal display as claimed in claim 10, wherein the drive unit comprises: a gate driver, electrically connected to the scan lines, for generating the gate signals; and A source driver is used to generate the source voltages required to drive the pixel column units. 12. The liquid crystal display as claimed in claim 11, wherein the gate driver also generates a plurality of level switching signals, and each of the switching units determines the first terminal according to its corresponding level switching signal and the conduction state of the second terminal. 13. The liquid crystal display as claimed in claim 10, wherein each of the pixel column units comprises N pixel units, and the N pixel units correspond to the N data lines one-to-one, and N is an integer greater than 0, Each pixel unit includes: A first switch has a first end, a second end and a control end, the first end is electrically connected to the corresponding data line, and the control end is electrically connected to the corresponding gate line; and A storage circuit is connected in series between the second end of the first switch and the corresponding level switching line, and is used to determine the display gray scale of the display panel. 14. The liquid crystal display as claimed in claim 13, wherein the storage circuit comprises at least one liquid crystal capacitor. 15. The liquid crystal display as claimed in claim 13, wherein the first switch is a thin film transistor. 16. The liquid crystal display as claimed in claim 13, wherein each pixel unit further comprises: A parasitic capacitor is electrically connected to the corresponding scan line and the second end of the first switch. 17. The liquid crystal display as claimed in claim 10, wherein each switching unit comprises at least one switch.

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