CN101263607A - Drain Extended MOSFET with Diode Clamp - Google Patents

Abstract

A MOS driver transistor (T2) with a high-side extended drain is described, wherein the extended drains (108, 156) are separated from the first buried layer (120) by a second buried layer (130) in which An internal or external diode (148) is coupled between a buried layer (120) and the extended drain (108, 156) to increase breakdown voltage.

Description

Drain Extended MOSFET with Diode Clamp

technical field

[001] The present invention relates generally to semiconductor devices and, more particularly, to extended drain MOS transistor devices and processing methods for making the same.

Background technique

[002] For high-power switching applications, power semiconductor products generally use drain-extended metal-oxide-semiconductor (DEMOS) transistor devices of N-type or P-type channels, such as laterally diffused MOS (LDMOS) devices or simplified surface field (RESURF) transistors are processed. DEMOS devices advantageously combine short channel operation with high current handling capability, relatively low drain-source on-resistance (Rdson), and the ability to withstand high blocking voltages without voltage breakdown failure. The breakdown voltage is generally measured as the drain-to-source breakdown voltage (BVdss) with the gate and source shorted together, where DEMOS device designs often involve a voltage between the breakdown voltage BVdss and Rdson Make a compromise. In addition to performance advantages, DEMOS device processing is relatively easy to integrate into a CMOS process flow for use in devices that also process logic circuits, low-power analog circuits, or other circuits within a single integrated circuit (IC).

[003] N-channel drain extension transistors (DENMOS) are asymmetric devices typically formed in an n-well with a p-well (eg, sometimes referred to as a p-type body) formed in the n-well. An n-type source is formed within the p-well providing a p-type channel region between the source and the extended n-type drain. The extended drain generally includes an n-type drain implanted into the n-well and a drift region extending between the channel region and the drain within the n-well. Low n-type doping on the drain side provides a large depletion layer with high blocking voltage capability, where the p-well is typically connected to the source by a p-type backgate connection to prevent the p-well from floating, thereby stabilizing the device threshold (Vt ). A device drain region is isolated from a channel (eg, an extended channel) to provide a drift region or drain extension in the n-type semiconductor material therebetween. In operation, the separation between the drain and channel extends beyond the electric field, increasing the breakdown voltage rating of the device (higher BVdss). However, the expansion of the drain increases the resistance (Rdson) of the drain-source current path, so the design of DEMOS devices often involves a compromise between high breakdown voltage BVdss and low Rdson.

[004] DEMOS devices have been widely used in power switching applications requiring high blocking voltage and high current carrying capability, especially for driving solenoids or other inductive loads. In a common configuration, two or four n-channel DEMOS devices are arranged as a half "H-bridge" circuit or a full "H-bridge" circuit to drive a load. In a half H-bridge arrangement, two DEMOS transistors are coupled in series between the power supply VCC and ground, while the load is coupled to ground from the middle node between the two transistors. In this configuration, the transistor between the middle node and ground is called the "low-side" transistor, and the other transistor is called the "high-side" transistor, where the two transistors are alternately active to supply current to the load. In a full H-bridge drive circuit, two high-side drivers and two low-side drivers are provided, with a load coupled between two intermediate nodes.

[005] In operation, the high-side DEMOS has a drain coupled to a power supply and a source coupled to a load. In the "on" state, the high-side driver conducts current from the source to the load, where the source is effectively pulled up to the supply voltage. A typical DEMOS device is fabricated on a wafer with a p-type doped silicon substrate, on which an epitaxial silicon layer is formed, wherein the substrate is grounded and transistor sources, drains, and trenches are formed in the epitaxial silicon layer channels (eg, including n-wells and p-wells). Therefore, in the on-state of the high-side DEMOS device, the p-well surrounding the source needs to be separated from the grounded underlying p-type substrate to prevent punch-through current between the p-well and the substrate. Although n-wells can extend under p-wells, n-wells are generally only lightly doped and thus do not provide an adequate barrier to on-state punch-through current from source to substrate. Therefore, a heavily doped n-type buried layer (e.g., NBL) is sometimes formed in the substrate prior to forming the epitaxial silicon layer to isolate the n-well from the substrate and thus inhibit p-well On-state feedthrough current to the substrate. The n-type buried layer can be connected to the drain terminal of these high-side DEMOS devices through a deep diffusion or sinker, and thus tie it to the supply voltage in order to prevent or suppress on-state punch-through current.

[006] Although the n-type buried layer prevents on-state shoot-through current, NBL limits the off-state breakdown voltage rating of the high-side DEMOS driver. In the "off" state, the source of the high-side driver is actually pulled down to ground while the low-side driver is turned on, and the drain-source voltage across the high-side DEMOS is actually the supply voltage VCC. In high voltage switching applications, the presence of an n-type buried layer under the p-well limits the drain-source breakdown of the device because the n-type buried layer is tied to the drain at VCC. In this case, the p-well is grounded, since the source is low in the off state, and the supply voltage VCC is actually lowered as it passes through the n-well portion extending beyond the bottom of the p-well and the n-type buried layer between, and between the channel side of the p-well and the drain. Also, since the high-side driver is turned off when driving an inductive load, the transient drain-source voltage can increase above the supply level VCC.

[007] In these cases, the lateral spacing between the drain and p-well can be adjusted to prevent breakdown from the p-well to the drain. However, the vertical separation from the bottom of the p-well to the n-type buried layer is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer. However, this is expensive in terms of process complexity, especially if deep diffusions are formed to connect the n-type buried layer to the drain. Therefore, there is a need for improved DEMOS devices and processing methods by which increased voltage breakdown withstand capability can be achieved without increasing the thickness of the epitaxial silicon layer and without sacrificing device performance.

Contents of the invention

[008] The present invention relates to n-channel or p-channel drain extended MOS (DEMOS) transistors and fabrication methods wherein the extended drain is separated from the first buried layer and coupled thereto by an internal or external diode. The present invention helps to increase the breakdown voltage operation of high-side drivers and other DEMOS devices without requiring a thicker epitaxial silicon layer and will not adversely affect Rdson, thereby making minimal changes to the existing process flow, and can An increased drive operating voltage is achieved. The first buried layer may be isolated from the extended drain by a second buried layer having an opposite conductivity type and formed prior to epitaxial growth. Diodes can be formed separately in the epitaxial layer to form a connection from the anode to the first buried layer and from the cathode to the extended drain in the interconnect layer or metallization layer, or to form external connections to couple the external diode to the between the first buried layer and the extended drain.

Description of drawings

1 is a schematic diagram illustrating a full H-bridge circuit device utilizing two pairs of low-side and high-side drain-extended NMOS devices to drive a load, in which one or more aspects of the present invention may be implemented;

[010] FIG. 2A is a partial side elevation view illustrating a cross-section of a conventional high-side DENMOS transistor;

[011] FIG. 2B is a side elevational view of the conventional high-side transistor of FIG. 2A illustrating the equipotential voltage lines in the drift region in the off state and the region prone to breakdown at high drain-source voltages;

[012] FIG. 3 is a partial side elevational view of a region illustrating an exemplary high-side DENMOS transistor with features isolating the extended drain from the underlying n-type buried layer in accordance with one or more aspects of the present invention. an open p-type buried layer, and a diode clamp coupling the n-type buried layer and the extended drain together;

[013] FIG. 3B is a side elevational view of the exemplary high-side DENMOS transistor of FIG. 3A illustrating equipotential voltage lines in the drift region in the off state;

[014] FIG. 3C is a graph illustrating drain current (Id) versus drain-source voltage (Vds) illustrating comparative breakdown voltage performance for the high-side DENMOS driver transistors of FIGS. 2A and 3A ;

[015] FIG. 4 is a flowchart illustrating an exemplary method of fabricating a semiconductor device and a high-side DENMOS driver transistor in accordance with the present invention;

[016] FIGS. 5A-5H are partial side elevational views of portions illustrating an exemplary embodiment of the high-side DENMOS driver transistor of FIG. Internal diodes together, the figure generally shows the various stages of processing according to the method of Figure 4;

[017] FIGS. 6A-6D are partial side elevational views of portions illustrating another possible implementation of the high-side DENMOS driver transistor of FIG. An external connection to couple external diodes between the poles, the figure generally shows the various stages of processing according to the method of Figure 4;

6E is a top plan view illustrating a single-chip implementation of the full H-bridge circuit device of FIG. 1 with external diode connections in accordance with the present invention; and

[019] FIG. 6F is a top plan view illustrating an embodiment of a single high-side driver transistor with external connections for external diodes in accordance with the present invention.

Detailed ways

[020] The present invention provides improved DEMOS transistors and methods of fabrication whereby high breakdown voltage ratings can be achieved without increasing the thickness of the epitaxial silicon layer, wherein the buried layer is diode-coupled to the extended drain. The present invention finds particular utility in high-side driver transistor applications for full-bridge or half-bridge circuits, although the transistors and methods of the present invention are not limited to these applications. Various aspects of the present invention will be illustrated and described below by taking an NMOS driver transistor as an example, although a PMOS implementation is also feasible, as long as the p-type doped region is replaced with an n-type doped region, and vice versa. Furthermore, while the following exemplary devices are formed using a semiconductor body having a silicon substrate and an overlying epitaxial silicon layer, other semiconductor bodies may be utilized including, but not limited to, standard semiconductor wafers, SOI wafers, etc., all of which vary Both embodiments are considered to be within the scope of the invention and the appended claims.

[021] FIG. 1 illustrates a full H-bridge driver semiconductor device 102 powered by a DC supply voltage VCC, in which various aspects of the present invention may be implemented. As shown and described further below with respect to FIG. 6E , semiconductor device 102 can be constructed as a single IC 102a with four driver transistors T1-T4 and external connections for power supply, gate signal, and load terminals, and optionally Ground provides connections for external diodes for the high-side drivers T2 and/or T3. Figure 6F illustrates another possible device 102b in which a single high side driver is provided in an IC with external connections for drain, source, gate, back gate and optional anode connections. The invention may alternatively be applied in other integrated circuits having any number of components in which extended drain MOS transistors with high breakdown voltage are required.

[022] As shown in FIG. 1, the exemplary device 102 includes four n-channel drain extended MOS (DENMOS) devices T1-T4, which have corresponding sources S1-S4, drains D1-D4, and gates, respectively. G1-G4, and are coupled in an H-bridge to drive a load coupled between intermediate nodes N1 and N2. Transistors T1-T4 are arranged as two pairs of low-side and high-side drivers (T1 & T2 and T4 & T3), with the load coupled between the intermediate nodes of the two pairs of low-side and high-side drivers, thereby forming an "H-shaped" circuit. A half-bridge driver circuit can be implemented with transistors T1 and T2, while node N2 on the right-hand side of the load is coupled to ground, where T3 and T4 can be ignored. In one example, for automotive applications, portable electronics, etc., the supply voltage VCC may be the positive terminal of a battery power supply, and ground may be the negative terminal of the battery.

[023] On the left side of the H-bridge of FIG. 1, a low-side driver T1 and a high-side driver T2 are coupled in series between a supply voltage VCC and ground, while another pair T4 and T3 are connected in a similar manner. The high-side driver transistor T2 has a drain D2 coupled to VCC and a source S2 coupled to the intermediate node N1 at the load. The low-side transistor T1 has a drain D1 coupled to a node N1 and a source S1 coupled to ground. A node N1 between transistors T1 and T2 is coupled to a first terminal of a load, and another load terminal N2 is coupled to another transistor pair T3 and T4 , where the load is generally not part of device 102 . The high-side and low-side transistor gates G1-G4 are controlled to drive the load in an alternating manner. When transistors T2 and T4 are on, current flows in a first direction (to the right in Figure 1) through high-side transistor T2 and the load, and when transistors T3 and T1 are both on, current flows in a second, opposite direction through the load and low-side transistor T1.

[024] In order to evaluate one or more shortcomings of conventional DEMOS transistors in applications such as the H bridge in Figure 1, Figures 2A and 2B illustrate a semiconductor device 2 with a conventional high-side DENMOS transistor 3, wherein Figure 2B The equipotential voltage lines in the drift region of the high-side driver 3 in the OFF state are shown in order to illustrate its breakdown voltage limit. In the following a conventional high-side driver transistor 3 is briefly described for the purpose of evaluating the possible advantages of the invention by taking an H-bridge driver circuit as an example, where a DENMOS transistor 3 can be coupled to drive a load in a full-bridge or half-bridge driver circuit configuration, T2 in the H-bridge circuit shown in Figure 1.

[025] As shown in FIG. 2A, the device 2 includes a p-type doped silicon substrate 4 on which an epitaxial silicon layer 6 is formed. An n-type buried layer (NBL) 20 is located in the substrate 4 below the high-side device 3 and extends locally into the epitaxial silicon layer 6 . The n-well 8 is implanted into the epitaxial silicon layer 6 above the n-type buried layer 20 by n-type dopants, and a p-well or p-base 18 is formed in the n-well 8 . Field oxide (FOX) isolation structures 34 are formed in the upper portion of the epitaxial silicon layer 6 between the transistor device terminals of the low-side and high-side transistors 1 and 3 . A p-type back gate 52 and an n-type source 54 are formed in the p-well 18 , and an n-type drain 56 is formed in the n-well 8 . Over the channel portion of the p-well 18 is formed a gate structure comprising a gate oxide 40 and a gate electrode 42, where the gate G2, source S2 and drain D2 of a conventional high-side DENMOS transistor 3 are labeled as are coupled to form a half or full H bridge in Figure 1 for illustration above.

[026] In this driver application, the high side device drain 56 is connected to the supply voltage VCC and the source 54 is coupled to the load at the intermediate node N1. When high-side transistor 3 is turned on, both source 54 and drain 56 are at or near supply voltage VCC, where n-type buried layer 20 helps prevent punch-through current between p-well 18 and grounded p-type substrate 4 flow, where n-type buried layer 20 is tied to drain 56 (eg, to VCC). However, when the high-side transistor 3 is turned off, the source 54 is actually pulled down to ground by the low-side transistor, whereby the drain-source voltage across the high-side DENMOS 3 is actually the supply voltage VCC. Furthermore, when switching from the on-state to the off-state, the high-side driver 3 experiences a transient drain-source voltage greater than VCC if the load is inductive. Figure 2B illustrates the equipotential voltage lines in the drift region of the n-well 8 within the high-side transistor 3 in the off state. At these high drain-source voltage levels, high electric fields are generated in regions 21 and 22 where the equipotential lines are closely spaced, where the high side driver 3 shown in Figure 2 is at Vds just below the breakdown level.

[027] The present inventors have realized that since at least part of the n-type buried layer 20 is located under the n-well 8, these regions 21 and 22 are prone to breakdown at higher supply voltages in the high-side driver OFF state, where shown The breakdown voltage BVdss of traditional DENMOS 3 is relatively low. Therefore, although the n-type buried layer 20 suppresses the on-state punch-through current from the p-well 18 to the substrate 4, the off-state breakdown voltage BVdss of the high-side driver 3 is limited by the presence of the NBL 20. In this regard, the inventors have realized that the presence of the n-type buried layer 20 at drain potential (VCC) leads to the equipotential line clustering in FIG. 2B at high drain-source voltage levels, especially in FIG. In areas 21 and 22 in 2B. In the absence of a design change, the supply voltage VCC cannot be increased without risking an off state or a momentary voltage breakdown. One method is to reduce the doping concentration of the n-well 8 to improve the breakdown voltage performance. However, this approach adversely affects the on-state drive current by increasing Rdson. Another method is to increase the thickness of the epitaxial silicon layer 6 . However, as mentioned above, processing a thicker epitaxial layer 6 leads to process complications and beyond a certain value may not be feasible.

[028] The present invention provides DEMOS transistors that readily improve breakdown voltage ratings without increasing Rdson or epitaxial silicon layer thickness. The present invention thus facilitates the use of these devices in new applications requiring higher supply voltages, including but not limited to full or half H-bridge configurations as shown in Figure 1, while avoiding or mitigating the need for drain-extended MOS devices. The usual compromise between Rdson and BVdss, and no significant changes to the existing process flow. 3A-3C illustrate an exemplary DENMOS high-side driver transistor T2 in the H-bridge drive device 102 of FIG. A diode 148 is coupled between the n-type buried layer 120 and the drain to increase the breakdown voltage without increasing the epitaxial thickness. Although illustrated as an example of a DENMOS high-side driver formed in a semiconductor body having a silicon substrate and an overlying epitaxial silicon layer, other implementations are possible within the scope of the invention, for example, PMOS implementations, utilizing Other semiconductor body structure processed devices, other drain extended MOS transistors (eg, RESURF devices, etc.) and/or unused transistors in high side driver applications. Furthermore, as described above, diode 148 may be integrated into device 102 or may be external.

[029] As shown in FIG. 3A, a device 102 is formed in a semiconductor body comprising a p-type doped silicon substrate 104 and an epitaxial silicon layer 106 formed on the substrate 104. Before forming the epitaxial silicon layer 106, an n-type buried layer (NBL) 120 is formed (eg, implanted and diffused) in the substrate 104 under its intended high-side driver region, where the n-type buried A p-type buried layer (PBL) 130 is formed (e.g., implanted) over the layer, thereby placing the p-type buried layer 130 between the n-type buried layer 120 and the overlying high-side DENMOS transistor T2, wherein the epitaxial silicon layer Some of the implanted p-type dopants of the p-type buried layer 130 diffuse upward into the epitaxial silicon layer 106 during growth and/or during subsequent processing steps that provide thermal energy to the device 102 . In addition, the p-type buried layer 130 prevents or inhibits the upward diffusion of n-type dopants of the n-type buried layer 120 during such heat treatment.

[030] The transistor T2 also includes an n-well 108 implanted in the epitaxial silicon layer 106 using an n-type dopant (for example, arsenic, phosphorus, etc.), and a p-well or a p-base 118 formed in the n-well 108, and at the same time A field oxide (FOX) structure 134 is formed on top of the epitaxial silicon layer 106 between the transistor source, drain and back gate terminals. Other implementations are possible, for example, the back gate can be directly connected to the source, or the isolation structure can be formed using shallow trench isolation (STI) technology, deposited oxide, etc., wherein all these alternative implementations make the first buried Layer (for example, NBL 120) is isolated from the DEMOS by a second buried layer of opposite conductivity type (for example, PBL 130), while coupling a diode (for example, diode 148) between the two, these schemes are considered to fall within the scope of the invention and the appended claims.

[031] The transistor T2 comprises a p-type back gate 152 and an n-type source 154 formed in the p-well 118, and an n-type drain 156 formed in the n-well, wherein the part between the drain 150 and the p-well 118 The n-well 108 provides the drain extension or drift region. Thus, transistor T3 includes an extended drain that includes the drift region of n-well 108 and drain 156 . In operation, back gate 152 may, but need not be, be coupled to source 154 in an overlying metallization layer (not shown). In one possible alternative implementation, the field oxide (FOX) structure 134 between the back gate 152 and the source 154 may be omitted for the direct connection of the back gate 152 to the source 154 . A gate structure is formed over the channel portion of the p-well 118 and a portion of the drift region of the n-well 108, the gate structure including a gate oxide 140 and a gate electrode 142, wherein a portion of the gate electrode 142 is further embedded in exemplary transistor T2. The drain extension of the well 108 or field oxide structure 134 above the drift region is extended.

[032] In a half-H-bridge or full-H-bridge load driver configuration, the drain 156 is connected to the supply voltage VCC along with the cathode of the internal or external diode 148, while the source 154 is coupled to the middle node in FIG. on the load at N1. In the on-state of the high-side DENMOS transistor T2, the source 154 is pulled up close to the supply voltage VCC, where the n-type buried layer 120 helps prevent punch-through current flow between the p-well 118 and the grounded p-type substrate 104 . In the OFF state, the majority of the supply voltage VCC is present between the drain 156 and the source 154 . However, instead of coupling the n-type buried layer (e.g., NBL 20 in FIG. Isolated from the extended drain (eg, from the drain 156 and the drift region of the n-well 108 ), where the diode 148 is coupled between the n-type buried layer 120 and the extended drain. Therefore, the off-state potential of the n-type buried layer 120 is lower than VCC.

[033] The lower n-type buried layer potential and the presence of intervening p-type buried layers lead to a much different electric field distribution in the device in the off state compared to that in conventional high-side drivers. FIG. 3B illustrates the high-side device T2 at a high drain-source voltage about 60% higher than that of FIG. 2B above without voltage breakdown, where the n-type buried layer 120 is at At lower voltages at drain 156 , part of the supply voltage appears across diode 148 . In this example, the design parameters (eg, size, doping concentration, etc.) of the exemplary high-side DENMOS transistor T2 are almost the same as the conventional device 3 in FIG. 2A , except that the p-type buried layer 130 and diode 148 are added. Thus, the addition of p-type buried layer 130 and a diode coupling n-type buried layer 120 to the extended drain enables operation at higher supply voltages VCC without experiencing off-state voltage breakdown, where BVdss is significantly increased without The thickness of the epitaxial silicon layer was not increased, and Rdson was not changed.

[034] FIG. 3C provides a graph illustrating the relationship between drain current (Id) and drain-source voltage (Vds) for curves 162 and 164, which correspond to the conventional high-side DENMOS 3 of FIG. 2A and FIG. 3A, respectively. An exemplary high-side DEMOS transistor T2. It can be seen from Figure 160 that the transistor T3 of Figure 3A can safely operate at a much higher voltage without breakdown, where the corresponding BVdss 164 is more than 60 higher than the BVdss 162 of the traditional high-side DENMOS 3 of Figure 2A %. Thus, the isolation between the n-type buried layer 120 and the extended drains 156, 108 and the coupling of the diode 148 between the two provide significantly higher breakdown voltages, allowing the use of higher supply voltages VCC without Increasing the thickness of the epitaxial silicon layer 106 does not have a significant adverse effect on Rdson.

[035] In a preferred embodiment, the doping concentration of the n-type buried layer 120 is higher than that of the p-type buried layer 130, so that when the n-well 108 is depleted between the p-well 118 and the p-type buried layer 130 , the on-state punch-through current is suppressed from flowing between the p-well 118 and the p-type substrate 104 . In one example, the p-type buried layer 130 has a maximum doping concentration greater than or equal to about 5E15 cm ⁻³ and less than or equal to about 5E17 cm ⁻³ , wherein the n-type buried layer 120 has a maximum doping concentration of greater than or equal to about 1E17 cm ⁻³ and less than or equal to about 1E20 cm ⁻³ The maximum doping concentration of the n-type buried layer is higher than the maximum concentration of the p-type buried layer 130 .

[036] Another aspect of the present invention provides methods for semiconductor device processing that can be used to process devices having NMOS and/or PMOS extended drain transistors with improved breakdown voltage performance. In this aspect of the invention, a first buried layer of a first conductivity type is implanted in the substrate, followed by a second buried layer of a second conductivity type. An epitaxial silicon layer is formed over the implanted substrate, and a drain extended MOS transistor is formed over the second buried layer in the epitaxial silicon layer, wherein the extended drain of the transistor is separated from the first buried layer. The method may include forming a diode in the epitaxial layer to couple the first buried layer to the extended drain, or forming an external connection to the first buried layer and the extended drain to couple an external diode therebetween.

[037] FIG. 4 illustrates an exemplary method 202 for processing semiconductor devices and DEMOS transistors in accordance with this aspect of the invention, while FIGS. 5A-5H generally follow the method 202 diagram of FIG. An exemplary semiconductor device 102 is shown illustrating various stages of processing. 6A-6D illustrate the fabrication of another embodiment of the device 102 and method 202 in which connections for the external diode 148 are provided. Other methods of the present invention can be utilized to form PMOS devices in which p-type dopants are replaced with n-type dopants and vice versa. Furthermore, the method 202 can be utilized to form devices with internal diodes for coupling the first buried layer to the extended drains of the DEMOS transistors and/or to produce devices with externally available connections, These externally available connections are used to couple external diodes between the first buried layer and the extended drain, wherein all such alternative embodiments are considered to be within the scope of the invention and appended claims.

[038] Although the exemplary method 202 is illustrated and described below as a series of acts or events, it should be appreciated that the invention is not limited to the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events than those shown and/or described herein in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the invention. Furthermore, methods in accordance with the present invention may be implemented in conjunction with device processing shown and described herein as well as with other devices and structures not shown.

[039] The method 202 begins at 204 in FIG. In the exemplary semiconductor device 102, an n-type buried layer 120 is provided for the high-side device T2 in the driver region 112, which may also be implanted elsewhere in the device 102, including a separate n-type buried layer in the diode region 111 120a. In FIG. 5A, device 102 is illustrated with NBL implant mask 302 formed over portions of silicon substrate 104 to expose a portion of the upper surface of substrate 104 in the intended high-side driver region 112, while A portion of the intended inner diode region 111 is covered. Implantation process 304 is performed by placing mask 302 appropriately to implant n-type dopants (e.g., arsenic, phosphorus, etc.) into exposed portions of substrate 104, thereby forming n-type buried layer 120 (e.g., having a first buried layer of the first conductivity type) and a separate n-type buried layer 120 a is formed in the diode region 111 . A diffusion anneal (not shown) may optionally be performed at step 208 to drive the n-type dopants deeper into the substrate 104 so that the n-type buried layer 120, 120a is downward and laterally outward from the initial implanted region. expand.

[040] At 210 in FIG. 4, a second buried layer having a second conductivity type (eg, p-type buried layer 130 in device 102), which may optionally be diffused at 212, is implanted. In FIG. 5B, a mask 312 is formed, which exposes a portion of the n-type buried layer 120 at the intended high-side region 112, and an implantation process 314 is performed to provide p-type dopants (eg, boron, etc.) to the substrate 104. in the exposed part. As shown in Figure 5B, an exemplary p-type buried layer 130 in the high-side region 112 is located within the n-type buried layer 120 of the device 102, where another diffusion anneal can optionally be performed at 212 to allow lateral and downward drive The implanted p-type dopant expands the p-type buried layer 130 .

[041] At 214 in FIG. 4, an epitaxial growth process is performed to grow the epitaxial silicon layer 106 on the substrate 104. Any suitable epitaxial growth process that forms epitaxial silicon layer 106 on the upper surface of substrate 104 may be utilized at 214 . In FIG. 5C, epitaxial silicon layer 106 is formed on substrate 104 by process 322, wherein thermal energy associated with epitaxial growth process 322 causes a portion of the p-type dopant of p-type buried layer 130 to diffuse upwards, thereby partially burying the p-type Layer 130 extends into epitaxial silicon layer 106 . Similarly, the end portion of the n-type buried layer 120 diffuses upwards into the epitaxial silicon layer 106 outside the high-side driver region 112 , and the n-type buried layer 120 a of the diode region also diffuses upwards into the epitaxial silicon layer 106 . However, during and after the epitaxial process 322 at 214, the p-type buried layer 130 generally prevents or inhibits the upward diffusion of at least a portion of the n-type buried layer 120 in the high-side driver region 112, and in the n-type buried layer 120 and subsequently A physical barrier is provided between the formed DEMOS extended drain (eg, drain 156 and n-well 108 in FIG. 3A ).

[042] At 216, an n-well is implanted in the epitaxial silicon layer 106 in the high-side region 112, and then at 218 the n-well may be thermally diffused. Before or after forming the n-well at 216 , a deep n-type diffusion (eg, implanted region) is formed in the epitaxial silicon layer 106 to provide a connection to the n-type buried layer 120 . In FIGS. 5D and 6A, a mask 324 is formed on the epitaxial silicon layer 106, and an n-type implant 326 and a thermal diffusion anneal (not shown) are performed simultaneously to create an n-type implanted region 107 into the n-type buried layer 120 in region 111. connect. A mask 332 is formed in FIGS. 5E and 6B that exposes all or a portion of the intended high-side driver region 112, and an implant 334 is performed to create n-wells 108 therein (e.g., n-wells 108a-108c and n-well 108 in FIG. 6B). In the case where internal diode 148 is to be formed in device 102, mask 332 exposes two parts of diode region 111 as shown in FIG. Cathode n-wells 108a and 108c of layer 120a, and also create DEMOS n-well 108b in high-side driver region 112, after which a thermal diffusion anneal may be performed at 218.

[043] At 220, the p-well or p-base region 118 is implanted into a portion of the transistor n-well 108, after which another thermal diffusion anneal (not shown) may be performed. 5F illustrates the case of internal diode 148, where mask 342 is formed to expose the intended p-well region of epitaxial layer 106 in DEMOS n-well 108b and in diode region 112 between n-wells 108a and 108c. Implantation process 344 is then performed to create anode p-well 118a, thereby creating inner diode 148 in epitaxial layer 106, and transistor p-well 118b, where n-well 108b extends into p-well 118b between p-well 118b and p-type buried layer 130 Down. In this configuration, n-wells 108a and 108c and n-type buried layer 120a of the diode region are used to isolate diode p-well 118a from the remainder of epitaxial layer 106 and from p-substrate 104 . FIG. 6C illustrates the use of external diode 148 where a single p-well 118 is created in transistor n-well 108 with mask 342 covering region 111 . It is within the scope of the present invention to utilize any suitable implantation process to form the buried layers 120, 130 and wells 108, 118, while selectively performing a dedicated diffusion anneal after any, all, or none of the implants, with all of these variations implementing Both ways are considered to fall within the scope of the present invention.

[044] At 222 in FIG. 4, isolation structures 134 are formed using any suitable technique, such as local oxidation of silicon (LOCOS), shallow trench isolation (STI), deposited oxide, and the like. In exemplary device 102, as shown in FIG. 5G, field oxide (FOX) structures 134 are formed for diode region 111 and high-side region 112, respectively. As shown in FIGS. 5H and 6D , a thin gate oxide 140 is formed on the top surface of the device (eg, at 224 in method 202 ) by, for example, a thermal oxidation process, and is formed over the thin gate oxide 140 at 226. A gate polysilicon layer 142 is deposited. Gate oxide 140 and polysilicon 142 are patterned at 228 to form a gate structure extending over the channel region of p-well 118b in FIG. 5H (p-well 118 in FIG. 6D ).

[045] After forming the patterned gate structure, LDD and/or MDD implants may be performed and sidewall spacers formed at 230 along lateral sidewalls of the patterned gate structure. At 232, source region 154 and drain region 156 are implanted with n-type dopants, and at 234, back gate 152 is implanted with p-type dopants, wherein any suitable masking and implantation process may be used to form n type source 154 and drain 156 and p-type back gate 152 . Silicide, metallization and other back-end processing are then performed at 236 and 238, respectively, so that the first pre-metal dielectric (PMD) over the gate 142, source 154, drain 156 and back gate 152 of DEMOS transistor T2 A conductive metal suicide material 172 and conductive contact plugs 178 (eg, tungsten, etc.) are grown in layer 174 and, in the case of internal diode 148 (FIG. 5H), over p-type anode 118a and n-type cathode 118a.

[046] Further metallization layers (not shown) are then formed at 240 to create a multi-level interconnect wiring structure, after which method 202 in FIG. 4 ends. As schematically shown in Figure 5H, in the case of an internal diode, the n-type buried layer 120 is coupled to the anode p-well 118a through the n-type implant region 107 and the conductive contact plug 178 above the implant region 107 and the anode 118a, and then can The n-type buried layer 120 is connected into the overlying metallization layer. As shown in FIG. 6D , when using external diode 148 , an external anode connection from metallization wiring is provided to connect diode 148 to n-type buried layer 120 and an external drain connection from D2 is provided to connect to the cathode of diode 148 .

[047] FIGS. 6E and 6F illustrate two possible completed semiconductor devices 102a and 102b, respectively, that provide external connections for the anode and cathode of an external diode 148, respectively. FIG. 6E illustrates an exemplary single-chip implementation 102a of the full H-bridge circuit device of FIG. 1 with external diode connections for driving DEMOS transistors T2 and T3 on the high side, respectively, in accordance with the present invention. Diodes 148a and 148b are coupled between the n-type buried layer 120 (anode) and the extended drain (cathode). FIG. 6F illustrates another exemplary device 102b that includes a single high-side driver transistor (eg, T2) with features for coupling an external diode 148 between the n-type buried layer 120 and the drain 156. external anode connection.

[048] While the invention has been illustrated and described in terms of one or more implementations, changes and/or modifications may be made to the illustrated examples without departing from the scope of the invention.

Claims (14)

1. A drain extended MOS transistor comprising: a source having a first conductivity type formed in the semiconductor body; a drain of said first conductivity type laterally isolated in said semiconductor body from said source; a drift region of said first conductivity type located between said drain and said source in said semiconductor body; a channel region of a second conductivity type extending between said drift region and said source in said semiconductor body, wherein said drift region extends between said channel region and said drain between; a gate overlying the channel region; a first buried layer with the first conductivity type, which is located under the source, the channel region and the drift region, the first buried layer is connected to the drift region and the drain separated; and A diode having an anode coupled to the first buried layer and a cathode coupled to at least one of the drift region and the drain. 2. The transistor of claim 1 , further comprising a second buried layer of the second conductivity type underlying the source, the channel region, and the drift region, wherein the A second buried layer separates the first buried layer from the drain and the drift region, and wherein the diode is separated from the second buried layer. 3. The transistor according to claim 2, wherein said semiconductor base comprises a silicon substrate and an epitaxial silicon layer formed on said silicon substrate, wherein said source, said drain, said channel region and the drift region are located in the epitaxial silicon layer, and wherein at least a portion of the second buried layer is located in the silicon substrate. 4. The transistor of claim 3, wherein the diode is formed in the epitaxial silicon layer. 5. The transistor of claim 2, wherein the first buried layer underlies at least a portion of the second buried layer. 6. The transistor of claim 2, comprising a first well of said first conductivity type extending in said semiconductor body beneath said source, said drain and said channel , wherein the second buried layer is located under the first well. 7. The transistor of claim 6, comprising a second well of the second conductivity type within the first well, the second well extending beyond the source and the gate Below, part of the first well extends between the second well and the second buried layer. 8. The transistor of claim 1, wherein the diode is formed in the semiconductor body. 9. The transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. 10. The transistor of claim 1 or 2, wherein the transistor comprises a drain extended MOS transistor. 11. A method of processing a semiconductor device, the method comprising: providing a silicon substrate; Implanting a first buried layer with a first conductivity type into the silicon substrate; Implanting a second buried layer having a second conductivity type into the silicon substrate; forming an epitaxial silicon layer on the silicon substrate after implanting the second buried layer; and An extended-drain MOS transistor is formed on the second buried layer in the epitaxial silicon layer, the extended-drain MOS transistor includes an extended drain of the first conductivity type, and the extended drain is connected to the extended drain. The first buried layer is separated. 12. The method of claim 11 , further comprising forming an external connection to the first buried layer and the extended drain for coupling between the first buried layer and the extended drain. Connect external diodes. 13. The method of claim 11, further comprising: forming a diode in the epitaxial silicon layer, the diode comprising an anode and a cathode; coupling the anode to the first buried layer; and The cathode is coupled to the extended drain. 14. The method of claim 11, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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