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CN101263547A - 具有低电感的半导体半桥模块 - Google Patents

具有低电感的半导体半桥模块 Download PDF

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Publication number
CN101263547A
CN101263547A CNA2006800219224A CN200680021922A CN101263547A CN 101263547 A CN101263547 A CN 101263547A CN A2006800219224 A CNA2006800219224 A CN A2006800219224A CN 200680021922 A CN200680021922 A CN 200680021922A CN 101263547 A CN101263547 A CN 101263547A
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China
Prior art keywords
bus
substrate
power semiconductor
module according
semiconductor switch
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威廉·格朗特
黑尼·利恩
杰克·马尔钦科夫斯基
韦利米尔·内迪克
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Publication of CN101263547A publication Critical patent/CN101263547A/zh
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Abstract

一种功率模块，其包括被设置成降低寄生电感的嵌入的输出总线和电源汇流条。

Description

具有低电感的半导体半桥模块
相关申请
本申请基于2005年6月24日提交的、序列号为60/193678且标题为“Semiconductor Switch Half-Bridge Module with Low Inductance”的美国临时申请并要求其权益，在此要求其优先权，其内容通过引用结合于此。
技术领域
本发明涉及功率模块，更具体地，本发明涉及半桥功率模块。
背景技术
众所周知，功率模块(如半导体半桥模块)可以用于功率应用，如功率转换和/或功率供给中。常规的模块是通过利用引线接合(WireBond)等将半导体晶片组装并连接到用于外部连接的导线框架(lead frame)和端子来构造的。晶片通常安装在传导性的金属层上，该金属层接合到非传导性的衬底上，而导线框架通常被插入模制到塑料外壳中。因而，电流通过引线接合、衬底的金属层和导线框架来传送。从外部可接入的导电端子使得可以将模块连接到外部电路，但是标准DC端子常常离得很远，而且呈现高寄生电感。
在全开关模式的功率转换应用中，使寄生电感最小化是非常重要的。如果寄生电感没有最小化，则瞬态电压会过冲，并且半导体晶片的损耗会增加，从而有效地降低半导体镜片能够处理的功率量。
发明内容
根据本发明的功率模块包括：框架；第一总线，可连接到电源的一极，并且嵌入在框架内；第二总线，可连接到电源的另一极，并且嵌入在框架内；输出总线，嵌入在框架内，并且与第一和第二汇流条垂直隔开而相对设置；以及功率电路，包括高侧功率半导体开关和低侧功率半导体开关，所述高侧功率半导体开关电连接到第一总线和输出总线，而所述低侧功率半导体开关电连接到第二总线和输出总线。
在优选实施例中，框架由适合的塑料模制而成。
根据本发明的模块进一步包括：与框架集成在一起的第一衬底和与框架集成在一起的第二衬底，其中高侧功率半导体开关设置在第一衬底上，而低侧功率半导体开关设置在第二衬底上。优选地，第一衬底被设置在第一总线、第二总线和输出总线一侧，而第二衬底被设置在第一总线、第二总线和输出总线一侧，并且与第一衬底相对，由此第一总线、第二总线和输出总线设置在第一衬底和第二衬底之间。
在优选实施例中，第一衬底包括用于所有高侧开关的公共栅极轨(gate track)，而第二衬底包括用于所有低侧开关的公共栅极轨。而且，第一衬底包括用于所有高侧开关的发射极感测轨(sense track)，而第二衬底包括用于所有低侧开关的发射极感测轨。此外，高侧开关共用第一衬底上的公共集电极接合垫(pad)，而低侧开关共用第二衬底上的公共集电极接合垫。
根据本发明的模块还包括：电连接到第一衬底上的公共集电极接合垫的集电极感测导线(sense lead)、电连接到第二衬底上的公共集电极接合垫的集电极感测导线、与框架集成在一起的高侧功率半导体开关的多个高侧I/O导线和与框架集成在一起的低侧功率半导体开关的多个低侧I/O导线，其中I/O导线包括温度感测导线、集电极感测导线、发射极感测导线和栅极导线。
根据以下参考附图的对本发明的说明，本发明的其它特征和优点将变得清楚。
附图说明
图1示出根据本发明优选实施例的一个半桥电路。
图2A示出根据本发明的一个功率模块中的外壳设置的俯视图。
图2B示出沿着线2B-2B以箭头的方向所看到的外壳设置的截面图。
图3示出根据优选实施例的一个功率模块的俯视图。
具体实施方式
参考图1，根据本发明优选实施例的一个功率模块：包括单相半桥电路10，该单相半桥电路10优选地包括：四个并联连接的高侧MOS栅半导体开关Qh1、Qh2、Qh3、Qh4；和多个并联连接的低侧MOS栅半导体开关QI1、QI2、QI3、QI4。注意，最好将功率二极管Dh1、Dh2、Dh3、Dh4、DI1、DI2、DI3、DI4与各自的电源开关并联连接。正如通常所知的，高侧开关在其一个电源电极处连接到一个电源端子(例如B+端子)，而低侧开关在其一个电源电极处连接到另一电源端子(例如B-端子)。高侧开关和低侧开关串联连接，以在高侧开关和低侧开关相连接的点处形成具有输出节点12的半桥。
在优选实施例中，在半桥电路10中使用IGBT。因而，高侧IGBT在其集电极电极处连接到B+端子，低侧IGBT在其发射极电极处连接到B-端子，并且每个高侧开关处的发射极电极连接到各自低侧开关的集电极电极。注意，在优选实施例中，电路10包括单个高侧栅极端子GH和单个低侧栅极端子GL，因为高侧IGBT的栅极和低侧IGBT的栅极并联连接，并且从端子GH(高侧IGBT)或端子GL(低侧IGBT)接收单独的栅极信号。优选地，电路10可以进一步包括用于收集信息的端子。例如，电路10包括：端子RT1和RT2，用于收集有关电源开关温度的信息；端子EL，用于收集低侧发射极的电流；端子CH，用于收集高侧集电极电流；端子EH，用于收集高侧发射极电流；以及端子CL，用于收集低侧集电极电流。
注意，虽然优选IGBT，但是，其它功率半导体器件，诸如功率MOSFET或基于III-氮化物的功率器件，也可以用于电路10，而不偏离本发明。
参考图2A和2B，根据本发明的一个功率模块包括外壳设置，该外壳设置包括：模制框架14、第一和第二衬底16和18、B+汇流条20、B-汇流条22、输出汇流条24以及多个输入/输出(I/O)导线26。B+汇流条20、B-汇流条22、输出汇流条24和导线26嵌入(模制在)在框架14中。注意，输出汇流条24与B+汇流条20和B-汇流条22垂直隔开，而相对设置，因而B+汇流条20和B-汇流条22在一个平面上，而输出汇流条24在另一平面上。而且，衬底16和18被模制在框架14中，或者通过粘合剂等附着到框架14。注意，优选地，框架14通常形成数字8的形状，因而，跨B+汇流条20、B-汇流条和输出汇流条24所在的中心区域具有两个相对的开口。每个衬底16、18关闭如图所示的各自的开口。注意，每个B+总线20、B-总线22和输出总线24包括各自的导线28、30、32。导线28可连接到电源的B+极，导线30可连接到电源的B-电极，并且导线32可连接到负载，优选地，所述负载可以是电动机。衬底16包括导电接合垫(conductive pad)34，以便以电的方式和以机械的方式接纳(通过传导性粘合剂，如焊料等)低侧IGBT的集电极电极和高侧二极管的节点电极，而衬底18包括导电接合垫36，以便以电的方式和以机械的方式接纳(通过传导性粘合剂，如焊料等)高侧IGBT的集电极电极和高侧二极管的阴极电极。衬底16还包括低侧栅极轨(gate track)38、低侧栅极接合垫40、低侧发射极感测轨42以及第一低侧温度接合垫44和第二低侧温度接合垫46。类似地，衬底18包括高侧栅极轨48、高侧栅极接合垫50、高侧发射极感测接合垫52以及第一温度接合垫(pad)54和第二温度接合垫56。
参考图3，高侧开关、高侧二极管、低侧开关和低侧二极管设置在示出的外壳设置内部，并且通过引线接合而互连，以形成电路10。因而，高侧开关的发射极和低侧开关的集电极被引线接合到输出总线24，高侧集电极被引线接合到B+总线20，而每个开关的栅极被引线接合到各自的栅极接合垫40、50，并且每个栅极接合垫被引线接合到各自的栅极轨38、48。类似地，高侧和低侧的导线RT1、RT2被引线接合到温度感测接合垫44、46、54、56，高侧和低侧栅极导线GH、GL被引线接合到各自的栅极轨48、38，每个高侧和低侧发射极感测导线ESH、ESL被引线接合到相应的发射极感测轨52、54，而高侧和低侧集电极感测导线CSH、CSL中的每个被连接到各自的导电接合垫36、34。注意，引线接合是用数字57来示意性地示出和标识的。注意，每个IGBT的发射极是利用至少一个引线接合被引线接合到各自的发射极感测轨42、52的。
根据优选实施例的一个功率模块通常包括两个主要的集成部件：包括铜插入模制的导线框架的框架14和衬底。
优选地，框架14由适合的模制塑料制成。依赖于所需的框架14的额定温度，适合的塑料可以是PBT、PPS或PPA等。
在此所述的导线框架包括B+汇流条20、B-汇流条22、输出汇流条24和I/O导线26。B+汇流条20、B-汇流条22和输出汇流条24可以由1mm厚度或更厚的铜制成，而I/O导线26可以由小于1mm的铜制成。
依赖于模块的所需的热性能，每个衬底16、18可以是绝缘的金属衬底(Insulated Metal Substrate，IMS)、直接敷铜(Direct Bonded Copper，DBC)或氮化硅上铜(Copper on Silicon Nitride)等。利用焊料或导热性粘合剂，IGBT可以附着到衬底的导电接合垫。
在优选的实施例中，使用粘合剂将衬底16、18粘合到外壳，并且通常在引线接合中使用直径为0.015″或0.020″的铝线。在引线接合操作之后，硅凝胶等被沉积在衬底上，以保护二极管和开关。
根据本发明的功率模块将该模块的寄生电感最小化。特别是根据本发明的一个方面，B+汇流条20和B-汇流条22被横向并排设置，并且相互平行，而输出汇流条24设置在B+汇流条20和B-汇流条22下面。由于输出汇流条24设置在B+汇流条20和B-汇流条下面，所以寄生电感减小。即，将B+汇流条20及其相邻的B-汇流条22放置在输出汇流条24上面会产生一个低电感模块。I/O导线26的对称设计以及衬底16和18的布局进一步增进了模块的低电感性能。
而且，有利的是，电感均匀地分布在低侧和高侧之间，从而导致对称电路。即，低侧和高侧开关因此被暴露于类似的寄生电感效应，如电压过冲和开关应力。结果，模块中的所有半导体开关可以以其最大额定来工作，从而消除针对最大应力开关的等级来降低模块的功率处理能力的需要。
而且，具有集成的汇流条消除对于外部高电感互连的需要。结果，有效地减少了系统的总杂散电感，从而提高AC动态电压均衡，并允许对晶片的电压闭锁(voltage blocking)能力的最佳使用。此外，因为B+汇流条20和B-汇流条22针对最低的杂散电感进行优化并彼此靠近放置，所以，正的和负的电流路径具有相同的长度，这改善了通量消除(fluxcancellation)，并且将杂散场最小化，所述杂散场会产生EMI噪音。另外，通过降低电压过冲和半导体损耗，降低电感以及对称地分布低侧和高侧之间的电感会减小半导体开关上的应力，从而有效减少辐射的EMI噪音。
通常，引线接合和衬底的金属层的电流传送能力限制现有模块的电流容量。通过将对用于电流传导的衬底的金属层的使用最小化、将引线接合的长度最小化、最大限度的使用导线框架以传导高电流，以及通过提供冗余电流路径，根据本发明的一个模块呈现出改善的电流容量。
另外，作为对称和平衡结构结果，通过对半导体开关的控制和电源端子的寄生阻抗进行均衡，改善了开关损耗和电流的共享。
根据本发明的具有有利的低寄生电感的模块可以与缓冲器(snubber)、EMI电容器和温度传感器结合。优选地，电容器非常近地连接到开关，以获得电容器和开关之间的最小的寄生电感，并且对于减小不期望的电压过冲、振荡和EMI是极其有效的。紧邻于半导体开关、直接在衬底上安装温度传感器使得可以为了保护的目的而对半导体器件的热状态进行监视。
根据本发明的一个模块，通过允许改善的总线电压操作和更好的总线利用，来提高电动机驱动系统的总效率。永磁同步和感应电动机在较高的线电压处呈现出提高的效率。根据本发明的一个模块实现了较低的瞬态过电压，以允许以增高的总线电压工作，这导致驱动系统的效率由于更有效地电动机运转而提高。
虽然本发明的优选实施例包括单个半桥，但是在此所实施的概念可以用于构造全桥模块以及两相、三相和多相模块。
根据本发明的一个功率模块可以用于所有类型的功率转换应用，例如DC-DC转换器(如降压(buck)、升压(boost)和降压-升压等)或AC应用(例如包括单相和多相逆变器、交-交变频器(cyclo-converter)和电动机驱动等)。所述应用还可以包括开关模式的功率放大器。
虽然本发明描述了与其有关的特定实施例，但是许多其它变形、修改和其它用途对本领域技术人员来说是明显的。因此，本发明不限于在此所具体公开的内容，而仅由所附的权利要求来限制。

Claims (19)

1.一种功率模块，包括：
框架；
第一总线，其可连接到电源的一极，并且嵌入在所述框架内；
第二总线，其可连接到电源的另一极，并且嵌入在所述框架内；
输出总线，其嵌入在所述框架内，并且与所述第一汇流条和所述第二汇流条隔开，而与所述第一汇流条和所述第二汇流条相对设置；以及
功率电路，包括高侧功率半导体开关和低侧功率半导体开关，所述高侧功率半导体开关电连接到所述第一总线和所述输出总线，而所述低侧功率半导体开关电连接到所述第二总线和所述输出总线。
2.根据权利要求1所述的模块，其中所述框架是模制的。
3.根据权利要求1所述的模块，其中所述第一汇流条和所述第二汇流条在一个平面上，而所述输出总线位于所述一个平面下的另一平面上。
4.根据权利要求1所述的模块，进一步包括与所述框架集成在一起的第一衬底和与所述框架集成在一起的第二衬底，其中所述高侧功率半导体开关设置在所述第一衬底上，而所述低侧功率半导体开关设置在所述第二衬底上。
5.根据权利要求4所述的模块，其中所述第一衬底被设置在所述第一总线、所述第二总线和所述输出总线一侧，而所述第二衬底被设置在所述第一总线、所述第二总线和所述输出总线一侧，并且与所述第一衬底相对，由此所述第一总线、所述第二总线和所述输出总线被设置在所述第一衬底和所述第二衬底之间。
6.根据权利要求1所述的模块，进一步包括：高侧二极管，其与所述高侧功率半导体开关并联连接；以及低侧二极管，其与所述低侧功率半导体开关并联连接。
7.根据权利要求1所述的模块，其中所述功率电路进一步包括：与所述高侧功率半导体开关并联连接的多个高侧功率半导体开关、以及与所述低侧功率半导体开关并联连接的多个低侧功率半导体开关。
8.根据权利要求7所述的模块，其中所述多个高侧功率半导体开关包括三个开关，并且所述多个低侧功率半导体开关包括三个开关。
9.根据权利要求7所述的模块，进一步包括二极管，其与每个所述高侧开关和每个所述低侧开关并联连接。
10.根据权利要求7所述的模块，其中所述第一衬底包括用于所有所述高侧开关的公共栅极轨和用于所有所述低侧开关的公共栅极轨。
11.根据权利要求7所述的模块，其中所述第一衬底包括用于所有所述高侧开关的发射极感测轨，而所述第二衬底包括用于所有所述低侧开关的发射极感测轨。
12.根据权利要求7所述的模块，其中所述高侧开关共用所述第一衬底上的公共集电极接合垫，并且所述低侧开关共用所述第二衬底上的公共集电极接合垫。
13.根据权利要求12所述的模块，进一步包括：电连接到所述第一衬底上的所述公共集电极接合垫的集电极感测导线、和电连接到所述第二衬底上的所述公共集电极接合垫的集电极感测导线。
14.根据权利要求1所述的模块，进一步包括：与所述框架集成在一起的所述高侧功率半导体开关的多个高侧I/O导线、和与所述框架集成在一起的所述低侧功率半导体开关的多个低侧I/O导线，其中所述I/O导线包括温度感测导线、集电极感测导线、发射极感测导线和栅极导线。
15.根据权利要求7所述的模块，进一步包括：与所述框架集成在一起的所述高侧功率半导体开关的多个高侧I/O导线、和与所述框架集成在一起的所述低侧功率半导体开关的多个低侧I/O导线，其中所述I/O导线包括温度感测导线、集电极感测导线、发射极感测导线和栅极导线。
16.根据权利要求4所述的模块，其中所述第一衬底和所述第二衬底中每个是IMS或DBC。
17.根据权利要求1所述的模块，其中所述高侧和低侧功率半导体开关是IGBT或功率MOSFET。
18.根据权利要求7所述的模块，其中所述高侧和低侧功率半导体开关是IGBT或功率MOSFET。
19.根据权利要求1所述的模块，其中所述第一总线和所述第二总线横向、并排设置，并且彼此相互平行，而所述输出总线设置在所述第一总线和所述第二总线下面。
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