CN101261611A - Data transmission device and method between peripheral equipment - Google Patents

Abstract

The invention relates to a device and a method for controlling data transmission, which are used for controlling the data transmission between peripheral equipment. The device comprises two control units and a temporary storage unit, wherein the control units and the temporary storage unit are integrated on the same chip. When the data is only transmitted among the peripheral equipment, the first control unit temporarily stores the data to be transmitted into the temporary storage unit by the first peripheral equipment, and then the second control unit directly stores the data to be transmitted into the second peripheral equipment from the temporary storage unit. The device and the method for controlling data transmission among the peripheral equipment have the advantages that the data transmission path is short, and the problems of time delay and the like caused by overlong transmission path in the traditional method are solved.

Description

A data transmission device and transmission method between peripheral devices

technical field

The invention relates to data transmission, in particular to a data transmission device and a transmission method between peripheral devices.

Background technique

In an embedded system containing a central processing unit (CPU), in order to improve the efficiency of memory and CPU usage, data transmission is usually performed by means of Direct Memory Access (DMA). In the prior art, each peripheral device has its corresponding DMA controller, and the DMA controller is generally integrated in the south bridge. When data is transferred from the first peripheral device to the second peripheral device, the transmission path it has to go through is very long. In the read cycle, the DMA controller of the first peripheral device obtains the data in the first peripheral device through the bus connected between the south bridge and the first peripheral device, and passes the data through another bus connected between the south bridge and the north bridge. The bus is transmitted to the North Bridge, and then the data is temporarily stored in the memory by the North Bridge through the bus connected between the North Bridge and the memory; in the write cycle, the data temporarily stored in the memory is transmitted to the North Bridge through the bus, and then the data is sent by the North Bridge The data is transmitted to the DMA controller of the second peripheral device in the south bridge through the bus, and the DMA controller of the second peripheral device stores the data into the second peripheral device.

Therefore, when performing data transmission between peripheral devices by means of DMA, since the data is temporarily stored in the memory, the data transmission path is very long. If a device and method for shortening the data transmission path can be found, the efficiency and performance of data transmission will be greatly improved.

Contents of the invention

Therefore, from the above summary, the objects, features and advantages of this invention will become apparent to those skilled in the art from the subsequent description and appended claims together with the accompanying drawings.

The present invention provides an apparatus and method for controlling data transmission for transmission between peripheral devices, so as to avoid the above-mentioned disadvantages.

In one embodiment, the present invention provides a device for controlling data transmission, which is used for controlling data transmission between a first peripheral device and a second peripheral device. The device for controlling data transmission includes a first control unit, a second control unit and a temporary storage unit. The first control unit is used for reading the data from the first peripheral device according to the read information of the data to be transmitted. The second control unit is used for storing the data to be transmitted in the second peripheral device according to the storage information of the data to be transmitted. The temporary storage unit is connected to the first control unit and the second control unit, and is integrated with the first control unit and the second control unit in the same chip, and is used to temporarily store the data read by the first control unit that needs to be transmitted , and transmit the data to be transmitted to the second control unit.

In another embodiment, the present invention also provides a method for controlling data transmission, which is used for controlling data transmission between a first peripheral device and a second peripheral device. The method includes: reading data to be transmitted from the first peripheral device according to the read information; temporarily storing the data to be transmitted in a temporary storage unit; and transmitting the data to be transmitted in the temporary storage unit according to the stored information Data is stored to a second peripheral.

The device and method for controlling data transmission provided by the present invention temporarily store the data transmitted between peripheral devices in the temporary storage unit, avoiding the problem of too long transmission path caused by the temporary storage of data in the memory, and improving the efficiency of data transmission. speed and performance.

Description of drawings

Fig. 1 is a traditional computer system architecture diagram including a DMA controller.

Fig. 2 is a flow chart when the data in the I/O device is transferred to the hard disk by means of DMA.

FIG. 3 is a computer system architecture diagram of a data transmission device between peripheral devices in the first preferred embodiment of the present invention.

FIG. 4 is a computer system architecture diagram of a data transmission device between peripheral devices in a second preferred embodiment of the present invention.

FIG. 5 is a flow chart of transferring data in the I/O device to the hard disk by using the improved data transmission method between peripheral devices.

Detailed ways

The invention will be described by the following examples. However, it should be understood that the following examples are not absolutely limitations of the present invention, but are typical implementations of the present invention.

Having outlined various aspects of the invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While the invention is described in connection with these figures, there is no intention to limit the invention to the embodiments of the invention herein. On the contrary, all alternatives, modifications and equivalents should fall within the spirit and scope of the invention as defined by the appended claims.

It should be noted that the diagrams presented herein are for illustrative purposes only of certain features and aspects of embodiments of the invention. It can be understood from the description provided herein that various alternative embodiments and implementations can be made without departing from the spirit and scope of the invention.

It should also be noted that the illustrations presented here are not drawn to scale. The proportions of some of the components are not in direct proportion to the proportions of other components to provide clarity and to emphasize the invention.

Referring to FIG. 1 , this is a traditional computer system architecture diagram including a DMA controller. The computer system architecture diagram includes a central processing unit 101, a north bridge 103, a memory 105, a south bridge 107 and related peripheral devices. In order to make the illustration clear, the peripheral devices only indicate the first peripheral device 109 and the second peripheral device 111 , and the data to be transmitted is transmitted from the first peripheral device 109 to the second peripheral device 111 . Peripheral devices include various input and output (I/O) devices including hard disks.

The central processing unit 101 is configured to generate a descriptor (descriptor) describing data read and write operations, and the descriptor includes a read descriptor and a storage descriptor. Wherein, the type of data to be transmitted, the length, and the address information of the data to be read from the first peripheral device 109 are recorded in the read descriptor, which is mainly used to describe the data transmission operation of the read cycle; The storage descriptor records the type and length of the data to be transmitted, and the address information of the data stored in the second peripheral device 111, etc., and is mainly used to describe the data transmission operation in the write cycle.

The Northbridge 103 is connected to the CPU 101 and is used for transmitting descriptors and data to be transmitted. Memory 105 is connected to central processing unit 101 and north bridge 103, and central processing unit 101 writes the descriptor information generated in memory 105, and north bridge 103 temporarily stores the data that needs transmission in memory 105, therefore, memory 105 is used for storing description character and the data to be transmitted and other information.

The south bridge 107 includes a connection unit 121 , a first DMA controller 123 and a second DMA controller 125 . The connection unit 121 is connected to the north bridge 103 and is mainly used to transmit the data to be transmitted to the north bridge 103 and receive the descriptor transmitted by the north bridge 103 . The first DMA controller 123 is connected between the connection unit 121 and the first peripheral device 109, and when the connection unit 121 receives the read descriptor, it will transmit the read descriptor to the first DMA controller 123, and the first The DMA controller 123 parses the read descriptor, and transmits the data to be transmitted at the corresponding address in the first peripheral device 109 to the connection unit 121 . The second DMA controller 125 is connected between the connection unit 121 and the second peripheral device 111, and when the connection unit 121 receives the storage descriptor, it will transmit the storage descriptor to the second DMA controller 125, and the second DMA controls The device 125 parses the storage descriptor, and transmits the data to be transmitted in the second peripheral device 111 to the connection unit 121 .

In order to show the process of data transmission in DMA mode more clearly, take the data transmission from I/O device to hard disk as an example, Figure 2 is a flow chart of using DMA to transfer data from input and output devices to hard disk . In step 201 , the CPU 101 writes the read descriptor of the read/write operation into the memory 105 . In step 203 , the read descriptor stored in the memory 105 will be transmitted to the connection unit 121 through the north bridge 103 , and the connection unit 121 will transmit the read descriptor to the first DMA controller 123 . Then, the first DMA controller 123 parses the read descriptor (step 205) to determine the type and length of the data to be transmitted, and the data that should be read from the first peripheral device 109, i.e. the I/O device in this embodiment Information such as the address of the read data. In step 207, according to the parsed read descriptor information, the first peripheral device 109, that is, the data to be transmitted in the I/O device in this embodiment is sent by the first DMA controller 123 through the connecting unit 121 and the north bridge 103 transferred to memory 105. In step 209, the first DMA controller 123 determines whether the data transfer has been completed. If it has not been completed, return to step 207; if the data transmission has been completed, enter step 211. In step 211 , the central processing unit 101 writes the storage descriptor corresponding to the read/write operation into the memory 105 . In step 213 , the storage descriptor stored in the memory 105 will be transmitted to the connection unit 121 through the north bridge 103 , and the connection unit 121 will transmit the read descriptor to the second DMA controller 125 . Then, the second DMA controller 125 parses this storage descriptor (step 215) to determine the type and length of the data that needs to be transmitted, and the data should be stored to the second peripheral device 111, that is, the hard disk in this embodiment Address and other information. In step 217, according to the parsed storage descriptor information, the data to be transferred is transferred by the second DMA controller 125 to the second peripheral device 111, ie the hard disk in this embodiment, through the north bridge 103 and the connection unit 121. In step 219, the second DMA controller 125 determines whether the data transfer has been completed. If it has not been completed, return to step 217; if the data transfer has been completed, the workflow ends, and the data is transferred from the I/O device to the hard disk in DMA mode. It can be seen from the flow chart that the path of data transmission is quite long. If the path of data transmission can be shortened, the rate and performance of data transmission can be greatly improved.

FIG. 3 is a computer system architecture diagram of a data transmission device between peripheral devices in the first preferred embodiment of the present invention. The computer system architecture diagram includes a central processing unit 301, a north bridge 303, a memory 305, a south bridge 307 and related peripheral devices. In order to make the illustration clear, the peripheral devices only indicate the first peripheral device 309 and the second peripheral device 311 , and the data to be transmitted is transmitted from the first peripheral device 309 to the second peripheral device 311 .

The central processing unit 301 is configured to generate descriptors describing data read and write operations, and the descriptors include read descriptors and storage descriptors. Wherein, the type of the data to be transmitted, the length, and the address information of the data to be read from the first peripheral device 309 are recorded in the read descriptor, which is mainly used to describe the data transmission operation of the read cycle; The storage descriptor records the type and length of the data to be transmitted, and the address information of the data stored in the second peripheral device 311, etc., and is mainly used to describe the data transmission operation in the write cycle.

The Northbridge 303 is connected to the CPU 301 for transmitting descriptors and data information. The memory 105 is connected to the central processing unit 301 and the north bridge 303, and the central processing unit 101 writes the generated descriptor information into the memory 305. If the data is not simply transmitted between peripheral devices, the north bridge 303 will transfer the data to the memory 305 , therefore, the memory 305 is used to store information such as descriptors and data.

The south bridge 307 includes a receiving unit 308 , a first DMA controller 327 and a second DMA controller 329 . The receiving unit 308 is connected to the Northbridge 303, and is mainly used to receive the read descriptor and the storage descriptor transmitted by the Northbridge 303, and analyze the read descriptor and the storage descriptor to obtain the type of data to be transmitted, the length, Information such as the address of the data read from the first peripheral device 309 and the address of the data stored in the second peripheral device 311 . If the data is not simply transmitted between peripheral devices, the receiving unit 308 transmits the data to the north bridge 303 .

The receiving unit 308 includes a connection unit 321 , a first parsing unit 323 and a second parsing unit 325 . The connection unit 321 is connected to the North Bridge 303 through an external bus, and is used for receiving the read descriptor and the store descriptor written into the memory 305 by the CPU 301 . The first analysis unit 323 is connected to the connection unit 321, and is used to receive the read descriptor transmitted from the connection unit 321, and analyze the read descriptor to obtain the read information of the data to be transmitted, for example, The type and length of the data to be read, and the address information of the data read from the peripheral device, etc. The second parsing unit 325 is connected to the connection unit 321, and is used to receive the storage descriptor transmitted from the connection unit 321, and then parse the storage descriptor to obtain the storage information of the data to be transmitted, for example, the data to be stored The type and length of the data, and the address information of the data stored in the peripheral device, etc.

The first control unit 327 is connected to the first parsing unit 323 and is used for controlling the transmission of the data to be transmitted read from the first peripheral device 309 according to the parsed read information of the data. The second control unit 329 is connected to the second parsing unit 325 , and is used for controlling the storage of the data to be transmitted into the second peripheral device 311 according to the parsed storage information of the data. The temporary storage unit 331 is connected between the first control unit 327 and the second control unit 329. When the data is only used for transmission between peripheral devices, the first control unit 327 temporarily stores the data to be transmitted in the temporary storage unit 331 , the second control unit 329 transmits the data temporarily stored in the temporary storage unit 331 to the second peripheral device 311 .

If the data is not only used for transmission between peripheral devices, then in the read cycle, the first control unit 327 transmits the data to the first analysis unit 323, and the first analysis unit 323 transmits the data to the connection unit 321, and the connection unit 321 transmits the data The data is transmitted to the Northbridge 303, and the data is finally transmitted to the memory 305 by the Northbridge 303. For example, the data that needs to be transmitted is image data, and image processing needs to be performed. At this time, the data will be passed by the first peripheral device 309 through the first control unit 327, the first analysis unit 323, the connection unit 321 and the north bridge 303, and finally temporarily Stored in the memory 305 ; and during the write cycle, the data temporarily stored in the memory 305 will be transmitted to the second peripheral device 311 through the north bridge 303 , the connection unit 321 , the second analysis unit 325 and the second control unit 329 . That is to say, when data is only transmitted between peripheral devices, the data to be transmitted is temporarily stored in the temporary storage unit 331 instead of temporarily stored in the memory.

The memory 305 is connected to the central processing unit 301. When the data needs to be processed, the traditional method of temporarily storing the data in the memory is more applicable. However, if the data is simply transferred between peripheral devices, the traditional temporary storage of data in the memory will bring unnecessary time delay. Due to the advancement of technology, the technology of integrating the temporary storage unit and the control unit on the same chip is quite mature. Therefore, using this method to realize data transmission between peripheral devices has good transmission efficiency and will greatly simplify read and write operations. workflow.

Referring to FIG. 4 , it is a computer system architecture diagram of a data transmission device between peripheral devices in the second preferred embodiment of the present invention. The computer system architecture diagram includes a central processing unit 401, a north bridge 403, a memory 405, a south bridge 407 and related peripheral devices. In order to make the illustration clear, the peripheral devices only indicate the first peripheral device 409 and the second peripheral device 411 , and the data to be transmitted is transmitted from the first peripheral device 409 to the second peripheral device 411 . The central processing unit 401 is used to generate descriptors describing data read and write operations. Different from traditional descriptors, the descriptors are no longer divided into read descriptors and storage descriptors, but the two descriptors are combined by the system software. Rewritten as a read-write descriptor, which records the type and length of the data to be transmitted, the address information of the data to be read from the first peripheral device 409, and the data stored in the second peripheral device 411 address information, etc. The read-write descriptor merges the repeated data information in the original read descriptor and storage descriptor, which can describe the read-write operation more simply. The Northbridge 403 is connected to the CPU 401 and is used for transmitting read/write descriptors and data information. The memory 405 is connected to the central processing unit 401 and the north bridge 403, and the central processing unit 401 writes the generated read-write descriptor information into the memory 405. If the data is not simply transmitted between peripheral devices, the north bridge 403 will transfer the data to the memory In 405, therefore, the memory 405 is used to store information such as descriptors and data.

The south bridge 407 includes a receiving unit 408 , a first controller 427 and a second controller 429 . The receiving unit 408 is connected to the north bridge 403, and is mainly used to receive the read-write descriptor transmitted by the north bridge 403, and analyze the read-write descriptor to obtain the type, length, and information from the first peripheral device 409 of the data to be transmitted. Information such as the address of the read data and the address of the data stored in the second peripheral device 411 . If the data is not simply transmitted between peripheral devices, the receiving unit 408 transmits the data to the north bridge 403 .

The receiving unit 408 includes a connection unit 421 and an analysis unit 423 . The connection unit 421 is connected to the north bridge 403 through an external bus, so as to receive the read/write descriptor written into the memory 405 by the central processing unit 401 . The analysis unit 423 is connected to the connection unit 421, and is used to receive the read-write descriptor transmitted from the connection unit 421, and analyze the read-write descriptor to obtain the reading and storage information of the data to be transmitted, for example, The type and length of the data to be transmitted, the address information of the data read from the first peripheral device 409 and the address information of the data stored in the second peripheral device 411 and so on.

The first control unit 427 is connected to the analysis unit 423, and is used to receive the read information from the analysis unit 423, and control the transmission of the data to be transmitted read from the first peripheral device 409 according to the read information of the data analyzed . The second control unit 429 is connected to the parsing unit 423 for receiving storage information from the parsing unit 423 , so as to control storing the data to be transmitted into the second peripheral device 311 according to the parsed storage information of the data.

The temporary storage unit 431 is connected between the first control unit 427 and the second control unit 429. When the data is only used for transmission between peripheral devices, the first control unit 427 temporarily stores the data to be transmitted in the temporary storage unit 431 , the second control unit 429 transmits the data temporarily stored in the temporary storage unit 331 to the second peripheral device 411 . If the data is not only used for transmission between peripheral devices, then in the read cycle, the first control unit 427 transmits the data to the analysis unit 423, the analysis unit 423 transmits the data to the connection unit 421, and the connection unit 421 transmits the data to the north bridge 403 , the data is finally transmitted to the memory 405 by the north bridge 403, for example, the data to be transmitted is image data, and image processing is required, at this time, the data will be passed by the first peripheral device 409 through the first control unit 427, the analysis unit 423, The connection unit 421 and the north bridge 403 are temporarily stored in the memory 405 at last; and in the write cycle, the data temporarily stored in the memory 405 will be transmitted to the second peripheral device through the north bridge 403, the connection unit 421, the analysis unit 423 and the second control unit 429 411 in.

Using software to rewrite the descriptor can save one analysis unit, and the connection unit 421 can directly transmit the descriptor to the only analysis unit 423, omitting the process of judging which analysis unit should be transmitted, that is, saving the chip area Also increased the transmission speed.

In another embodiment, the receiving unit 408 , the first control unit 427 , the temporary storage unit 431 and the second control unit 429 are integrated in another independent chip instead of the south bridge 407 . In one embodiment, the receiving unit 408 is integrated on the south bridge 407, and the first control unit 427, the temporary storage unit 431 and the second control unit 429 are integrated in another independent chip.

In order to compare with the traditional DMA data transmission method, take the data transmission from the I/O device to the hard disk as an example again. Figure 5 uses the improved data transmission method between peripheral devices to transfer the data in the I/O device The flow chart when entering the hard disk, the computer system architecture adopted is as shown in Figure 4.

In step 501, the central processing unit 401 writes the read-write descriptor of the read-write operation into the memory 405. The read-write descriptor merges the original read descriptor and storage descriptor, and includes the data required for data transmission. necessary information. In step 503 , the read-write descriptor stored in the memory 405 will be transmitted to the connecting unit 421 in the receiving unit 408 through the north bridge 403 , and the connecting unit 421 will transmit the read-write descriptor to the parsing unit 423 . Then, the parsing unit 423 in the receiving unit 408 parses the descriptor (step 505) to obtain the reading and storage information of the data to be transmitted, for example, the type, length, and information of the data to be transmitted from the first peripheral device. The address information of the read data in 409 and the address information of the data stored in the second peripheral device 411 and so on. In step 507, the parsing unit 123 judges the type of the data transmission according to the parsed descriptor information, and when the data is not used for transmission between peripheral devices, the step proceeds to 508 to perform a traditional DMA operation. When the data is transmitted between peripheral devices, if this cycle is a read operation, the analysis unit 423 will transmit the read information to the first control unit 427, and the process enters step 509; if this cycle is a write operation, the analysis unit 423 will read The fetched information is transmitted to the second control unit 429, and the process goes to step 511. In step 509 , the data in the first peripheral device 409 , that is, the I/O device in this embodiment is transferred to the temporary storage unit 431 by the first control unit 427 . In step 511, the first control unit 427 determines whether the data transmission has been completed. If it has not been completed, return to step 509; if the data transmission has been completed, enter step 513. In step 513, the second control unit 429 transfers the data in the temporary storage unit 431 to the second peripheral device, namely the hard disk in this embodiment. In step 515, the second control unit 429 determines whether the data transmission has been completed. If it has not been completed, return to step 515; if the data transfer has been completed, the workflow ends, and the data in the I/O device is transferred to the hard disk. It can be seen from this flow chart that since the data is temporarily stored in the temporary storage unit 431, the path of data transmission is shortened, reducing the time delay caused by too long transmission path, which will greatly improve the rate and speed of data transmission. performance.

The above description is not intended to be exhaustive or to limit the invention to the precise form invented. Obvious modifications and variations are possible in light of the above teachings. In this regard, the embodiments discussed were chosen and described in order to provide the best explanation of the principles of the invention and its practical application, thereby enabling others of ordinary skill in the art to utilize the invention in various embodiments and to provide the best explanation for its practical application. Various modifications are suited to the particular intended use. All such modifications and variations are within the scope of the invention, which is to be determined by the appended claims to be read to the breadth they are legally and equitably entitled to.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and improvements on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims of the present application.

Claims (10)

1. A device for controlling data transmission, used for data transmission between a first peripheral device and a second peripheral device, characterized in that it comprises: The first control unit is configured to read the data to be transmitted from the first peripheral device according to the read information of the data to be transmitted; A second control unit, configured to store the data to be transmitted in the second peripheral device according to the storage information of the data to be transmitted; and a temporary storage unit, connected to the first control unit and the second control unit, and integrated in the same chip with the first control unit and the second control unit, for temporarily storing the data that needs to be transmitted, and transmit the data that needs to be transmitted to the second control unit. 2. The device for controlling data transmission according to claim 1, further comprising: The receiving unit is connected to the first control unit and the second control unit, and is used to receive the descriptor and analyze the descriptor to obtain the read information and the storage information of the data to be transmitted. 3. The device for controlling data transmission according to claim 2, wherein the receiving unit includes: A connection unit, connected to the external bus, for receiving the descriptor, the descriptor includes a read descriptor and a storage descriptor; a first parsing unit, connected to the connection unit and the first control unit, for parsing the read descriptor to obtain the read information described in the data to be transmitted; and The second parsing unit, connected to the connection unit and the second control unit, is configured to parse the storage descriptor to obtain the storage information described in the data to be transmitted. 4. The device for controlling data transmission according to claim 2, wherein the receiving unit includes: a connection unit, connected to the external bus, for receiving the descriptor, where the descriptor is a read-write descriptor; and An analysis unit, connected to the connection unit, the first control unit, and the second control unit, for analyzing the read-write descriptor to obtain the read information described in the data to be transmitted and the data to be transmitted the stored information. 5. The device for controlling data transmission according to claim 1, characterized in that, the types of peripheral devices include any combination of input and output devices and hard disks. 6. A method for controlling data transmission, used in a chip to control data transmission between a first peripheral device and a second peripheral device, characterized in that it comprises: reading data to be transmitted from the first peripheral device according to the read information; Temporarily storing the data to be transmitted in a temporary storage unit in the chip; and The data to be transmitted in the temporary storage unit is stored in the second peripheral device according to the storage information. 7. The method for controlling data transmission according to claim 6, further comprising a receive descriptor, the descriptor includes a read descriptor and a storage descriptor. 8. The method for controlling data transmission according to claim 7, further comprising Parsing the read descriptor to obtain the read information described in the data to be transmitted; and The storage descriptor is parsed to obtain the storage information described in the data to be transmitted. 9. The method for controlling data transmission according to claim 6, further comprising receiving the read-write descriptor and parsing the read-write descriptor to obtain the read-write descriptor of the data to be transmitted. Fetch information and store information as described. 10. The method for controlling data transmission according to claim 6, characterized in that, the types of peripheral devices include any combination of input and output devices and hard disks.

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