CN101257303A - Clock Control Circuit of Sigma-Delta Modulator in Sigma-Delta Fractional Frequency Synthesizer - Google Patents

Abstract

A sigma-delta modulator clock control circuit in a sigma-delta fractional frequency synthesizer, including a sigma-delta modulator, receiving a VCO signal from an externally connected voltage-controlled oscillator and receiving a signal from the sigma-delta modulator. The delay unit of the signal. The delay unit includes a frequency divider and a delay circuit, wherein the input terminal of the frequency divider receives the VCO signal sent by the external voltage-controlled oscillator, and the input terminal of the frequency divider is also connected with the Σ-Δ modulator to receive the signal sent by it. signal; the output end of the frequency divider is respectively connected with an external PFD and a delay circuit, and the delay circuit outputs a clock signal of the Σ-Δ modulator to the Σ-Δ modulator. The present invention has wide applicability, no matter what structure the frequency divider in the fractional frequency synthesizer adopts, and what structure the DSM adopts, it can be applied to ensure that the frequency divider reads the correct frequency division number and eliminates the digital frequency divider. The influence of circuit switch flipping on PFD ensures the accuracy of phase comparison, thereby improving system performance.

Description

Clock Control Circuit of Sigma-Delta Modulator in Sigma-Delta Fractional Frequency Synthesizer

technical field

The invention relates to a Σ-Δ modulator clock control technology. In particular, it relates to a method that can be applied regardless of the structure of the frequency divider in the fractional frequency synthesizer and the structure of the DSM, so as to ensure that the frequency divider reads the correct frequency division number and eliminate the impact of digital circuit switch flipping. The effect of PFD, which in turn improves the system performance of the sigma-delta modulator clock control circuit in the sigma-delta fractional frequency synthesizer.

Background technique

As shown in Figure 1, a frequency synthesizer based on a phase-locked loop structure includes basic units such as a phase-frequency detector (PFD), a charge pump, a filter, a voltage-controlled oscillator (VCO), and a frequency divider. The frequency and phase detector inputs a reference frequency, and the output frequency of the voltage-controlled oscillator is also input to the frequency and phase detector after being divided by the frequency divider. The frequency and phase detector compares the difference between the two input frequency phases , and then control the voltage-controlled oscillator to change the output frequency, so that the output frequency reaches the target frequency value—the base reference frequency multiplied by the frequency division multiple. On the basis of the above phase-locked loop structure, the Σ-Δ fractional frequency synthesizer realizes fractional frequency division, that is, the frequency division multiple can be a fractional value, not limited to an integer. This fractional frequency division is realized by continuously changing the integer frequency division value of the frequency divider so that the average value reaches the desired decimal. The change of the frequency division modulus is controlled by a Σ-Δ modulator (DSM). In the circuit, DSM needs a clock signal to trigger, and the quantized output of DSM changes on each trigger edge, and the frequency division number changes accordingly. Usually, the clock signal of the DSM is the reference clock Tref or the frequency-divided signal output by the voltage-controlled oscillator, that is, an input comparison signal Tdiv of a phase frequency detector (PFD). However, there are certain problems in the above two solutions in practical applications, which lead to the deterioration of the performance of the frequency synthesizer, or even the failure to lock it.

Since the frequency division number of the fractional frequency synthesizer is constantly changing, the counting unit in the frequency divider needs to read the next frequency division number after each complete frequency division cycle ends, usually under the control of the overflow signal of the counting unit Read in of a frequency divider. If the clock signal of the DSM is provided by the reference clock Tref, the following problems will arise: If a period signal after frequency division is ahead of the reference clock signal, that is to say, the DSM has not output a new frequency division number after a complete frequency division period. , what the frequency division counter reads is still the frequency division number of the previous cycle, resulting in an error in the average fractional frequency division value. Usually the smaller the frequency division, the more obvious this effect. If the division number is small, this deviation will cause the output frequency to swing wildly and the loop will not lock.

Selecting the frequency-divided signal Tdiv as the DSM clock signal can avoid the above problems. However, DSM is a digital circuit. When the clock edge is triggered, a large number of MOS tubes will be flipped inside. At this time, it is also the time for PFD to perform phase comparison. After the system reaches the locked state, the signals compared by PFD are very different. Short, if this digital switch flip is coupled to the PFD through the power supply or the substrate, it will cause errors in the PFD comparison, cause additional phase deviation, and degrade the overall noise performance of the system. Of course, for the former case where the DSM clock is provided by the reference frequency, in addition to the above-mentioned problem of reading in the wrong frequency division, there will also be DSM because the phase difference between the two inputs of the frequency detector and phase detector is not large when the loop is locked. Issue with digital switch flipping affecting PFD phase comparison.

Contents of the invention

The technical problem to be solved by the present invention is to provide a kind of structure that can be applied to ensure that the frequency divider reads the correct frequency division number regardless of the structure of the frequency divider in the decimal frequency synthesizer or the structure of the DSM. And eliminate the impact of digital circuit switch flipping on PFD, and then improve the system performance of the Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer.

The technical solution adopted in the present invention is: a Σ-Δ modulator clock control circuit in a Σ-Δ fractional frequency synthesizer, including a Σ-Δ modulator, which receives the VCO signal sent by an externally connected voltage-controlled oscillator And a delay unit receiving the signal sent by the sigma-delta modulator.

The delay unit includes a frequency divider and a delay circuit, wherein the input terminal of the frequency divider receives the VCO signal sent by the external voltage-controlled oscillator, and the input terminal of the frequency divider is also connected with the Σ-Δ modulator to receive the signal. The signal sent out; the output end of the frequency divider is respectively connected to an external PFD and a delay circuit, and the delay circuit outputs a clock signal of the Σ-Δ modulator to the Σ-Δ modulator.

The delay circuit is composed of an inverter chain composed of a plurality of NOT gates F.

The Σ-Δ modulator is a Σ-Δ modulator with a MASH1-1-1 structure.

Described frequency divider comprises n/n+1 prescaler and the P-S programming counter that is connected with n/n+1 prescaler and receives its signal, and described delay circuit adopts TSPC-D flip-flop, Among them, the input terminal of the n/n+1 prescaler receives the VCO signal sent by the voltage controlled oscillator, the n/n+1 prescaler sends a clock signal to the TSPC-D flip-flop, and the TSPC-D flip-flop sends a clock signal to the The Σ-Δ modulator outputs a Σ-Δ modulator clock signal, and the output of the Σ-Δ modulator is connected to the P-S programming counter; the output terminals of the P-S programming counter are respectively connected to the external PFD and TSPC-D flip-flops.

The Σ-Δ modulator is a Single-loop four-bit third-order modulator.

The Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer of the present invention adopts delay technology and corresponding circuit structure, solves the problems existing in the existing Σ-Δ fractional frequency synthesizer, and ensures that the frequency divider reads Enter the correct frequency division number, and can effectively avoid the influence of digital circuit switch flipping on PFD phase comparison, ensuring the accuracy of phase comparison. The present invention has wide applicability, no matter what structure the frequency divider in the fractional frequency synthesizer adopts, and what structure the DSM adopts, it can be applied to ensure that the frequency divider reads the correct frequency division number and eliminates the digital frequency divider. The impact of circuit switch flipping on PFD, thereby improving system performance.

Description of drawings

Fig. 1 is the structural principle diagram of the sigma-delta fractional frequency synthesizer based on the PLL structure of the prior art;

Fig. 2 is a schematic circuit diagram of the present invention;

Fig. 3 is a schematic circuit diagram of an embodiment of Fig. 2;

FIG. 4 is a schematic circuit diagram of another embodiment of FIG. 2 .

1: delay unit 2: frequency divider

3: Delay circuit 4: Σ-Δ modulator

5: 7/8 prescaler 6: P-S programming counter

7: TSPC-D trigger

Detailed ways

The clock control circuit of the sigma-delta modulator in the sigma-delta fractional frequency synthesizer of the present invention will be described in detail below with reference to the drawings of the embodiments.

The Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer of the present invention includes a Σ-Δ modulator 4 (DSM), which receives the VCO signal sent by the voltage-controlled oscillator connected to the outside and receives the Σ-Δ modulator 4 (DSM). Delta Modulator 4

(DSM) Delay unit 1 for the signal sent out. The technology of adding the delay unit in the present invention ensures that the frequency divider reads the correct frequency division number, and at the same time makes the digital circuit switch flip and PFD phase comparison time staggered, thereby effectively avoiding the influence of the digital circuit switch flip on the PFD phase comparison, The accuracy of the phase comparison is guaranteed. The delay unit can be implemented with different circuits, such as inverter chains, flip-flops, etc. The selection of the delay time should be determined in combination with the working characteristics of the system. The delay time should be sufficient to ensure that the PFD completes the phase comparison. For the fractional frequency synthesizer, because the frequency division number is constantly changing and the output frequency is constantly changing, the system can never reach a strictly locked state, that is to say, the phase difference between the two input comparison signals of the PFD is always changing, which means It also brings uncertainty to the selection of delay time. But from a macro point of view, the phase difference of the PFD input signal is zero after a long enough accumulation. Based on this point, ignoring the accumulation of phase difference and the adjustment effect of the phase-locked loop system on the phase difference, it is approximately considered that the input phase difference of the PFD is only related to the frequency division number of the current cycle. Since the frequency division numbers of common Σ-Δ fractional frequency synthesizers vary in a small range (for example, the output range of the MASH1-1-1 structure is -3~4, and the Single-loop four-digit three-order structure is -1~2), so the system After reaching the locked state, the time difference between the two input signals of the PFD will not exceed several VCO cycles, and the delay time slightly longer than this time can ensure that the frequency divider reads the correct frequency division number, and at the same time makes the phase comparison and digital circuit switch The flipping is staggered, so as to avoid the influence of the digital circuit switch flipping on the PFD. For example, the desired fractional frequency division value is 70.5, and the frequency division ratio of the frequency divider is 70 in a certain comparison period, the phase difference caused is 0.5 VCO oscillation period, so the DSM clock signal is delayed by half a VCO period It is possible to avoid the impact of digital switch flipping on the PFD. Considering the influence of other factors in the actual circuit, the delay time can be set slightly larger.

As shown in Figure 2, the delay unit 1 includes a frequency divider 2 and a delay circuit 3, wherein the input terminal of the frequency divider 2 receives the VCO signal sent by the external voltage controlled oscillator, and the input of the frequency divider 2 The terminal is also connected with the Σ-Δ modulator 4 to receive the signal it sends; the output terminal of the frequency divider 2 is respectively connected to an external PFD (phase frequency detector) and a delay circuit 3, and the delay circuit 3 is connected to the Σ-Δ modulator. 4 Output sigma-delta modulator clock signal.

As shown in FIG. 3 , the delay circuit 3 may be composed of an inverter chain composed of a plurality of NOT gates F. When the delay circuit 3 is composed of an inverter chain composed of a plurality of NOT gates F, the Σ-Δ modulator 4 is a Σ-Δ modulator with a MASH1-1-1 structure.

Implementations of the above delay techniques are discussed without considering the specific structure of the frequency divider. Among them, the DSM uses the MASH1-1-1 structure, and the delay unit is realized by an inverter chain.

After the VCO output signal is divided by the frequency divider, it is still divided into two channels, one is directly fed back to the PFD for phase comparison, and the other is input to the inverter chain, which is delayed and used as the clock signal of the DSM. The inverter chain should have an even number of stages, keeping the output in phase with the input signal.

In this scheme, the DSM output range of the MASH1-1-1 structure is -3 to 4. According to the estimation method of the above phase difference, in the worst case, the difference between the actual frequency division value and the expected value is 4, then the clock signal of the DSM must be delayed by at least 4 VCO cycle. Considering the influence of other factors in the actual circuit, the delay time can be set to 6 VCO cycle times. Taking the VCO output frequency as 2GHz as an example, it is necessary to design the inverter chain to generate a delay of about 3ns. Considering the parameters of the selected process and the structure of the actual circuit, by adjusting the size of the inverter and the number of stages of the inverter chain to control the delay time, the digital circuit switch of the DSM can be flipped after the phase comparison is completed by the PFD, so as to ensure the phase The accuracy of the comparison.

As shown in Figure 4, described frequency divider 2 can also be: comprise n/n+1 prescaler 5 and be connected with n/n+1 prescaler 5 and receive the P-S programming counter of its signal 6. The delay circuit 3 uses a TSPC-D flip-flop 7, wherein the input terminal of the n/n+1 prescaler 5 receives the VCO signal sent by the voltage-controlled oscillator, and the n/n+1 prescaler The device 5 sends a clock signal to the TSPC-D flip-flop 7, and the TSPC-D flip-flop 7 outputs the Σ-Δ modulator clock signal to the Σ-Δ modulator 4, and the output of the Σ-Δ modulator 4 is connected with the P-S programming counter 6; The output terminals of the P-S programming counter 6 are respectively connected to an external PFD (phase frequency detector) and TSPC-D flip-flop 7 .

In the case of this embodiment as shown in FIG. 4 , the Σ-Δ modulator 4 adopts a four-bit third-order modulator, and the prescaler 5 adopts a 7/8 prescaler 5 .

Above-mentioned embodiment, frequency divider utilizes prescaler (prescaler) and programming counter to realize, DSM adopts Single-loop four-bit three-stage structure, delay unit adopts TSPC (True Single Phase Clock, true single-phase clock) structure high-speed D flip-flop accomplish.

Due to the high output frequency of the frequency synthesizer, it is difficult for the general programming counter to divide it directly. Usually, it needs to pre-scale to obtain a signal with a lower frequency, and then divide it by the programming counter. For the frequency synthesizer whose output frequency reaches GHz, the signal frequency after pre-dividing is also in the order of hundreds of megahertz, which is still high, and the D flip-flop should adopt a high-speed flip-flop structure. Commonly used high-speed flip-flops mainly adopt structures such as TSPC and CML (Current Mode Logic, current mode logic), and the working frequency can reach several GHz. Since the CML structure D flip-flop requires a differential input signal, the delay unit in this scheme is implemented with a TSPC structure and only needs a single-phase clock. The VCO output signal is divided into two channels after frequency division by the prescaler, one channel is directly fed back to the PFD for phase comparison, that is, the Tdiv signal, and the other channel is used as the clock signal of the DSM through the TSPC-D flip-flop. Compared with the Tdiv signal, the DSM clock is delayed by one D flip-flop clock cycle, so selecting a suitable D flip-flop clock signal can achieve a proper delay, so that the DSM switch flip occurs after the PFD completes the phase comparison, thereby avoiding The effect of switch flipping on PFD is shown.

In this embodiment, the output range of the Single-loop four-bit three-order structure Σ-Δ modulator is -1˜2. Considering the worst case, the difference between the actual frequency division value and the expected value is 2, and the delay of the DSM clock is at least 2 VCO cycles, so as long as the prescaler can complete the frequency division by two times or more, then the TSPC-D The delay generated by the flip-flops guarantees the time for the DSM switch to flip to avoid the PFD phase comparison. The convenience of directly using the output signal of the prescaler as the clock of the TSPC-D flip-flop is that the existing signal in the original circuit structure is directly used without any additional circuit, which makes the circuit structure simple and easy to implement.

Take the 7/8 prescaler as an example, that is, the clock of the DSM is delayed by 7 or 8 VCO cycles. This delay time is enough to ensure that the flipping of the digital switch of the DSM will not affect the phase comparison of the PFD, effectively avoiding possible caused phase error.

Claims (6)

1. a Σ-Δ modulator clock control circuit in a Σ-Δ fractional frequency synthesizer, is characterized in that, comprises Σ-Δ modulator (4), receives the VCO signal that the voltage controlled oscillator of external connection sends over And a delay unit (1) receiving the signal sent by the sigma-delta modulator (4). 2. Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer according to claim 1, is characterized in that, described delay unit (1) comprises frequency divider (2) and delay circuit ( 3), wherein, the input terminal of the frequency divider (2) receives the VCO signal sent by the external voltage controlled oscillator, and the input terminal of the frequency divider (2) is also connected with the Σ-Δ modulator (4) to receive the signal sent by it. signal; the output end of the frequency divider (2) is respectively connected to an external PFD and a delay circuit (3), and the delay circuit (3) outputs a Σ-Δ modulator clock signal to the Σ-Δ modulator (4). 3. Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer according to claim 2, is characterized in that, described delay circuit (3) is the inverter that is made up of a plurality of NOT gates F chain composition. 4. Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer according to claim 3, is characterized in that, described Σ-Δ modulator (4) is the Σ of MASH1-1-1 structure - Delta modulator. 5. Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer according to claim 2, is characterized in that, described frequency divider (2) comprises n/n+1 prescaler (5) and the P-S programming counter (6) that is connected with n/n+1 prescaler (5) and receives its signal, and described delay circuit (3) adopts TSPC-D flip-flop (7), wherein, The input terminal of the n/n+1 prescaler (5) receives the VCO signal sent by the voltage controlled oscillator, and the n/n+1 prescaler (5) sends a clock signal to the TSPC-D flip-flop (7) , TSPC-D flip-flop (7) outputs Σ-Δ modulator clock signal to Σ-Δ modulator (4), and the output of Σ-Δ modulator (4) links to each other with P-S programming counter (6); Described P-S The output terminals of the programming counter (6) are respectively connected to the external PFD and TSPC-D flip-flops (7). 6. Σ-Δ modulator clock control circuit in the Σ-Δ fractional frequency synthesizer according to claim 5, is characterized in that, described Σ-Δ modulator (4) is Single-loop four three-order modulation device.

Images